Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. |
| 3 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * publishhed by the Free Software Foundation. |
| 8 | */ |
| 9 | #include "st-pincfg.h" |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 11 | / { |
| 12 | |
| 13 | aliases { |
| 14 | gpio0 = &PIO0; |
| 15 | gpio1 = &PIO1; |
| 16 | gpio2 = &PIO2; |
| 17 | gpio3 = &PIO3; |
| 18 | gpio4 = &PIO4; |
| 19 | gpio5 = &PIO5; |
| 20 | gpio6 = &PIO6; |
| 21 | gpio7 = &PIO7; |
| 22 | gpio8 = &PIO8; |
| 23 | gpio9 = &PIO9; |
| 24 | gpio10 = &PIO10; |
| 25 | gpio11 = &PIO11; |
| 26 | gpio12 = &PIO12; |
| 27 | gpio13 = &PIO13; |
| 28 | gpio14 = &PIO14; |
| 29 | gpio15 = &PIO15; |
| 30 | gpio16 = &PIO16; |
| 31 | gpio17 = &PIO17; |
| 32 | gpio18 = &PIO18; |
| 33 | gpio19 = &PIO100; |
| 34 | gpio20 = &PIO101; |
| 35 | gpio21 = &PIO102; |
| 36 | gpio22 = &PIO103; |
| 37 | gpio23 = &PIO104; |
| 38 | gpio24 = &PIO105; |
| 39 | gpio25 = &PIO106; |
| 40 | gpio26 = &PIO107; |
| 41 | }; |
| 42 | |
| 43 | soc { |
| 44 | pin-controller-sbc { |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <1>; |
| 47 | compatible = "st,stih415-sbc-pinctrl"; |
| 48 | st,syscfg = <&syscfg_sbc>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 49 | reg = <0xfe61f080 0x4>; |
| 50 | reg-names = "irqmux"; |
| 51 | interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 52 | interrupt-names = "irqmux"; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 53 | ranges = <0 0xfe610000 0x5000>; |
| 54 | |
| 55 | PIO0: gpio@fe610000 { |
| 56 | gpio-controller; |
| 57 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 58 | interrupt-controller; |
| 59 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 60 | reg = <0 0x100>; |
| 61 | st,bank-name = "PIO0"; |
| 62 | }; |
| 63 | PIO1: gpio@fe611000 { |
| 64 | gpio-controller; |
| 65 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 66 | interrupt-controller; |
| 67 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 68 | reg = <0x1000 0x100>; |
| 69 | st,bank-name = "PIO1"; |
| 70 | }; |
| 71 | PIO2: gpio@fe612000 { |
| 72 | gpio-controller; |
| 73 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 74 | interrupt-controller; |
| 75 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 76 | reg = <0x2000 0x100>; |
| 77 | st,bank-name = "PIO2"; |
| 78 | }; |
| 79 | PIO3: gpio@fe613000 { |
| 80 | gpio-controller; |
| 81 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 82 | interrupt-controller; |
| 83 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 84 | reg = <0x3000 0x100>; |
| 85 | st,bank-name = "PIO3"; |
| 86 | }; |
| 87 | PIO4: gpio@fe614000 { |
| 88 | gpio-controller; |
| 89 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 90 | interrupt-controller; |
| 91 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 92 | reg = <0x4000 0x100>; |
| 93 | st,bank-name = "PIO4"; |
| 94 | }; |
| 95 | |
| 96 | sbc_serial1 { |
| 97 | pinctrl_sbc_serial1:sbc_serial1 { |
| 98 | st,pins { |
| 99 | tx = <&PIO2 6 ALT3 OUT>; |
| 100 | rx = <&PIO2 7 ALT3 IN>; |
| 101 | }; |
| 102 | }; |
| 103 | }; |
Maxime COQUELIN | 5bbb752 | 2013-11-06 09:25:14 +0100 | [diff] [blame] | 104 | |
Gabriel FERNANDEZ | c316d7d | 2014-04-11 17:07:00 +0200 | [diff] [blame] | 105 | keyscan { |
| 106 | pinctrl_keyscan: keyscan { |
| 107 | st,pins { |
| 108 | keyin0 = <&PIO0 2 ALT2 IN>; |
| 109 | keyin1 = <&PIO0 3 ALT2 IN>; |
| 110 | keyin2 = <&PIO0 4 ALT2 IN>; |
| 111 | keyin3 = <&PIO2 6 ALT2 IN>; |
| 112 | |
| 113 | keyout0 = <&PIO1 6 ALT2 OUT>; |
| 114 | keyout1 = <&PIO1 7 ALT2 OUT>; |
| 115 | keyout2 = <&PIO0 6 ALT2 OUT>; |
| 116 | keyout3 = <&PIO2 7 ALT2 OUT>; |
| 117 | }; |
| 118 | }; |
| 119 | }; |
| 120 | |
Maxime COQUELIN | 5bbb752 | 2013-11-06 09:25:14 +0100 | [diff] [blame] | 121 | sbc_i2c0 { |
| 122 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { |
| 123 | st,pins { |
| 124 | sda = <&PIO4 6 ALT1 BIDIR>; |
| 125 | scl = <&PIO4 5 ALT1 BIDIR>; |
| 126 | }; |
| 127 | }; |
| 128 | }; |
| 129 | |
| 130 | sbc_i2c1 { |
| 131 | pinctrl_sbc_i2c1_default: sbc_i2c1-default { |
| 132 | st,pins { |
| 133 | sda = <&PIO3 2 ALT2 BIDIR>; |
| 134 | scl = <&PIO3 1 ALT2 BIDIR>; |
| 135 | }; |
| 136 | }; |
| 137 | }; |
Srinivas Kandagatla | c80fe335 | 2014-01-29 16:19:44 +0000 | [diff] [blame] | 138 | |
Srinivas Kandagatla | 8ccd3f3 | 2013-11-11 13:19:18 +0000 | [diff] [blame] | 139 | rc{ |
| 140 | pinctrl_ir: ir0 { |
| 141 | st,pins { |
| 142 | ir = <&PIO4 0 ALT2 IN>; |
| 143 | }; |
| 144 | }; |
| 145 | }; |
| 146 | |
Srinivas Kandagatla | c80fe335 | 2014-01-29 16:19:44 +0000 | [diff] [blame] | 147 | gmac1 { |
| 148 | pinctrl_mii1: mii1 { |
| 149 | st,pins { |
| 150 | txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 151 | txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 152 | txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 153 | txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 154 | txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 155 | txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
| 156 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; |
| 157 | col = <&PIO0 7 ALT1 IN BYPASS 1000>; |
| 158 | mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; |
| 159 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; |
| 160 | crs = <&PIO1 2 ALT1 IN BYPASS 1000>; |
| 161 | mdint = <&PIO1 3 ALT1 IN BYPASS 0>; |
| 162 | rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 163 | rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 164 | rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 165 | rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 166 | rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 167 | rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; |
| 168 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; |
| 169 | phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | pinctrl_rgmii1: rgmii1-0 { |
| 174 | st,pins { |
| 175 | txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; |
| 176 | txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; |
| 177 | txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; |
| 178 | txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; |
| 179 | txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; |
| 180 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; |
| 181 | mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; |
| 182 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; |
| 183 | rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; |
| 184 | rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; |
| 185 | rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; |
| 186 | rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; |
| 187 | |
| 188 | rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; |
| 189 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; |
| 190 | phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; |
| 191 | |
| 192 | clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; |
| 193 | }; |
| 194 | }; |
| 195 | }; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | pin-controller-front { |
| 199 | #address-cells = <1>; |
| 200 | #size-cells = <1>; |
| 201 | compatible = "st,stih415-front-pinctrl"; |
| 202 | st,syscfg = <&syscfg_front>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 203 | reg = <0xfee0f080 0x4>; |
| 204 | reg-names = "irqmux"; |
| 205 | interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 206 | interrupt-names = "irqmux"; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 207 | ranges = <0 0xfee00000 0x8000>; |
| 208 | |
| 209 | PIO5: gpio@fee00000 { |
| 210 | gpio-controller; |
| 211 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 212 | interrupt-controller; |
| 213 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 214 | reg = <0 0x100>; |
| 215 | st,bank-name = "PIO5"; |
| 216 | }; |
| 217 | PIO6: gpio@fee01000 { |
| 218 | gpio-controller; |
| 219 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 220 | interrupt-controller; |
| 221 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 222 | reg = <0x1000 0x100>; |
| 223 | st,bank-name = "PIO6"; |
| 224 | }; |
| 225 | PIO7: gpio@fee02000 { |
| 226 | gpio-controller; |
| 227 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 228 | interrupt-controller; |
| 229 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 230 | reg = <0x2000 0x100>; |
| 231 | st,bank-name = "PIO7"; |
| 232 | }; |
| 233 | PIO8: gpio@fee03000 { |
| 234 | gpio-controller; |
| 235 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 236 | interrupt-controller; |
| 237 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 238 | reg = <0x3000 0x100>; |
| 239 | st,bank-name = "PIO8"; |
| 240 | }; |
| 241 | PIO9: gpio@fee04000 { |
| 242 | gpio-controller; |
| 243 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 244 | interrupt-controller; |
| 245 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 246 | reg = <0x4000 0x100>; |
| 247 | st,bank-name = "PIO9"; |
| 248 | }; |
| 249 | PIO10: gpio@fee05000 { |
| 250 | gpio-controller; |
| 251 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 252 | interrupt-controller; |
| 253 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 254 | reg = <0x5000 0x100>; |
| 255 | st,bank-name = "PIO10"; |
| 256 | }; |
| 257 | PIO11: gpio@fee06000 { |
| 258 | gpio-controller; |
| 259 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 260 | interrupt-controller; |
| 261 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 262 | reg = <0x6000 0x100>; |
| 263 | st,bank-name = "PIO11"; |
| 264 | }; |
| 265 | PIO12: gpio@fee07000 { |
| 266 | gpio-controller; |
| 267 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 268 | interrupt-controller; |
| 269 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 270 | reg = <0x7000 0x100>; |
| 271 | st,bank-name = "PIO12"; |
| 272 | }; |
Maxime COQUELIN | 5bbb752 | 2013-11-06 09:25:14 +0100 | [diff] [blame] | 273 | |
| 274 | i2c0 { |
| 275 | pinctrl_i2c0_default: i2c0-default { |
| 276 | st,pins { |
| 277 | sda = <&PIO9 3 ALT1 BIDIR>; |
| 278 | scl = <&PIO9 2 ALT1 BIDIR>; |
| 279 | }; |
| 280 | }; |
| 281 | }; |
| 282 | |
| 283 | i2c1 { |
| 284 | pinctrl_i2c1_default: i2c1-default { |
| 285 | st,pins { |
| 286 | sda = <&PIO12 1 ALT1 BIDIR>; |
| 287 | scl = <&PIO12 0 ALT1 BIDIR>; |
| 288 | }; |
| 289 | }; |
| 290 | }; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | pin-controller-rear { |
| 294 | #address-cells = <1>; |
| 295 | #size-cells = <1>; |
| 296 | compatible = "st,stih415-rear-pinctrl"; |
| 297 | st,syscfg = <&syscfg_rear>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 298 | reg = <0xfe82f080 0x4>; |
| 299 | reg-names = "irqmux"; |
| 300 | interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 301 | interrupt-names = "irqmux"; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 302 | ranges = <0 0xfe820000 0x8000>; |
| 303 | |
| 304 | PIO13: gpio@fe820000 { |
| 305 | gpio-controller; |
| 306 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 307 | interrupt-controller; |
| 308 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 309 | reg = <0 0x100>; |
| 310 | st,bank-name = "PIO13"; |
| 311 | }; |
| 312 | PIO14: gpio@fe821000 { |
| 313 | gpio-controller; |
| 314 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 315 | interrupt-controller; |
| 316 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 317 | reg = <0x1000 0x100>; |
| 318 | st,bank-name = "PIO14"; |
| 319 | }; |
| 320 | PIO15: gpio@fe822000 { |
| 321 | gpio-controller; |
| 322 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 323 | interrupt-controller; |
| 324 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 325 | reg = <0x2000 0x100>; |
| 326 | st,bank-name = "PIO15"; |
| 327 | }; |
| 328 | PIO16: gpio@fe823000 { |
| 329 | gpio-controller; |
| 330 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 331 | interrupt-controller; |
| 332 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 333 | reg = <0x3000 0x100>; |
| 334 | st,bank-name = "PIO16"; |
| 335 | }; |
| 336 | PIO17: gpio@fe824000 { |
| 337 | gpio-controller; |
| 338 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 339 | interrupt-controller; |
| 340 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 341 | reg = <0x4000 0x100>; |
| 342 | st,bank-name = "PIO17"; |
| 343 | }; |
| 344 | PIO18: gpio@fe825000 { |
| 345 | gpio-controller; |
| 346 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 347 | interrupt-controller; |
| 348 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 349 | reg = <0x5000 0x100>; |
| 350 | st,bank-name = "PIO18"; |
| 351 | }; |
| 352 | |
| 353 | serial2 { |
| 354 | pinctrl_serial2: serial2-0 { |
| 355 | st,pins { |
| 356 | tx = <&PIO17 4 ALT2 OUT>; |
| 357 | rx = <&PIO17 5 ALT2 IN>; |
| 358 | }; |
| 359 | }; |
| 360 | }; |
Srinivas Kandagatla | c80fe335 | 2014-01-29 16:19:44 +0000 | [diff] [blame] | 361 | |
| 362 | gmac0{ |
| 363 | pinctrl_mii0: mii0 { |
| 364 | st,pins { |
| 365 | mdint = <&PIO13 6 ALT2 IN BYPASS 0>; |
| 366 | txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; |
| 367 | |
| 368 | txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; |
| 369 | txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; |
| 370 | txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; |
| 371 | txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; |
| 372 | |
| 373 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; |
| 374 | txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; |
| 375 | crs = <&PIO15 2 ALT2 IN BYPASS 1000>; |
| 376 | col = <&PIO15 3 ALT2 IN BYPASS 1000>; |
| 377 | mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; |
| 378 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; |
| 379 | |
| 380 | rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 381 | rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 382 | rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 383 | rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 384 | rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 385 | rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; |
| 386 | rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; |
| 387 | phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; |
| 388 | |
| 389 | }; |
| 390 | }; |
| 391 | |
| 392 | pinctrl_gmii0: gmii0 { |
| 393 | st,pins { |
| 394 | mdint = <&PIO13 6 ALT2 IN BYPASS 0>; |
| 395 | mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; |
| 396 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; |
| 397 | txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; |
| 398 | |
| 399 | txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; |
| 400 | txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; |
| 401 | txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 402 | txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 403 | txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 404 | txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 405 | txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 406 | txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; |
| 407 | |
| 408 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; |
| 409 | txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; |
| 410 | crs = <&PIO15 2 ALT2 IN BYPASS 1000>; |
| 411 | col = <&PIO15 3 ALT2 IN BYPASS 1000>; |
| 412 | rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 413 | rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 414 | |
| 415 | rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 416 | rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 417 | rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 418 | rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 419 | rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 420 | rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 421 | rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 422 | rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; |
| 423 | |
| 424 | rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; |
| 425 | clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; |
| 426 | phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; |
| 427 | |
| 428 | |
| 429 | }; |
| 430 | }; |
| 431 | }; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 432 | }; |
| 433 | |
| 434 | pin-controller-left { |
| 435 | #address-cells = <1>; |
| 436 | #size-cells = <1>; |
| 437 | compatible = "st,stih415-left-pinctrl"; |
| 438 | st,syscfg = <&syscfg_left>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 439 | reg = <0xfd6bf080 0x4>; |
| 440 | reg-names = "irqmux"; |
| 441 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 442 | interrupt-names = "irqmux"; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 443 | ranges = <0 0xfd6b0000 0x3000>; |
| 444 | |
| 445 | PIO100: gpio@fd6b0000 { |
| 446 | gpio-controller; |
| 447 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 448 | interrupt-controller; |
| 449 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 450 | reg = <0 0x100>; |
| 451 | st,bank-name = "PIO100"; |
| 452 | }; |
| 453 | PIO101: gpio@fd6b1000 { |
| 454 | gpio-controller; |
| 455 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 456 | interrupt-controller; |
| 457 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 458 | reg = <0x1000 0x100>; |
| 459 | st,bank-name = "PIO101"; |
| 460 | }; |
| 461 | PIO102: gpio@fd6b2000 { |
| 462 | gpio-controller; |
| 463 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 464 | interrupt-controller; |
| 465 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 466 | reg = <0x2000 0x100>; |
| 467 | st,bank-name = "PIO102"; |
| 468 | }; |
| 469 | }; |
| 470 | |
| 471 | pin-controller-right { |
| 472 | #address-cells = <1>; |
| 473 | #size-cells = <1>; |
| 474 | compatible = "st,stih415-right-pinctrl"; |
| 475 | st,syscfg = <&syscfg_right>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 476 | reg = <0xfd33f080 0x4>; |
| 477 | reg-names = "irqmux"; |
| 478 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 479 | interrupt-names = "irqmux"; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 480 | ranges = <0 0xfd330000 0x5000>; |
| 481 | |
| 482 | PIO103: gpio@fd330000 { |
| 483 | gpio-controller; |
| 484 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 485 | interrupt-controller; |
| 486 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 487 | reg = <0 0x100>; |
| 488 | st,bank-name = "PIO103"; |
| 489 | }; |
| 490 | PIO104: gpio@fd331000 { |
| 491 | gpio-controller; |
| 492 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 493 | interrupt-controller; |
| 494 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 495 | reg = <0x1000 0x100>; |
| 496 | st,bank-name = "PIO104"; |
| 497 | }; |
| 498 | PIO105: gpio@fd332000 { |
| 499 | gpio-controller; |
| 500 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 501 | interrupt-controller; |
| 502 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 503 | reg = <0x2000 0x100>; |
| 504 | st,bank-name = "PIO105"; |
| 505 | }; |
| 506 | PIO106: gpio@fd333000 { |
| 507 | gpio-controller; |
| 508 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 509 | interrupt-controller; |
| 510 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 511 | reg = <0x3000 0x100>; |
| 512 | st,bank-name = "PIO106"; |
| 513 | }; |
| 514 | PIO107: gpio@fd334000 { |
| 515 | gpio-controller; |
| 516 | #gpio-cells = <1>; |
Srinivas Kandagatla | 7ec5183 | 2014-01-08 12:49:57 +0000 | [diff] [blame] | 517 | interrupt-controller; |
| 518 | #interrupt-cells = <2>; |
Srinivas Kandagatla | 65ebcc1 | 2013-06-25 12:15:10 +0100 | [diff] [blame] | 519 | reg = <0x4000 0x100>; |
| 520 | st,bank-name = "PIO107"; |
| 521 | }; |
| 522 | }; |
| 523 | }; |
| 524 | }; |