Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
| 14 | /include/ "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | interrupt-parent = <&intc>; |
| 18 | |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 19 | aliases { |
| 20 | ethernet0 = &emac; |
Maxime Ripard | 4dd4065 | 2014-01-02 22:05:04 +0100 | [diff] [blame] | 21 | serial0 = &uart0; |
| 22 | serial1 = &uart1; |
| 23 | serial2 = &uart2; |
| 24 | serial3 = &uart3; |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 25 | }; |
| 26 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 27 | cpus { |
| 28 | cpu@0 { |
| 29 | compatible = "arm,cortex-a8"; |
| 30 | }; |
| 31 | }; |
| 32 | |
| 33 | memory { |
| 34 | reg = <0x40000000 0x20000000>; |
| 35 | }; |
| 36 | |
| 37 | clocks { |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | ranges; |
| 41 | |
| 42 | /* |
| 43 | * This is a dummy clock, to be used as placeholder on |
| 44 | * other mux clocks when a specific parent clock is not |
| 45 | * yet implemented. It should be dropped when the driver |
| 46 | * is complete. |
| 47 | */ |
| 48 | dummy: dummy { |
| 49 | #clock-cells = <0>; |
| 50 | compatible = "fixed-clock"; |
| 51 | clock-frequency = <0>; |
| 52 | }; |
| 53 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 54 | osc24M: clk@01c20050 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 55 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 56 | compatible = "allwinner,sun4i-a10-osc-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 57 | reg = <0x01c20050 0x4>; |
| 58 | clock-frequency = <24000000>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 59 | clock-output-names = "osc24M"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 60 | }; |
| 61 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 62 | osc32k: clk@0 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 63 | #clock-cells = <0>; |
| 64 | compatible = "fixed-clock"; |
| 65 | clock-frequency = <32768>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 66 | clock-output-names = "osc32k"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 67 | }; |
| 68 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 69 | pll1: clk@01c20000 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 70 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 71 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 72 | reg = <0x01c20000 0x4>; |
| 73 | clocks = <&osc24M>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 74 | clock-output-names = "pll1"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 75 | }; |
| 76 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 77 | pll4: clk@01c20018 { |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 78 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 79 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 80 | reg = <0x01c20018 0x4>; |
| 81 | clocks = <&osc24M>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 82 | clock-output-names = "pll4"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 83 | }; |
| 84 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 85 | pll5: clk@01c20020 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 86 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 87 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 88 | reg = <0x01c20020 0x4>; |
| 89 | clocks = <&osc24M>; |
| 90 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 91 | }; |
| 92 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 93 | pll6: clk@01c20028 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 94 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 95 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 96 | reg = <0x01c20028 0x4>; |
| 97 | clocks = <&osc24M>; |
| 98 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| 99 | }; |
| 100 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 101 | /* dummy is 200M */ |
| 102 | cpu: cpu@01c20054 { |
| 103 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 104 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 105 | reg = <0x01c20054 0x4>; |
| 106 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 107 | clock-output-names = "cpu"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | axi: axi@01c20054 { |
| 111 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 112 | compatible = "allwinner,sun4i-a10-axi-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 113 | reg = <0x01c20054 0x4>; |
| 114 | clocks = <&cpu>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 115 | clock-output-names = "axi"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 116 | }; |
| 117 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 118 | axi_gates: clk@01c2005c { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 119 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 120 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 121 | reg = <0x01c2005c 0x4>; |
| 122 | clocks = <&axi>; |
| 123 | clock-output-names = "axi_dram"; |
| 124 | }; |
| 125 | |
| 126 | ahb: ahb@01c20054 { |
| 127 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 128 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 129 | reg = <0x01c20054 0x4>; |
| 130 | clocks = <&axi>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 131 | clock-output-names = "ahb"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 132 | }; |
| 133 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 134 | ahb_gates: clk@01c20060 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 135 | #clock-cells = <1>; |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 136 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 137 | reg = <0x01c20060 0x8>; |
| 138 | clocks = <&ahb>; |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 139 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 140 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 141 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", |
| 142 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", |
| 143 | "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", |
| 144 | "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", |
| 145 | "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | apb0: apb0@01c20054 { |
| 149 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 151 | reg = <0x01c20054 0x4>; |
| 152 | clocks = <&ahb>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 153 | clock-output-names = "apb0"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 154 | }; |
| 155 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 156 | apb0_gates: clk@01c20068 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 157 | #clock-cells = <1>; |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 158 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 159 | reg = <0x01c20068 0x4>; |
| 160 | clocks = <&apb0>; |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 161 | clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", |
| 162 | "apb0_ir", "apb0_keypad"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 163 | }; |
| 164 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 165 | apb1_mux: apb1_mux@01c20058 { |
| 166 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 167 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 168 | reg = <0x01c20058 0x4>; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 169 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 170 | clock-output-names = "apb1_mux"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | apb1: apb1@01c20058 { |
| 174 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 175 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 176 | reg = <0x01c20058 0x4>; |
| 177 | clocks = <&apb1_mux>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 178 | clock-output-names = "apb1"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 179 | }; |
| 180 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 181 | apb1_gates: clk@01c2006c { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 182 | #clock-cells = <1>; |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 183 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 184 | reg = <0x01c2006c 0x4>; |
| 185 | clocks = <&apb1>; |
| 186 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
Maxime Ripard | 29bb805 | 2013-07-16 11:28:58 +0200 | [diff] [blame] | 187 | "apb1_i2c2", "apb1_uart0", "apb1_uart1", |
| 188 | "apb1_uart2", "apb1_uart3"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 189 | }; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 190 | |
| 191 | nand_clk: clk@01c20080 { |
| 192 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 193 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 194 | reg = <0x01c20080 0x4>; |
| 195 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 196 | clock-output-names = "nand"; |
| 197 | }; |
| 198 | |
| 199 | ms_clk: clk@01c20084 { |
| 200 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 201 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 202 | reg = <0x01c20084 0x4>; |
| 203 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 204 | clock-output-names = "ms"; |
| 205 | }; |
| 206 | |
| 207 | mmc0_clk: clk@01c20088 { |
| 208 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 209 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 210 | reg = <0x01c20088 0x4>; |
| 211 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 212 | clock-output-names = "mmc0"; |
| 213 | }; |
| 214 | |
| 215 | mmc1_clk: clk@01c2008c { |
| 216 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 217 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 218 | reg = <0x01c2008c 0x4>; |
| 219 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 220 | clock-output-names = "mmc1"; |
| 221 | }; |
| 222 | |
| 223 | mmc2_clk: clk@01c20090 { |
| 224 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 225 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 226 | reg = <0x01c20090 0x4>; |
| 227 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 228 | clock-output-names = "mmc2"; |
| 229 | }; |
| 230 | |
| 231 | ts_clk: clk@01c20098 { |
| 232 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 233 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 234 | reg = <0x01c20098 0x4>; |
| 235 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 236 | clock-output-names = "ts"; |
| 237 | }; |
| 238 | |
| 239 | ss_clk: clk@01c2009c { |
| 240 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 241 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 242 | reg = <0x01c2009c 0x4>; |
| 243 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 244 | clock-output-names = "ss"; |
| 245 | }; |
| 246 | |
| 247 | spi0_clk: clk@01c200a0 { |
| 248 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 249 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 250 | reg = <0x01c200a0 0x4>; |
| 251 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 252 | clock-output-names = "spi0"; |
| 253 | }; |
| 254 | |
| 255 | spi1_clk: clk@01c200a4 { |
| 256 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 258 | reg = <0x01c200a4 0x4>; |
| 259 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 260 | clock-output-names = "spi1"; |
| 261 | }; |
| 262 | |
| 263 | spi2_clk: clk@01c200a8 { |
| 264 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 266 | reg = <0x01c200a8 0x4>; |
| 267 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 268 | clock-output-names = "spi2"; |
| 269 | }; |
| 270 | |
| 271 | ir0_clk: clk@01c200b0 { |
| 272 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 274 | reg = <0x01c200b0 0x4>; |
| 275 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 276 | clock-output-names = "ir0"; |
| 277 | }; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 278 | |
Roman Byshko | 4c5d72f | 2014-02-07 16:21:52 +0100 | [diff] [blame] | 279 | usb_clk: clk@01c200cc { |
| 280 | #clock-cells = <1>; |
| 281 | #reset-cells = <1>; |
| 282 | compatible = "allwinner,sun5i-a13-usb-clk"; |
| 283 | reg = <0x01c200cc 0x4>; |
| 284 | clocks = <&pll6 1>; |
| 285 | clock-output-names = "usb_ohci0", "usb_phy"; |
| 286 | }; |
| 287 | |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 288 | mbus_clk: clk@01c2015c { |
| 289 | #clock-cells = <0>; |
Maxime Ripard | 7868c5e | 2014-07-16 23:45:48 +0200 | [diff] [blame] | 290 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 291 | reg = <0x01c2015c 0x4>; |
| 292 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 293 | clock-output-names = "mbus"; |
| 294 | }; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 295 | }; |
| 296 | |
Maxime Ripard | 9e19929 | 2013-08-03 16:07:36 +0200 | [diff] [blame] | 297 | soc@01c00000 { |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 298 | compatible = "simple-bus"; |
| 299 | #address-cells = <1>; |
| 300 | #size-cells = <1>; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 301 | ranges; |
| 302 | |
Emilio López | 6a5775e | 2014-08-04 17:09:58 -0300 | [diff] [blame] | 303 | dma: dma-controller@01c02000 { |
| 304 | compatible = "allwinner,sun4i-a10-dma"; |
| 305 | reg = <0x01c02000 0x1000>; |
| 306 | interrupts = <27>; |
| 307 | clocks = <&ahb_gates 6>; |
| 308 | #dma-cells = <2>; |
| 309 | }; |
| 310 | |
Maxime Ripard | 8a68956 | 2014-02-22 22:35:56 +0100 | [diff] [blame] | 311 | spi0: spi@01c05000 { |
| 312 | compatible = "allwinner,sun4i-a10-spi"; |
| 313 | reg = <0x01c05000 0x1000>; |
| 314 | interrupts = <10>; |
| 315 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
| 316 | clock-names = "ahb", "mod"; |
Emilio López | fed4c5c | 2014-08-04 17:10:01 -0300 | [diff] [blame] | 317 | dmas = <&dma 1 27>, <&dma 1 26>; |
| 318 | dma-names = "rx", "tx"; |
Maxime Ripard | 8a68956 | 2014-02-22 22:35:56 +0100 | [diff] [blame] | 319 | status = "disabled"; |
| 320 | #address-cells = <1>; |
| 321 | #size-cells = <0>; |
| 322 | }; |
| 323 | |
| 324 | spi1: spi@01c06000 { |
| 325 | compatible = "allwinner,sun4i-a10-spi"; |
| 326 | reg = <0x01c06000 0x1000>; |
| 327 | interrupts = <11>; |
| 328 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
| 329 | clock-names = "ahb", "mod"; |
Emilio López | fed4c5c | 2014-08-04 17:10:01 -0300 | [diff] [blame] | 330 | dmas = <&dma 1 9>, <&dma 1 8>; |
| 331 | dma-names = "rx", "tx"; |
Maxime Ripard | 8a68956 | 2014-02-22 22:35:56 +0100 | [diff] [blame] | 332 | status = "disabled"; |
| 333 | #address-cells = <1>; |
| 334 | #size-cells = <0>; |
| 335 | }; |
| 336 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 337 | emac: ethernet@01c0b000 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 338 | compatible = "allwinner,sun4i-a10-emac"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 339 | reg = <0x01c0b000 0x1000>; |
| 340 | interrupts = <55>; |
| 341 | clocks = <&ahb_gates 17>; |
| 342 | status = "disabled"; |
| 343 | }; |
| 344 | |
| 345 | mdio@01c0b080 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 346 | compatible = "allwinner,sun4i-a10-mdio"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 347 | reg = <0x01c0b080 0x14>; |
| 348 | status = "disabled"; |
| 349 | #address-cells = <1>; |
| 350 | #size-cells = <0>; |
| 351 | }; |
| 352 | |
David Lanzendörfer | d3aed1d | 2014-05-02 17:57:21 +0200 | [diff] [blame] | 353 | mmc0: mmc@01c0f000 { |
| 354 | compatible = "allwinner,sun5i-a13-mmc"; |
| 355 | reg = <0x01c0f000 0x1000>; |
| 356 | clocks = <&ahb_gates 8>, <&mmc0_clk>; |
| 357 | clock-names = "ahb", "mmc"; |
| 358 | interrupts = <32>; |
| 359 | status = "disabled"; |
| 360 | }; |
| 361 | |
| 362 | mmc1: mmc@01c10000 { |
| 363 | compatible = "allwinner,sun5i-a13-mmc"; |
| 364 | reg = <0x01c10000 0x1000>; |
| 365 | clocks = <&ahb_gates 9>, <&mmc1_clk>; |
| 366 | clock-names = "ahb", "mmc"; |
| 367 | interrupts = <33>; |
| 368 | status = "disabled"; |
| 369 | }; |
| 370 | |
| 371 | mmc2: mmc@01c11000 { |
| 372 | compatible = "allwinner,sun5i-a13-mmc"; |
| 373 | reg = <0x01c11000 0x1000>; |
| 374 | clocks = <&ahb_gates 10>, <&mmc2_clk>; |
| 375 | clock-names = "ahb", "mmc"; |
| 376 | interrupts = <34>; |
| 377 | status = "disabled"; |
| 378 | }; |
| 379 | |
Roman Byshko | 06c7d52 | 2014-03-01 20:26:24 +0100 | [diff] [blame] | 380 | usbphy: phy@01c13400 { |
| 381 | #phy-cells = <1>; |
| 382 | compatible = "allwinner,sun5i-a13-usb-phy"; |
| 383 | reg = <0x01c13400 0x10 0x01c14800 0x4>; |
| 384 | reg-names = "phy_ctrl", "pmu1"; |
| 385 | clocks = <&usb_clk 8>; |
| 386 | clock-names = "usb_phy"; |
| 387 | resets = <&usb_clk 1>; |
| 388 | reset-names = "usb1_reset"; |
| 389 | status = "disabled"; |
| 390 | }; |
| 391 | |
| 392 | ehci0: usb@01c14000 { |
| 393 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; |
| 394 | reg = <0x01c14000 0x100>; |
| 395 | interrupts = <39>; |
| 396 | clocks = <&ahb_gates 1>; |
| 397 | phys = <&usbphy 1>; |
| 398 | phy-names = "usb"; |
| 399 | status = "disabled"; |
| 400 | }; |
| 401 | |
| 402 | ohci0: usb@01c14400 { |
| 403 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; |
| 404 | reg = <0x01c14400 0x100>; |
| 405 | interrupts = <40>; |
| 406 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
| 407 | phys = <&usbphy 1>; |
| 408 | phy-names = "usb"; |
| 409 | status = "disabled"; |
| 410 | }; |
| 411 | |
Maxime Ripard | 8a68956 | 2014-02-22 22:35:56 +0100 | [diff] [blame] | 412 | spi2: spi@01c17000 { |
| 413 | compatible = "allwinner,sun4i-a10-spi"; |
| 414 | reg = <0x01c17000 0x1000>; |
| 415 | interrupts = <12>; |
| 416 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
| 417 | clock-names = "ahb", "mod"; |
Emilio López | fed4c5c | 2014-08-04 17:10:01 -0300 | [diff] [blame] | 418 | dmas = <&dma 1 29>, <&dma 1 28>; |
| 419 | dma-names = "rx", "tx"; |
Maxime Ripard | 8a68956 | 2014-02-22 22:35:56 +0100 | [diff] [blame] | 420 | status = "disabled"; |
| 421 | #address-cells = <1>; |
| 422 | #size-cells = <0>; |
| 423 | }; |
| 424 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 425 | intc: interrupt-controller@01c20400 { |
Maxime Ripard | 09504a7 | 2014-02-07 21:50:26 +0100 | [diff] [blame] | 426 | compatible = "allwinner,sun4i-a10-ic"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 427 | reg = <0x01c20400 0x400>; |
| 428 | interrupt-controller; |
| 429 | #interrupt-cells = <1>; |
| 430 | }; |
| 431 | |
| 432 | pio: pinctrl@01c20800 { |
| 433 | compatible = "allwinner,sun5i-a10s-pinctrl"; |
| 434 | reg = <0x01c20800 0x400>; |
| 435 | interrupts = <28>; |
| 436 | clocks = <&apb0_gates 5>; |
| 437 | gpio-controller; |
| 438 | interrupt-controller; |
Chen-Yu Tsai | 7d4ff96 | 2014-06-30 23:57:51 +0200 | [diff] [blame] | 439 | #interrupt-cells = <2>; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 440 | #size-cells = <0>; |
| 441 | #gpio-cells = <3>; |
| 442 | |
| 443 | uart0_pins_a: uart0@0 { |
| 444 | allwinner,pins = "PB19", "PB20"; |
| 445 | allwinner,function = "uart0"; |
| 446 | allwinner,drive = <0>; |
| 447 | allwinner,pull = <0>; |
| 448 | }; |
| 449 | |
| 450 | uart2_pins_a: uart2@0 { |
| 451 | allwinner,pins = "PC18", "PC19"; |
| 452 | allwinner,function = "uart2"; |
| 453 | allwinner,drive = <0>; |
| 454 | allwinner,pull = <0>; |
| 455 | }; |
| 456 | |
| 457 | uart3_pins_a: uart3@0 { |
| 458 | allwinner,pins = "PG9", "PG10"; |
| 459 | allwinner,function = "uart3"; |
| 460 | allwinner,drive = <0>; |
| 461 | allwinner,pull = <0>; |
| 462 | }; |
| 463 | |
| 464 | emac_pins_a: emac0@0 { |
| 465 | allwinner,pins = "PA0", "PA1", "PA2", |
| 466 | "PA3", "PA4", "PA5", "PA6", |
| 467 | "PA7", "PA8", "PA9", "PA10", |
| 468 | "PA11", "PA12", "PA13", "PA14", |
| 469 | "PA15", "PA16"; |
| 470 | allwinner,function = "emac"; |
| 471 | allwinner,drive = <0>; |
| 472 | allwinner,pull = <0>; |
| 473 | }; |
Emilio López | 170ab43 | 2013-07-07 18:31:56 -0300 | [diff] [blame] | 474 | |
| 475 | i2c0_pins_a: i2c0@0 { |
| 476 | allwinner,pins = "PB0", "PB1"; |
| 477 | allwinner,function = "i2c0"; |
| 478 | allwinner,drive = <0>; |
| 479 | allwinner,pull = <0>; |
| 480 | }; |
| 481 | |
| 482 | i2c1_pins_a: i2c1@0 { |
| 483 | allwinner,pins = "PB15", "PB16"; |
| 484 | allwinner,function = "i2c1"; |
| 485 | allwinner,drive = <0>; |
| 486 | allwinner,pull = <0>; |
| 487 | }; |
| 488 | |
| 489 | i2c2_pins_a: i2c2@0 { |
| 490 | allwinner,pins = "PB17", "PB18"; |
| 491 | allwinner,function = "i2c2"; |
| 492 | allwinner,drive = <0>; |
| 493 | allwinner,pull = <0>; |
| 494 | }; |
Hans de Goede | 6da50f1 | 2014-04-26 12:16:12 +0200 | [diff] [blame] | 495 | |
| 496 | mmc0_pins_a: mmc0@0 { |
| 497 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; |
| 498 | allwinner,function = "mmc0"; |
| 499 | allwinner,drive = <2>; |
| 500 | allwinner,pull = <0>; |
| 501 | }; |
| 502 | |
| 503 | mmc1_pins_a: mmc1@0 { |
| 504 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; |
| 505 | allwinner,function = "mmc1"; |
| 506 | allwinner,drive = <2>; |
| 507 | allwinner,pull = <0>; |
| 508 | }; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 509 | }; |
| 510 | |
| 511 | timer@01c20c00 { |
Maxime Ripard | b4f2644 | 2014-02-06 10:40:32 +0100 | [diff] [blame] | 512 | compatible = "allwinner,sun4i-a10-timer"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 513 | reg = <0x01c20c00 0x90>; |
| 514 | interrupts = <22>; |
| 515 | clocks = <&osc24M>; |
| 516 | }; |
| 517 | |
| 518 | wdt: watchdog@01c20c90 { |
Maxime Ripard | ca5d04d | 2014-02-07 22:29:26 +0100 | [diff] [blame] | 519 | compatible = "allwinner,sun4i-a10-wdt"; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 520 | reg = <0x01c20c90 0x10>; |
| 521 | }; |
| 522 | |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 523 | sid: eeprom@01c23800 { |
Maxime Ripard | 043d56e | 2014-02-07 22:20:40 +0100 | [diff] [blame] | 524 | compatible = "allwinner,sun4i-a10-sid"; |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 525 | reg = <0x01c23800 0x10>; |
| 526 | }; |
| 527 | |
Hans de Goede | f65c93a | 2013-12-31 17:20:51 +0100 | [diff] [blame] | 528 | rtp: rtp@01c25000 { |
Maxime Ripard | 40dd8f3 | 2014-02-02 14:52:40 +0100 | [diff] [blame] | 529 | compatible = "allwinner,sun4i-a10-ts"; |
Hans de Goede | f65c93a | 2013-12-31 17:20:51 +0100 | [diff] [blame] | 530 | reg = <0x01c25000 0x100>; |
| 531 | interrupts = <29>; |
| 532 | }; |
| 533 | |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 534 | uart0: serial@01c28000 { |
| 535 | compatible = "snps,dw-apb-uart"; |
| 536 | reg = <0x01c28000 0x400>; |
| 537 | interrupts = <1>; |
| 538 | reg-shift = <2>; |
| 539 | reg-io-width = <4>; |
| 540 | clocks = <&apb1_gates 16>; |
| 541 | status = "disabled"; |
| 542 | }; |
| 543 | |
| 544 | uart1: serial@01c28400 { |
| 545 | compatible = "snps,dw-apb-uart"; |
| 546 | reg = <0x01c28400 0x400>; |
| 547 | interrupts = <2>; |
| 548 | reg-shift = <2>; |
| 549 | reg-io-width = <4>; |
| 550 | clocks = <&apb1_gates 17>; |
| 551 | status = "disabled"; |
| 552 | }; |
| 553 | |
| 554 | uart2: serial@01c28800 { |
| 555 | compatible = "snps,dw-apb-uart"; |
| 556 | reg = <0x01c28800 0x400>; |
| 557 | interrupts = <3>; |
| 558 | reg-shift = <2>; |
| 559 | reg-io-width = <4>; |
| 560 | clocks = <&apb1_gates 18>; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | |
| 564 | uart3: serial@01c28c00 { |
| 565 | compatible = "snps,dw-apb-uart"; |
| 566 | reg = <0x01c28c00 0x400>; |
| 567 | interrupts = <4>; |
| 568 | reg-shift = <2>; |
| 569 | reg-io-width = <4>; |
| 570 | clocks = <&apb1_gates 19>; |
| 571 | status = "disabled"; |
| 572 | }; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 573 | |
| 574 | i2c0: i2c@01c2ac00 { |
| 575 | #address-cells = <1>; |
| 576 | #size-cells = <0>; |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 577 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 578 | reg = <0x01c2ac00 0x400>; |
| 579 | interrupts = <7>; |
| 580 | clocks = <&apb1_gates 0>; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 581 | status = "disabled"; |
| 582 | }; |
| 583 | |
| 584 | i2c1: i2c@01c2b000 { |
| 585 | #address-cells = <1>; |
| 586 | #size-cells = <0>; |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 587 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 588 | reg = <0x01c2b000 0x400>; |
| 589 | interrupts = <8>; |
| 590 | clocks = <&apb1_gates 1>; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 591 | status = "disabled"; |
| 592 | }; |
| 593 | |
| 594 | i2c2: i2c@01c2b400 { |
| 595 | #address-cells = <1>; |
| 596 | #size-cells = <0>; |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 597 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 598 | reg = <0x01c2b400 0x400>; |
| 599 | interrupts = <9>; |
| 600 | clocks = <&apb1_gates 2>; |
Emilio López | ca3d4ed | 2013-07-07 18:31:57 -0300 | [diff] [blame] | 601 | status = "disabled"; |
| 602 | }; |
Maxime Ripard | f2b5002 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 603 | |
| 604 | timer@01c60000 { |
| 605 | compatible = "allwinner,sun5i-a13-hstimer"; |
| 606 | reg = <0x01c60000 0x1000>; |
| 607 | interrupts = <82>, <83>; |
| 608 | clocks = <&ahb_gates 28>; |
| 609 | }; |
Maxime Ripard | d3ae078 | 2013-06-09 10:40:53 +0200 | [diff] [blame] | 610 | }; |
| 611 | }; |