Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra20-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 5 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 6 | #include "skeleton.dtsi" |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 7 | |
| 8 | / { |
| 9 | compatible = "nvidia,tegra20"; |
| 10 | interrupt-parent = <&intc>; |
| 11 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 12 | aliases { |
| 13 | serial0 = &uarta; |
| 14 | serial1 = &uartb; |
| 15 | serial2 = &uartc; |
| 16 | serial3 = &uartd; |
| 17 | serial4 = &uarte; |
| 18 | }; |
| 19 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 20 | host1x@50000000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 21 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
| 22 | reg = <0x50000000 0x00024000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 23 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 24 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 25 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 26 | resets = <&tegra_car 28>; |
| 27 | reset-names = "host1x"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 33 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 34 | mpe@54040000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 35 | compatible = "nvidia,tegra20-mpe"; |
| 36 | reg = <0x54040000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 37 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 38 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 39 | resets = <&tegra_car 60>; |
| 40 | reset-names = "mpe"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 41 | }; |
| 42 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 43 | vi@54080000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 44 | compatible = "nvidia,tegra20-vi"; |
| 45 | reg = <0x54080000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 46 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 47 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 48 | resets = <&tegra_car 20>; |
| 49 | reset-names = "vi"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 50 | }; |
| 51 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 52 | epp@540c0000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 53 | compatible = "nvidia,tegra20-epp"; |
| 54 | reg = <0x540c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 55 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 56 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 57 | resets = <&tegra_car 19>; |
| 58 | reset-names = "epp"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 59 | }; |
| 60 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 61 | isp@54100000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 62 | compatible = "nvidia,tegra20-isp"; |
| 63 | reg = <0x54100000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 64 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 65 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 66 | resets = <&tegra_car 23>; |
| 67 | reset-names = "isp"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 68 | }; |
| 69 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 70 | gr2d@54140000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 71 | compatible = "nvidia,tegra20-gr2d"; |
| 72 | reg = <0x54140000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 73 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 74 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 75 | resets = <&tegra_car 21>; |
| 76 | reset-names = "2d"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 77 | }; |
| 78 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 79 | gr3d@54140000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 80 | compatible = "nvidia,tegra20-gr3d"; |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 81 | reg = <0x54140000 0x00040000>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 82 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 83 | resets = <&tegra_car 24>; |
| 84 | reset-names = "3d"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | dc@54200000 { |
| 88 | compatible = "nvidia,tegra20-dc"; |
| 89 | reg = <0x54200000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 90 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 91 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
| 92 | <&tegra_car TEGRA20_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 93 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 94 | resets = <&tegra_car 27>; |
| 95 | reset-names = "dc"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 96 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 97 | nvidia,head = <0>; |
| 98 | |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 99 | rgb { |
| 100 | status = "disabled"; |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | dc@54240000 { |
| 105 | compatible = "nvidia,tegra20-dc"; |
| 106 | reg = <0x54240000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 107 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 108 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
| 109 | <&tegra_car TEGRA20_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 110 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 111 | resets = <&tegra_car 26>; |
| 112 | reset-names = "dc"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 113 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 114 | nvidia,head = <1>; |
| 115 | |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 116 | rgb { |
| 117 | status = "disabled"; |
| 118 | }; |
| 119 | }; |
| 120 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 121 | hdmi@54280000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 122 | compatible = "nvidia,tegra20-hdmi"; |
| 123 | reg = <0x54280000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 124 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 125 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
| 126 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; |
Prashant Gaikwad | 8d8b43d | 2013-01-11 13:31:21 +0530 | [diff] [blame] | 127 | clock-names = "hdmi", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 128 | resets = <&tegra_car 51>; |
| 129 | reset-names = "hdmi"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 130 | status = "disabled"; |
| 131 | }; |
| 132 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 133 | tvo@542c0000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 134 | compatible = "nvidia,tegra20-tvo"; |
| 135 | reg = <0x542c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 136 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 137 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 138 | status = "disabled"; |
| 139 | }; |
| 140 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 141 | dsi@542c0000 { |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 142 | compatible = "nvidia,tegra20-dsi"; |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 143 | reg = <0x542c0000 0x00040000>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 144 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 145 | resets = <&tegra_car 48>; |
| 146 | reset-names = "dsi"; |
Thierry Reding | ed821f0 | 2012-11-15 22:07:54 +0100 | [diff] [blame] | 147 | status = "disabled"; |
| 148 | }; |
| 149 | }; |
| 150 | |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 151 | timer@50004600 { |
| 152 | compatible = "arm,cortex-a9-twd-timer"; |
| 153 | reg = <0x50040600 0x20>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 154 | interrupts = <GIC_PPI 13 |
| 155 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 156 | clocks = <&tegra_car TEGRA20_CLK_TWD>; |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 157 | }; |
| 158 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 159 | intc: interrupt-controller@50041000 { |
pdeschrijver@nvidia.com | 0d4f747 | 2011-11-29 18:29:19 -0700 | [diff] [blame] | 160 | compatible = "arm,cortex-a9-gic"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 161 | reg = <0x50041000 0x1000 |
| 162 | 0x50040100 0x0100>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 163 | interrupt-controller; |
| 164 | #interrupt-cells = <3>; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 165 | }; |
| 166 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 167 | cache-controller@50043000 { |
Stephen Warren | bb2c1de | 2013-01-14 10:09:16 -0700 | [diff] [blame] | 168 | compatible = "arm,pl310-cache"; |
| 169 | reg = <0x50043000 0x1000>; |
| 170 | arm,data-latency = <5 5 2>; |
| 171 | arm,tag-latency = <4 4 2>; |
| 172 | cache-unified; |
| 173 | cache-level = <2>; |
| 174 | }; |
| 175 | |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 176 | timer@60005000 { |
| 177 | compatible = "nvidia,tegra20-timer"; |
| 178 | reg = <0x60005000 0x60>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 179 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 180 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 181 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 182 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 183 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 184 | }; |
| 185 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 186 | tegra_car: clock@60006000 { |
Stephen Warren | 270f8ce | 2013-01-11 13:16:22 +0530 | [diff] [blame] | 187 | compatible = "nvidia,tegra20-car"; |
| 188 | reg = <0x60006000 0x1000>; |
| 189 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 190 | #reset-cells = <1>; |
Stephen Warren | 270f8ce | 2013-01-11 13:16:22 +0530 | [diff] [blame] | 191 | }; |
| 192 | |
Thierry Reding | b102313 | 2014-08-26 08:14:03 +0200 | [diff] [blame] | 193 | flow-controller@60007000 { |
| 194 | compatible = "nvidia,tegra20-flowctrl"; |
| 195 | reg = <0x60007000 0x1000>; |
| 196 | }; |
| 197 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 198 | apbdma: dma@6000a000 { |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 199 | compatible = "nvidia,tegra20-apbdma"; |
| 200 | reg = <0x6000a000 0x1200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 201 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 202 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 203 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 204 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 205 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 206 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 209 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 211 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 212 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 213 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 214 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 215 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 216 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 217 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 218 | resets = <&tegra_car 34>; |
| 219 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 220 | #dma-cells = <1>; |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 221 | }; |
| 222 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 223 | ahb@6000c004 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 224 | compatible = "nvidia,tegra20-ahb"; |
| 225 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 226 | }; |
| 227 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 228 | gpio: gpio@6000d000 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 229 | compatible = "nvidia,tegra20-gpio"; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 230 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 231 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 232 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 233 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 234 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 235 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 236 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 237 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 238 | #gpio-cells = <2>; |
| 239 | gpio-controller; |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 240 | #interrupt-cells = <2>; |
| 241 | interrupt-controller; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 242 | }; |
| 243 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 244 | apbmisc@70000800 { |
| 245 | compatible = "nvidia,tegra20-apbmisc"; |
| 246 | reg = <0x70000800 0x64 /* Chip revision */ |
| 247 | 0x70000008 0x04>; /* Strapping options */ |
| 248 | }; |
| 249 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 250 | pinmux: pinmux@70000014 { |
Stephen Warren | f62f548 | 2011-10-11 16:16:13 -0600 | [diff] [blame] | 251 | compatible = "nvidia,tegra20-pinmux"; |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 252 | reg = <0x70000014 0x10 /* Tri-state registers */ |
| 253 | 0x70000080 0x20 /* Mux registers */ |
| 254 | 0x700000a0 0x14 /* Pull-up/down registers */ |
| 255 | 0x70000868 0xa8>; /* Pad control registers */ |
Stephen Warren | f62f548 | 2011-10-11 16:16:13 -0600 | [diff] [blame] | 256 | }; |
| 257 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 258 | das@70000c00 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 259 | compatible = "nvidia,tegra20-das"; |
| 260 | reg = <0x70000c00 0x80>; |
| 261 | }; |
Stephen Warren | fc5c306 | 2013-03-06 11:28:32 -0700 | [diff] [blame] | 262 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 263 | tegra_ac97: ac97@70002000 { |
Lucas Stach | 0698ed1 | 2013-01-05 02:18:44 +0100 | [diff] [blame] | 264 | compatible = "nvidia,tegra20-ac97"; |
| 265 | reg = <0x70002000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 266 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 267 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 268 | resets = <&tegra_car 3>; |
| 269 | reset-names = "ac97"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 270 | dmas = <&apbdma 12>, <&apbdma 12>; |
| 271 | dma-names = "rx", "tx"; |
Lucas Stach | 0698ed1 | 2013-01-05 02:18:44 +0100 | [diff] [blame] | 272 | status = "disabled"; |
| 273 | }; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 274 | |
| 275 | tegra_i2s1: i2s@70002800 { |
| 276 | compatible = "nvidia,tegra20-i2s"; |
| 277 | reg = <0x70002800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 278 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 279 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 280 | resets = <&tegra_car 11>; |
| 281 | reset-names = "i2s"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 282 | dmas = <&apbdma 2>, <&apbdma 2>; |
| 283 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 284 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | tegra_i2s2: i2s@70002a00 { |
| 288 | compatible = "nvidia,tegra20-i2s"; |
| 289 | reg = <0x70002a00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 290 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 291 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 292 | resets = <&tegra_car 18>; |
| 293 | reset-names = "i2s"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 294 | dmas = <&apbdma 1>, <&apbdma 1>; |
| 295 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 296 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 297 | }; |
| 298 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 299 | /* |
| 300 | * There are two serial driver i.e. 8250 based simple serial |
| 301 | * driver and APB DMA based serial driver for higher baudrate |
| 302 | * and performace. To enable the 8250 based driver, the compatible |
| 303 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial |
| 304 | * driver, the comptible is "nvidia,tegra20-hsuart". |
| 305 | */ |
| 306 | uarta: serial@70006000 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 307 | compatible = "nvidia,tegra20-uart"; |
| 308 | reg = <0x70006000 0x40>; |
| 309 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 310 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 311 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 312 | resets = <&tegra_car 6>; |
| 313 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 314 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 315 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 316 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 317 | }; |
| 318 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 319 | uartb: serial@70006040 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 320 | compatible = "nvidia,tegra20-uart"; |
| 321 | reg = <0x70006040 0x40>; |
| 322 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 323 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 324 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 325 | resets = <&tegra_car 7>; |
| 326 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 327 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 328 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 329 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 330 | }; |
| 331 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 332 | uartc: serial@70006200 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 333 | compatible = "nvidia,tegra20-uart"; |
| 334 | reg = <0x70006200 0x100>; |
| 335 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 336 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 337 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 338 | resets = <&tegra_car 55>; |
| 339 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 340 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 341 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 342 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 343 | }; |
| 344 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 345 | uartd: serial@70006300 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 346 | compatible = "nvidia,tegra20-uart"; |
| 347 | reg = <0x70006300 0x100>; |
| 348 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 349 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 350 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 351 | resets = <&tegra_car 65>; |
| 352 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 353 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 354 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 355 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 356 | }; |
| 357 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 358 | uarte: serial@70006400 { |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 359 | compatible = "nvidia,tegra20-uart"; |
| 360 | reg = <0x70006400 0x100>; |
| 361 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 362 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 363 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 364 | resets = <&tegra_car 66>; |
| 365 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 366 | dmas = <&apbdma 20>, <&apbdma 20>; |
| 367 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 368 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 369 | }; |
| 370 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 371 | pwm: pwm@7000a000 { |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 372 | compatible = "nvidia,tegra20-pwm"; |
| 373 | reg = <0x7000a000 0x100>; |
| 374 | #pwm-cells = <2>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 375 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 376 | resets = <&tegra_car 17>; |
| 377 | reset-names = "pwm"; |
Andrew Chew | b69cd98 | 2013-03-12 16:40:51 -0700 | [diff] [blame] | 378 | status = "disabled"; |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 379 | }; |
| 380 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 381 | rtc@7000e000 { |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 382 | compatible = "nvidia,tegra20-rtc"; |
| 383 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 384 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 385 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 386 | }; |
| 387 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 388 | i2c@7000c000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 389 | compatible = "nvidia,tegra20-i2c"; |
| 390 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 391 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 392 | #address-cells = <1>; |
| 393 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 394 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
| 395 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 8d8b43d | 2013-01-11 13:31:21 +0530 | [diff] [blame] | 396 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 397 | resets = <&tegra_car 12>; |
| 398 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 399 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 400 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 401 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 402 | }; |
| 403 | |
Laxman Dewangan | fa98a11 | 2012-11-13 10:33:39 +0530 | [diff] [blame] | 404 | spi@7000c380 { |
| 405 | compatible = "nvidia,tegra20-sflash"; |
| 406 | reg = <0x7000c380 0x80>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 407 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | fa98a11 | 2012-11-13 10:33:39 +0530 | [diff] [blame] | 408 | #address-cells = <1>; |
| 409 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 410 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 411 | resets = <&tegra_car 43>; |
| 412 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 413 | dmas = <&apbdma 11>, <&apbdma 11>; |
| 414 | dma-names = "rx", "tx"; |
Laxman Dewangan | fa98a11 | 2012-11-13 10:33:39 +0530 | [diff] [blame] | 415 | status = "disabled"; |
| 416 | }; |
| 417 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 418 | i2c@7000c400 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 419 | compatible = "nvidia,tegra20-i2c"; |
| 420 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 421 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 422 | #address-cells = <1>; |
| 423 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 424 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
| 425 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 8d8b43d | 2013-01-11 13:31:21 +0530 | [diff] [blame] | 426 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 427 | resets = <&tegra_car 54>; |
| 428 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 429 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 430 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 431 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 432 | }; |
| 433 | |
| 434 | i2c@7000c500 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 435 | compatible = "nvidia,tegra20-i2c"; |
| 436 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 437 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 438 | #address-cells = <1>; |
| 439 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 440 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
| 441 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 8d8b43d | 2013-01-11 13:31:21 +0530 | [diff] [blame] | 442 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 443 | resets = <&tegra_car 67>; |
| 444 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 445 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 446 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 447 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 448 | }; |
| 449 | |
| 450 | i2c@7000d000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 451 | compatible = "nvidia,tegra20-i2c-dvc"; |
| 452 | reg = <0x7000d000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 453 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 454 | #address-cells = <1>; |
| 455 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 456 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
| 457 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 8d8b43d | 2013-01-11 13:31:21 +0530 | [diff] [blame] | 458 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 459 | resets = <&tegra_car 47>; |
| 460 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 461 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 462 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 463 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 464 | }; |
| 465 | |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 466 | spi@7000d400 { |
| 467 | compatible = "nvidia,tegra20-slink"; |
| 468 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 469 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 470 | #address-cells = <1>; |
| 471 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 472 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 473 | resets = <&tegra_car 41>; |
| 474 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 475 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 476 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 477 | status = "disabled"; |
| 478 | }; |
| 479 | |
| 480 | spi@7000d600 { |
| 481 | compatible = "nvidia,tegra20-slink"; |
| 482 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 483 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 486 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 487 | resets = <&tegra_car 44>; |
| 488 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 489 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 490 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | spi@7000d800 { |
| 495 | compatible = "nvidia,tegra20-slink"; |
Laxman Dewangan | 57471c8 | 2013-03-22 12:35:06 -0600 | [diff] [blame] | 496 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 497 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 498 | #address-cells = <1>; |
| 499 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 500 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 501 | resets = <&tegra_car 46>; |
| 502 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 503 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 504 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
| 508 | spi@7000da00 { |
| 509 | compatible = "nvidia,tegra20-slink"; |
| 510 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 511 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 512 | #address-cells = <1>; |
| 513 | #size-cells = <0>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 514 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 515 | resets = <&tegra_car 68>; |
| 516 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 517 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 518 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 519 | status = "disabled"; |
| 520 | }; |
| 521 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 522 | kbc@7000e200 { |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 523 | compatible = "nvidia,tegra20-kbc"; |
| 524 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 525 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 526 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 527 | resets = <&tegra_car 36>; |
| 528 | reset-names = "kbc"; |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 529 | status = "disabled"; |
| 530 | }; |
| 531 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 532 | pmc@7000e400 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 533 | compatible = "nvidia,tegra20-pmc"; |
| 534 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 535 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 536 | clock-names = "pclk", "clk32k_in"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 537 | }; |
| 538 | |
Stephen Warren | bbfc33b | 2012-10-02 13:10:47 -0600 | [diff] [blame] | 539 | memory-controller@7000f000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 540 | compatible = "nvidia,tegra20-mc"; |
| 541 | reg = <0x7000f000 0x024 |
| 542 | 0x7000f03c 0x3c4>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 543 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 544 | }; |
| 545 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 546 | iommu@7000f024 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 547 | compatible = "nvidia,tegra20-gart"; |
| 548 | reg = <0x7000f024 0x00000018 /* controller registers */ |
| 549 | 0x58000000 0x02000000>; /* GART aperture */ |
| 550 | }; |
| 551 | |
Stephen Warren | bbfc33b | 2012-10-02 13:10:47 -0600 | [diff] [blame] | 552 | memory-controller@7000f400 { |
Olof Johansson | 0c6700a | 2011-10-13 02:14:55 -0700 | [diff] [blame] | 553 | compatible = "nvidia,tegra20-emc"; |
| 554 | reg = <0x7000f400 0x200>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 555 | #address-cells = <1>; |
| 556 | #size-cells = <0>; |
Olof Johansson | 0c6700a | 2011-10-13 02:14:55 -0700 | [diff] [blame] | 557 | }; |
| 558 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 559 | fuse@7000f800 { |
| 560 | compatible = "nvidia,tegra20-efuse"; |
| 561 | reg = <0x7000F800 0x400>; |
| 562 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; |
| 563 | clock-names = "fuse"; |
| 564 | resets = <&tegra_car 39>; |
| 565 | reset-names = "fuse"; |
| 566 | }; |
| 567 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 568 | pcie-controller@80003000 { |
Thierry Reding | 1b62b61 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 569 | compatible = "nvidia,tegra20-pcie"; |
| 570 | device_type = "pci"; |
| 571 | reg = <0x80003000 0x00000800 /* PADS registers */ |
| 572 | 0x80003800 0x00000200 /* AFI registers */ |
| 573 | 0x90000000 0x10000000>; /* configuration space */ |
| 574 | reg-names = "pads", "afi", "cs"; |
| 575 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ |
| 576 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| 577 | interrupt-names = "intr", "msi"; |
| 578 | |
Lucas Stach | 97070bd | 2014-03-05 14:25:46 +0100 | [diff] [blame] | 579 | #interrupt-cells = <1>; |
| 580 | interrupt-map-mask = <0 0 0 0>; |
| 581 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 582 | |
Thierry Reding | 1b62b61 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 583 | bus-range = <0x00 0xff>; |
| 584 | #address-cells = <3>; |
| 585 | #size-cells = <2>; |
| 586 | |
| 587 | ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ |
| 588 | 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ |
| 589 | 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ |
Jay Agarwal | d7283c1 | 2013-08-09 16:49:31 +0200 | [diff] [blame] | 590 | 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ |
| 591 | 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ |
Thierry Reding | 1b62b61 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 592 | |
| 593 | clocks = <&tegra_car TEGRA20_CLK_PEX>, |
| 594 | <&tegra_car TEGRA20_CLK_AFI>, |
Thierry Reding | 1b62b61 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 595 | <&tegra_car TEGRA20_CLK_PLL_E>; |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 596 | clock-names = "pex", "afi", "pll_e"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 597 | resets = <&tegra_car 70>, |
| 598 | <&tegra_car 72>, |
| 599 | <&tegra_car 74>; |
| 600 | reset-names = "pex", "afi", "pcie_x"; |
Thierry Reding | 1b62b61 | 2013-08-09 16:49:19 +0200 | [diff] [blame] | 601 | status = "disabled"; |
| 602 | |
| 603 | pci@1,0 { |
| 604 | device_type = "pci"; |
| 605 | assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; |
| 606 | reg = <0x000800 0 0 0 0>; |
| 607 | status = "disabled"; |
| 608 | |
| 609 | #address-cells = <3>; |
| 610 | #size-cells = <2>; |
| 611 | ranges; |
| 612 | |
| 613 | nvidia,num-lanes = <2>; |
| 614 | }; |
| 615 | |
| 616 | pci@2,0 { |
| 617 | device_type = "pci"; |
| 618 | assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; |
| 619 | reg = <0x001000 0 0 0 0>; |
| 620 | status = "disabled"; |
| 621 | |
| 622 | #address-cells = <3>; |
| 623 | #size-cells = <2>; |
| 624 | ranges; |
| 625 | |
| 626 | nvidia,num-lanes = <2>; |
| 627 | }; |
| 628 | }; |
| 629 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 630 | usb@c5000000 { |
| 631 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 632 | reg = <0xc5000000 0x4000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 633 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 634 | phy_type = "utmi"; |
| 635 | nvidia,has-legacy-mode; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 636 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 637 | resets = <&tegra_car 22>; |
| 638 | reset-names = "usb"; |
Venu Byravarasu | b4e0747 | 2012-12-13 20:59:07 +0000 | [diff] [blame] | 639 | nvidia,needs-double-reset; |
Venu Byravarasu | e374b65 | 2013-01-16 03:30:19 +0000 | [diff] [blame] | 640 | nvidia,phy = <&phy1>; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 641 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 642 | }; |
| 643 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 644 | phy1: usb-phy@c5000000 { |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 645 | compatible = "nvidia,tegra20-usb-phy"; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 646 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 647 | phy_type = "utmi"; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 648 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
| 649 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 650 | <&tegra_car TEGRA20_CLK_CLK_M>, |
| 651 | <&tegra_car TEGRA20_CLK_USBD>; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 652 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 653 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 654 | reset-names = "usb", "utmi-pads"; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 655 | nvidia,has-legacy-mode; |
Mikko Perttunen | c49667e | 2013-07-17 09:31:00 +0300 | [diff] [blame] | 656 | nvidia,hssync-start-delay = <9>; |
| 657 | nvidia,idle-wait-delay = <17>; |
| 658 | nvidia,elastic-limit = <16>; |
| 659 | nvidia,term-range-adj = <6>; |
| 660 | nvidia,xcvr-setup = <9>; |
| 661 | nvidia,xcvr-lsfslew = <1>; |
| 662 | nvidia,xcvr-lsrslew = <1>; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 663 | nvidia,has-utmi-pad-registers; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 664 | status = "disabled"; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 665 | }; |
| 666 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 667 | usb@c5004000 { |
| 668 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 669 | reg = <0xc5004000 0x4000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 670 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 671 | phy_type = "ulpi"; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 672 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 673 | resets = <&tegra_car 58>; |
| 674 | reset-names = "usb"; |
Venu Byravarasu | e374b65 | 2013-01-16 03:30:19 +0000 | [diff] [blame] | 675 | nvidia,phy = <&phy2>; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 676 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 677 | }; |
| 678 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 679 | phy2: usb-phy@c5004000 { |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 680 | compatible = "nvidia,tegra20-usb-phy"; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 681 | reg = <0xc5004000 0x4000>; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 682 | phy_type = "ulpi"; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 683 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
| 684 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 685 | <&tegra_car TEGRA20_CLK_CDEV2>; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 686 | clock-names = "reg", "pll_u", "ulpi-link"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 687 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 688 | reset-names = "usb", "utmi-pads"; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 689 | status = "disabled"; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 690 | }; |
| 691 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 692 | usb@c5008000 { |
| 693 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 694 | reg = <0xc5008000 0x4000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 695 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 696 | phy_type = "utmi"; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 697 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 698 | resets = <&tegra_car 59>; |
| 699 | reset-names = "usb"; |
Venu Byravarasu | e374b65 | 2013-01-16 03:30:19 +0000 | [diff] [blame] | 700 | nvidia,phy = <&phy3>; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 701 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 702 | }; |
| 703 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 704 | phy3: usb-phy@c5008000 { |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 705 | compatible = "nvidia,tegra20-usb-phy"; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 706 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 707 | phy_type = "utmi"; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 708 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
| 709 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 710 | <&tegra_car TEGRA20_CLK_CLK_M>, |
| 711 | <&tegra_car TEGRA20_CLK_USBD>; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 712 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 713 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 714 | reset-names = "usb", "utmi-pads"; |
Mikko Perttunen | c49667e | 2013-07-17 09:31:00 +0300 | [diff] [blame] | 715 | nvidia,hssync-start-delay = <9>; |
| 716 | nvidia,idle-wait-delay = <17>; |
| 717 | nvidia,elastic-limit = <16>; |
| 718 | nvidia,term-range-adj = <6>; |
| 719 | nvidia,xcvr-setup = <9>; |
| 720 | nvidia,xcvr-lsfslew = <2>; |
| 721 | nvidia,xcvr-lsrslew = <2>; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 722 | status = "disabled"; |
Stephen Warren | 5d32441 | 2013-03-06 11:28:33 -0700 | [diff] [blame] | 723 | }; |
| 724 | |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 725 | sdhci@c8000000 { |
| 726 | compatible = "nvidia,tegra20-sdhci"; |
| 727 | reg = <0xc8000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 728 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 729 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 730 | resets = <&tegra_car 14>; |
| 731 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 732 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 733 | }; |
| 734 | |
| 735 | sdhci@c8000200 { |
| 736 | compatible = "nvidia,tegra20-sdhci"; |
| 737 | reg = <0xc8000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 738 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 739 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 740 | resets = <&tegra_car 9>; |
| 741 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 742 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 743 | }; |
| 744 | |
| 745 | sdhci@c8000400 { |
| 746 | compatible = "nvidia,tegra20-sdhci"; |
| 747 | reg = <0xc8000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 748 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 749 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 750 | resets = <&tegra_car 69>; |
| 751 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 752 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 753 | }; |
| 754 | |
| 755 | sdhci@c8000600 { |
| 756 | compatible = "nvidia,tegra20-sdhci"; |
| 757 | reg = <0xc8000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 758 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 759 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 760 | resets = <&tegra_car 15>; |
| 761 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 762 | status = "disabled"; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 763 | }; |
Olof Johansson | c27317c | 2011-11-04 09:12:39 +0000 | [diff] [blame] | 764 | |
Hiroshi Doyu | 4dd2bd3 | 2013-01-11 15:26:55 +0200 | [diff] [blame] | 765 | cpus { |
| 766 | #address-cells = <1>; |
| 767 | #size-cells = <0>; |
| 768 | |
| 769 | cpu@0 { |
| 770 | device_type = "cpu"; |
| 771 | compatible = "arm,cortex-a9"; |
| 772 | reg = <0>; |
| 773 | }; |
| 774 | |
| 775 | cpu@1 { |
| 776 | device_type = "cpu"; |
| 777 | compatible = "arm,cortex-a9"; |
| 778 | reg = <1>; |
| 779 | }; |
| 780 | }; |
| 781 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 782 | pmu { |
| 783 | compatible = "arm,cortex-a9-pmu"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 784 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| 785 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
hdoyu@nvidia.com | 6a943e0 | 2012-05-09 21:45:33 +0000 | [diff] [blame] | 786 | }; |
Grant Likely | 8e267f3 | 2011-07-19 17:26:54 -0600 | [diff] [blame] | 787 | }; |