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Jingchang Lue77b74ee2013-05-28 17:12:23 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf610.dtsi"
12
13/ {
14 model = "VF610 Tower Board";
15 compatible = "fsl,vf610-twr", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP1,115200";
19 };
20
21 memory {
22 reg = <0x80000000 0x8000000>;
23 };
24
Stefan Agner3f3ebfb2014-11-02 21:36:44 +010025 audio_ext: mclk_osc {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <24576000>;
29 };
Jingchang Lue77b74ee2013-05-28 17:12:23 +080030
Stefan Agner3f3ebfb2014-11-02 21:36:44 +010031 enet_ext: eth_osc {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <50000000>;
Jingchang Lue77b74ee2013-05-28 17:12:23 +080035 };
36
Xiubo Lic5d571e2014-02-19 15:42:30 +080037 regulators {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 reg_3p3v: regulator@0 {
43 compatible = "regulator-fixed";
44 reg = <0>;
45 regulator-name = "3P3V";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-always-on;
49 };
Fugang Duan64436ff2014-02-21 13:24:16 +080050
51 reg_vcc_3v3_mcu: regulator@1 {
52 compatible = "regulator-fixed";
53 reg = <1>;
54 regulator-name = "vcc_3v3_mcu";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 };
Xiubo Lic5d571e2014-02-19 15:42:30 +080058 };
Xiubo Li8128c4f2014-02-19 15:42:31 +080059
60 sound {
61 compatible = "simple-audio-card";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,widgets =
64 "Microphone", "Microphone Jack",
65 "Headphone", "Headphone Jack",
66 "Speaker", "Speaker Ext",
67 "Line", "Line In Jack";
68 simple-audio-card,routing =
69 "MIC_IN", "Microphone Jack",
70 "Microphone Jack", "Mic Bias",
71 "LINE_IN", "Line In Jack",
72 "Headphone Jack", "HP_OUT",
73 "Speaker Ext", "LINE_OUT";
74
75 simple-audio-card,cpu {
76 sound-dai = <&sai2>;
Xiubo Li8128c4f2014-02-19 15:42:31 +080077 frame-master;
78 bitclock-master;
79 };
80
81 simple-audio-card,codec {
82 sound-dai = <&codec>;
83 frame-master;
84 bitclock-master;
85 };
86 };
Jingchang Lue77b74ee2013-05-28 17:12:23 +080087};
88
Fugang Duan64436ff2014-02-21 13:24:16 +080089&adc0 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_adc0_ad5>;
92 vref-supply = <&reg_vcc_3v3_mcu>;
93 status = "okay";
94};
95
Stefan Agner3f3ebfb2014-11-02 21:36:44 +010096&clks {
97 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
98 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
99};
100
Chao Fudc03a502013-08-30 11:19:49 +0800101&dspi0 {
102 bus-num = <0>;
103 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800104 pinctrl-0 = <&pinctrl_dspi0>;
Chao Fudc03a502013-08-30 11:19:49 +0800105 status = "okay";
106
107 sflash: at26df081a@0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "atmel,at26df081a";
111 spi-max-frequency = <16000000>;
112 spi-cpol;
113 spi-cpha;
114 reg = <0>;
115 };
116};
117
Stefan Agnerefb45b32014-11-02 21:36:46 +0100118&edma0 {
119 status = "okay";
120};
121
Cosmin Stoica0517fe62014-03-06 18:40:34 +0200122&esdhc1 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1>;
125 bus-width = <4>;
126 status = "okay";
127};
128
Jingchang Lue77b74ee2013-05-28 17:12:23 +0800129&fec0 {
130 phy-mode = "rmii";
131 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800132 pinctrl-0 = <&pinctrl_fec0>;
Jingchang Lue77b74ee2013-05-28 17:12:23 +0800133 status = "okay";
134};
135
136&fec1 {
137 phy-mode = "rmii";
138 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800139 pinctrl-0 = <&pinctrl_fec1>;
Jingchang Lue77b74ee2013-05-28 17:12:23 +0800140 status = "okay";
141};
142
Jingchang Lud45393c2013-08-16 13:02:19 +0800143&i2c0 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800146 pinctrl-0 = <&pinctrl_i2c0>;
Jingchang Lud45393c2013-08-16 13:02:19 +0800147 status = "okay";
Xiubo Lic5d571e2014-02-19 15:42:30 +0800148
149 codec: sgtl5000@0a {
Xiubo Li8128c4f2014-02-19 15:42:31 +0800150 #sound-dai-cells = <0>;
Xiubo Lic5d571e2014-02-19 15:42:30 +0800151 compatible = "fsl,sgtl5000";
152 reg = <0x0a>;
153 VDDA-supply = <&reg_3p3v>;
154 VDDIO-supply = <&reg_3p3v>;
155 clocks = <&clks VF610_CLK_SAI2>;
156 };
Jingchang Lud45393c2013-08-16 13:02:19 +0800157};
158
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800159&iomuxc {
160 vf610-twr {
Fugang Duan64436ff2014-02-21 13:24:16 +0800161 pinctrl_adc0_ad5: adc0ad5grp {
162 fsl,pins = <
163 VF610_PAD_PTC30__ADC0_SE5 0xa1
164 >;
165 };
166
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800167 pinctrl_dspi0: dspi0grp {
168 fsl,pins = <
169 VF610_PAD_PTB19__DSPI0_CS0 0x1182
170 VF610_PAD_PTB20__DSPI0_SIN 0x1181
171 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
172 VF610_PAD_PTB22__DSPI0_SCK 0x1182
173 >;
174 };
175
Cosmin Stoica0517fe62014-03-06 18:40:34 +0200176 pinctrl_esdhc1: esdhc1grp {
Bill Pringlemeir0aa4dcb2014-08-05 13:34:00 -0400177 fsl,pins = <
Cosmin Stoica0517fe62014-03-06 18:40:34 +0200178 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
179 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
180 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
181 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
182 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
183 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
184 VF610_PAD_PTA7__GPIO_134 0x219d
185 >;
186 };
187
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800188 pinctrl_fec0: fec0grp {
189 fsl,pins = <
190 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
191 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
192 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
193 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
194 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
195 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
196 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
197 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
198 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
199 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
200 >;
201 };
202
203 pinctrl_fec1: fec1grp {
204 fsl,pins = <
205 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
206 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
207 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
208 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
209 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
210 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
211 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
212 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
213 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
214 >;
215 };
216
217 pinctrl_i2c0: i2c0grp {
218 fsl,pins = <
219 VF610_PAD_PTB14__I2C0_SCL 0x30d3
220 VF610_PAD_PTB15__I2C0_SDA 0x30d3
221 >;
222 };
223
Xiubo Lif54c2fe2014-03-24 10:22:15 +0800224 pinctrl_pwm0: pwm0grp {
225 fsl,pins = <
226 VF610_PAD_PTB0__FTM0_CH0 0x1582
227 VF610_PAD_PTB1__FTM0_CH1 0x1582
228 VF610_PAD_PTB2__FTM0_CH2 0x1582
229 VF610_PAD_PTB3__FTM0_CH3 0x1582
Xiubo Lif54c2fe2014-03-24 10:22:15 +0800230 >;
231 };
232
Xiubo Li95b13b62014-02-19 15:42:29 +0800233 pinctrl_sai2: sai2grp {
234 fsl,pins = <
235 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
236 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
237 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
238 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
239 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
240 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
241 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
242 >;
243 };
244
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800245 pinctrl_uart1: uart1grp {
246 fsl,pins = <
247 VF610_PAD_PTB4__UART1_TX 0x21a2
248 VF610_PAD_PTB5__UART1_RX 0x21a1
249 >;
250 };
Bill Pringlemeird8c99932014-08-05 13:34:01 -0400251
252 pinctrl_uart2: uart2grp {
253 fsl,pins = <
254 VF610_PAD_PTB6__UART2_TX 0x21a2
255 VF610_PAD_PTB7__UART2_RX 0x21a1
256 >;
257 };
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800258 };
259};
260
Xiubo Li266a71b2014-03-24 10:22:16 +0800261&pwm0 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_pwm0>;
264 status = "okay";
265};
266
Xiubo Li95b13b62014-02-19 15:42:29 +0800267&sai2 {
Xiubo Li8128c4f2014-02-19 15:42:31 +0800268 #sound-dai-cells = <0>;
Xiubo Li95b13b62014-02-19 15:42:29 +0800269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_sai2>;
271 status = "okay";
272};
273
Jingchang Lue77b74ee2013-05-28 17:12:23 +0800274&uart1 {
275 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800276 pinctrl-0 = <&pinctrl_uart1>;
Jingchang Lue77b74ee2013-05-28 17:12:23 +0800277 status = "okay";
278};
Bill Pringlemeird8c99932014-08-05 13:34:01 -0400279
280&uart2 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_uart2>;
283 status = "okay";
284};
Stefan Agner49b2ae02014-08-18 22:07:17 +0200285
286&usbdev0 {
287 disable-over-current;
288 status = "okay";
289};
290
291&usbh1 {
292 disable-over-current;
293 status = "okay";
294};
Stefan Agnerefb45b32014-11-02 21:36:46 +0100295
296&usbphy0 {
297 status = "okay";
298};
299
300&usbphy1 {
301 status = "okay";
302};