Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Low-level CPU initialisation |
| 3 | * Based on arch/arm/kernel/head.S |
| 4 | * |
| 5 | * Copyright (C) 1994-2002 Russell King |
| 6 | * Copyright (C) 2003-2012 ARM Ltd. |
| 7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> |
| 8 | * Will Deacon <will.deacon@arm.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #include <linux/linkage.h> |
| 24 | #include <linux/init.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 25 | #include <linux/irqchip/arm-gic-v3.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 26 | |
| 27 | #include <asm/assembler.h> |
Ard Biesheuvel | 08cdac6 | 2016-04-18 17:09:47 +0200 | [diff] [blame] | 28 | #include <asm/boot.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 29 | #include <asm/ptrace.h> |
| 30 | #include <asm/asm-offsets.h> |
Catalin Marinas | c218bca | 2014-03-26 18:25:55 +0000 | [diff] [blame] | 31 | #include <asm/cache.h> |
Javi Merino | 0359b0e | 2012-08-29 18:32:18 +0100 | [diff] [blame] | 32 | #include <asm/cputype.h> |
Ard Biesheuvel | 1e48ef7 | 2016-01-26 09:13:44 +0100 | [diff] [blame] | 33 | #include <asm/elf.h> |
Suzuki K. Poulose | 87d1587 | 2015-10-19 14:19:27 +0100 | [diff] [blame] | 34 | #include <asm/kernel-pgtable.h> |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 35 | #include <asm/kvm_arm.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 36 | #include <asm/memory.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 37 | #include <asm/pgtable-hwdef.h> |
| 38 | #include <asm/pgtable.h> |
| 39 | #include <asm/page.h> |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 40 | #include <asm/smp.h> |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 41 | #include <asm/sysreg.h> |
| 42 | #include <asm/thread_info.h> |
Marc Zyngier | f35a920 | 2012-10-26 15:40:05 +0100 | [diff] [blame] | 43 | #include <asm/virt.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 44 | |
Ard Biesheuvel | 6f4d57f | 2015-03-17 09:14:29 +0100 | [diff] [blame] | 45 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 46 | |
Ard Biesheuvel | 4190312 | 2014-08-13 18:53:03 +0100 | [diff] [blame] | 47 | #if (TEXT_OFFSET & 0xfff) != 0 |
| 48 | #error TEXT_OFFSET must be at least 4KB aligned |
| 49 | #elif (PAGE_OFFSET & 0x1fffff) != 0 |
Mark Rutland | da57a36 | 2014-06-24 16:51:37 +0100 | [diff] [blame] | 50 | #error PAGE_OFFSET must be at least 2MB aligned |
Ard Biesheuvel | 4190312 | 2014-08-13 18:53:03 +0100 | [diff] [blame] | 51 | #elif TEXT_OFFSET > 0x1fffff |
Mark Rutland | da57a36 | 2014-06-24 16:51:37 +0100 | [diff] [blame] | 52 | #error TEXT_OFFSET must be less than 2MB |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 53 | #endif |
| 54 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 55 | /* |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 56 | * Kernel startup entry point. |
| 57 | * --------------------------- |
| 58 | * |
| 59 | * The requirements are: |
| 60 | * MMU = off, D-cache = off, I-cache = on or off, |
| 61 | * x0 = physical address to the FDT blob. |
| 62 | * |
| 63 | * This code is mostly position independent so you call this at |
| 64 | * __pa(PAGE_OFFSET + TEXT_OFFSET). |
| 65 | * |
| 66 | * Note that the callee-saved registers are used for storing variables |
| 67 | * that are useful before the MMU is enabled. The allocations are described |
| 68 | * in the entry routines. |
| 69 | */ |
| 70 | __HEAD |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 71 | _head: |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 72 | /* |
| 73 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. |
| 74 | */ |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 75 | #ifdef CONFIG_EFI |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 76 | /* |
| 77 | * This add instruction has no meaningful effect except that |
| 78 | * its opcode forms the magic "MZ" signature required by UEFI. |
| 79 | */ |
| 80 | add x13, x18, #0x16 |
| 81 | b stext |
| 82 | #else |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 83 | b stext // branch to kernel start, magic |
| 84 | .long 0 // reserved |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 85 | #endif |
Ard Biesheuvel | 6ad1fe5 | 2015-12-26 13:48:02 +0100 | [diff] [blame] | 86 | le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian |
| 87 | le64sym _kernel_size_le // Effective size of kernel image, little-endian |
| 88 | le64sym _kernel_flags_le // Informative flags, little-endian |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 89 | .quad 0 // reserved |
| 90 | .quad 0 // reserved |
| 91 | .quad 0 // reserved |
| 92 | .byte 0x41 // Magic number, "ARM\x64" |
| 93 | .byte 0x52 |
| 94 | .byte 0x4d |
| 95 | .byte 0x64 |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 96 | #ifdef CONFIG_EFI |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 97 | .long pe_header - _head // Offset to the PE header. |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 98 | #else |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 99 | .word 0 // reserved |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 100 | #endif |
| 101 | |
| 102 | #ifdef CONFIG_EFI |
| 103 | .align 3 |
| 104 | pe_header: |
| 105 | .ascii "PE" |
| 106 | .short 0 |
| 107 | coff_header: |
| 108 | .short 0xaa64 // AArch64 |
| 109 | .short 2 // nr_sections |
| 110 | .long 0 // TimeDateStamp |
| 111 | .long 0 // PointerToSymbolTable |
| 112 | .long 1 // NumberOfSymbols |
| 113 | .short section_table - optional_header // SizeOfOptionalHeader |
| 114 | .short 0x206 // Characteristics. |
| 115 | // IMAGE_FILE_DEBUG_STRIPPED | |
| 116 | // IMAGE_FILE_EXECUTABLE_IMAGE | |
| 117 | // IMAGE_FILE_LINE_NUMS_STRIPPED |
| 118 | optional_header: |
| 119 | .short 0x20b // PE32+ format |
| 120 | .byte 0x02 // MajorLinkerVersion |
| 121 | .byte 0x14 // MinorLinkerVersion |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 122 | .long _end - efi_header_end // SizeOfCode |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 123 | .long 0 // SizeOfInitializedData |
| 124 | .long 0 // SizeOfUninitializedData |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 125 | .long __efistub_entry - _head // AddressOfEntryPoint |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 126 | .long efi_header_end - _head // BaseOfCode |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 127 | |
| 128 | extra_header_fields: |
| 129 | .quad 0 // ImageBase |
Ard Biesheuvel | ea6bc80 | 2014-10-10 11:25:24 +0200 | [diff] [blame] | 130 | .long 0x1000 // SectionAlignment |
Ard Biesheuvel | a352ea3 | 2014-10-10 18:42:55 +0200 | [diff] [blame] | 131 | .long PECOFF_FILE_ALIGNMENT // FileAlignment |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 132 | .short 0 // MajorOperatingSystemVersion |
| 133 | .short 0 // MinorOperatingSystemVersion |
| 134 | .short 0 // MajorImageVersion |
| 135 | .short 0 // MinorImageVersion |
| 136 | .short 0 // MajorSubsystemVersion |
| 137 | .short 0 // MinorSubsystemVersion |
| 138 | .long 0 // Win32VersionValue |
| 139 | |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 140 | .long _end - _head // SizeOfImage |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 141 | |
| 142 | // Everything before the kernel image is considered part of the header |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 143 | .long efi_header_end - _head // SizeOfHeaders |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 144 | .long 0 // CheckSum |
| 145 | .short 0xa // Subsystem (EFI application) |
| 146 | .short 0 // DllCharacteristics |
| 147 | .quad 0 // SizeOfStackReserve |
| 148 | .quad 0 // SizeOfStackCommit |
| 149 | .quad 0 // SizeOfHeapReserve |
| 150 | .quad 0 // SizeOfHeapCommit |
| 151 | .long 0 // LoaderFlags |
| 152 | .long 0x6 // NumberOfRvaAndSizes |
| 153 | |
| 154 | .quad 0 // ExportTable |
| 155 | .quad 0 // ImportTable |
| 156 | .quad 0 // ResourceTable |
| 157 | .quad 0 // ExceptionTable |
| 158 | .quad 0 // CertificationTable |
| 159 | .quad 0 // BaseRelocationTable |
| 160 | |
| 161 | // Section table |
| 162 | section_table: |
| 163 | |
| 164 | /* |
| 165 | * The EFI application loader requires a relocation section |
| 166 | * because EFI applications must be relocatable. This is a |
| 167 | * dummy section as far as we are concerned. |
| 168 | */ |
| 169 | .ascii ".reloc" |
| 170 | .byte 0 |
| 171 | .byte 0 // end of 0 padding of section name |
| 172 | .long 0 |
| 173 | .long 0 |
| 174 | .long 0 // SizeOfRawData |
| 175 | .long 0 // PointerToRawData |
| 176 | .long 0 // PointerToRelocations |
| 177 | .long 0 // PointerToLineNumbers |
| 178 | .short 0 // NumberOfRelocations |
| 179 | .short 0 // NumberOfLineNumbers |
| 180 | .long 0x42100040 // Characteristics (section flags) |
| 181 | |
| 182 | |
| 183 | .ascii ".text" |
| 184 | .byte 0 |
| 185 | .byte 0 |
| 186 | .byte 0 // end of 0 padding of section name |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 187 | .long _end - efi_header_end // VirtualSize |
| 188 | .long efi_header_end - _head // VirtualAddress |
| 189 | .long _edata - efi_header_end // SizeOfRawData |
| 190 | .long efi_header_end - _head // PointerToRawData |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 191 | |
| 192 | .long 0 // PointerToRelocations (0 for executables) |
| 193 | .long 0 // PointerToLineNumbers (0 for executables) |
| 194 | .short 0 // NumberOfRelocations (0 for executables) |
| 195 | .short 0 // NumberOfLineNumbers (0 for executables) |
| 196 | .long 0xe0500020 // Characteristics (section flags) |
Ard Biesheuvel | ea6bc80 | 2014-10-10 11:25:24 +0200 | [diff] [blame] | 197 | |
| 198 | /* |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 199 | * EFI will load .text onwards at the 4k section alignment |
Ard Biesheuvel | ea6bc80 | 2014-10-10 11:25:24 +0200 | [diff] [blame] | 200 | * described in the PE/COFF header. To ensure that instruction |
| 201 | * sequences using an adrp and a :lo12: immediate will function |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 202 | * correctly at this alignment, we must ensure that .text is |
Ard Biesheuvel | ea6bc80 | 2014-10-10 11:25:24 +0200 | [diff] [blame] | 203 | * placed at a 4k boundary in the Image to begin with. |
| 204 | */ |
| 205 | .align 12 |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 206 | efi_header_end: |
Mark Salter | 3c7f255 | 2014-04-15 22:47:52 -0400 | [diff] [blame] | 207 | #endif |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 208 | |
Ard Biesheuvel | 546c8c4 | 2016-03-30 17:43:07 +0200 | [diff] [blame] | 209 | __INIT |
| 210 | |
Ard Biesheuvel | a9be2ee | 2016-08-31 12:05:17 +0100 | [diff] [blame] | 211 | /* |
| 212 | * The following callee saved general purpose registers are used on the |
| 213 | * primary lowlevel boot path: |
| 214 | * |
| 215 | * Register Scope Purpose |
| 216 | * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 |
| 217 | * x23 stext() .. start_kernel() physical misalignment/KASLR offset |
| 218 | * x28 __create_page_tables() callee preserved temp register |
| 219 | * x19/x20 __primary_switch() callee preserved temp registers |
| 220 | */ |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 221 | ENTRY(stext) |
Ard Biesheuvel | da9c177 | 2015-03-17 10:55:12 +0100 | [diff] [blame] | 222 | bl preserve_boot_args |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 223 | bl el2_setup // Drop to EL1, w0=cpu_boot_mode |
Ard Biesheuvel | b929fe3 | 2016-08-31 12:05:15 +0100 | [diff] [blame] | 224 | adrp x23, __PHYS_OFFSET |
| 225 | and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 226 | bl set_cpu_boot_mode_flag |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 227 | bl __create_page_tables |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 228 | /* |
Marc Zyngier | a591ede | 2015-03-18 14:55:20 +0000 | [diff] [blame] | 229 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
| 230 | * details. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 231 | * On return, the CPU will be ready for the MMU to be turned on and |
| 232 | * the TCR will have been set. |
| 233 | */ |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 234 | bl __cpu_setup // initialise processor |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 235 | b __primary_switch |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 236 | ENDPROC(stext) |
| 237 | |
| 238 | /* |
Ard Biesheuvel | da9c177 | 2015-03-17 10:55:12 +0100 | [diff] [blame] | 239 | * Preserve the arguments passed by the bootloader in x0 .. x3 |
| 240 | */ |
| 241 | preserve_boot_args: |
| 242 | mov x21, x0 // x21=FDT |
| 243 | |
| 244 | adr_l x0, boot_args // record the contents of |
| 245 | stp x21, x1, [x0] // x0 .. x3 at kernel entry |
| 246 | stp x2, x3, [x0, #16] |
| 247 | |
| 248 | dmb sy // needed before dc ivac with |
| 249 | // MMU off |
| 250 | |
| 251 | add x1, x0, #0x20 // 4 x 8 bytes |
| 252 | b __inval_cache_range // tail call |
| 253 | ENDPROC(preserve_boot_args) |
| 254 | |
| 255 | /* |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 256 | * Macro to create a table entry to the next page. |
| 257 | * |
| 258 | * tbl: page table address |
| 259 | * virt: virtual address |
| 260 | * shift: #imm page table shift |
| 261 | * ptrs: #imm pointers per table page |
| 262 | * |
| 263 | * Preserves: virt |
| 264 | * Corrupts: tmp1, tmp2 |
| 265 | * Returns: tbl -> next level table page address |
| 266 | */ |
| 267 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 |
| 268 | lsr \tmp1, \virt, #\shift |
| 269 | and \tmp1, \tmp1, #\ptrs - 1 // table index |
| 270 | add \tmp2, \tbl, #PAGE_SIZE |
| 271 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type |
| 272 | str \tmp2, [\tbl, \tmp1, lsl #3] |
| 273 | add \tbl, \tbl, #PAGE_SIZE // next level table page |
| 274 | .endm |
| 275 | |
| 276 | /* |
| 277 | * Macro to populate the PGD (and possibily PUD) for the corresponding |
| 278 | * block entry in the next level (tbl) for the given virtual address. |
| 279 | * |
| 280 | * Preserves: tbl, next, virt |
| 281 | * Corrupts: tmp1, tmp2 |
| 282 | */ |
| 283 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 |
| 284 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 |
Suzuki K. Poulose | 6a3fd40 | 2015-10-19 14:19:31 +0100 | [diff] [blame] | 285 | #if SWAPPER_PGTABLE_LEVELS > 3 |
| 286 | create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 |
| 287 | #endif |
| 288 | #if SWAPPER_PGTABLE_LEVELS > 2 |
Suzuki K. Poulose | 87d1587 | 2015-10-19 14:19:27 +0100 | [diff] [blame] | 289 | create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 290 | #endif |
| 291 | .endm |
| 292 | |
| 293 | /* |
| 294 | * Macro to populate block entries in the page table for the start..end |
| 295 | * virtual range (inclusive). |
| 296 | * |
| 297 | * Preserves: tbl, flags |
| 298 | * Corrupts: phys, start, end, pstate |
| 299 | */ |
| 300 | .macro create_block_map, tbl, flags, phys, start, end |
Suzuki K. Poulose | 87d1587 | 2015-10-19 14:19:27 +0100 | [diff] [blame] | 301 | lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT |
| 302 | lsr \start, \start, #SWAPPER_BLOCK_SHIFT |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 303 | and \start, \start, #PTRS_PER_PTE - 1 // table index |
Suzuki K. Poulose | 87d1587 | 2015-10-19 14:19:27 +0100 | [diff] [blame] | 304 | orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry |
| 305 | lsr \end, \end, #SWAPPER_BLOCK_SHIFT |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 306 | and \end, \end, #PTRS_PER_PTE - 1 // table end index |
| 307 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry |
| 308 | add \start, \start, #1 // next entry |
Suzuki K. Poulose | 87d1587 | 2015-10-19 14:19:27 +0100 | [diff] [blame] | 309 | add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 310 | cmp \start, \end |
| 311 | b.ls 9999b |
| 312 | .endm |
| 313 | |
| 314 | /* |
| 315 | * Setup the initial page tables. We only setup the barest amount which is |
| 316 | * required to get the kernel running. The following sections are required: |
| 317 | * - identity mapping to enable the MMU (low address, TTBR0) |
| 318 | * - first few MB of the kernel linear mapping to jump to once the MMU has |
Ard Biesheuvel | 61bd93c | 2015-06-01 13:40:32 +0200 | [diff] [blame] | 319 | * been enabled |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 320 | */ |
| 321 | __create_page_tables: |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 322 | mov x28, lr |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 323 | |
| 324 | /* |
| 325 | * Invalidate the idmap and swapper page tables to avoid potential |
| 326 | * dirty cache lines being evicted. |
| 327 | */ |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 328 | adrp x0, idmap_pg_dir |
| 329 | adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 330 | bl __inval_cache_range |
| 331 | |
| 332 | /* |
| 333 | * Clear the idmap and swapper page tables. |
| 334 | */ |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 335 | adrp x0, idmap_pg_dir |
| 336 | adrp x6, swapper_pg_dir + SWAPPER_DIR_SIZE |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 337 | 1: stp xzr, xzr, [x0], #16 |
| 338 | stp xzr, xzr, [x0], #16 |
| 339 | stp xzr, xzr, [x0], #16 |
| 340 | stp xzr, xzr, [x0], #16 |
| 341 | cmp x0, x6 |
| 342 | b.lo 1b |
| 343 | |
Ard Biesheuvel | b03cc88 | 2016-04-18 17:09:45 +0200 | [diff] [blame] | 344 | mov x7, SWAPPER_MM_MMUFLAGS |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 345 | |
| 346 | /* |
| 347 | * Create the identity mapping. |
| 348 | */ |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 349 | adrp x0, idmap_pg_dir |
Ard Biesheuvel | 5dfe9d7 | 2015-06-01 13:40:33 +0200 | [diff] [blame] | 350 | adrp x3, __idmap_text_start // __pa(__idmap_text_start) |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 351 | |
| 352 | #ifndef CONFIG_ARM64_VA_BITS_48 |
| 353 | #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) |
| 354 | #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) |
| 355 | |
| 356 | /* |
| 357 | * If VA_BITS < 48, it may be too small to allow for an ID mapping to be |
| 358 | * created that covers system RAM if that is located sufficiently high |
| 359 | * in the physical address space. So for the ID map, use an extended |
| 360 | * virtual range in that case, by configuring an additional translation |
| 361 | * level. |
| 362 | * First, we have to verify our assumption that the current value of |
| 363 | * VA_BITS was chosen such that all translation levels are fully |
| 364 | * utilised, and that lowering T0SZ will always result in an additional |
| 365 | * translation level to be configured. |
| 366 | */ |
| 367 | #if VA_BITS != EXTRA_SHIFT |
| 368 | #error "Mismatch between VA_BITS and page size/number of translation levels" |
| 369 | #endif |
| 370 | |
| 371 | /* |
| 372 | * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the |
Ard Biesheuvel | 5dfe9d7 | 2015-06-01 13:40:33 +0200 | [diff] [blame] | 373 | * entire ID map region can be mapped. As T0SZ == (64 - #bits used), |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 374 | * this number conveniently equals the number of leading zeroes in |
Ard Biesheuvel | 5dfe9d7 | 2015-06-01 13:40:33 +0200 | [diff] [blame] | 375 | * the physical address of __idmap_text_end. |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 376 | */ |
Ard Biesheuvel | 5dfe9d7 | 2015-06-01 13:40:33 +0200 | [diff] [blame] | 377 | adrp x5, __idmap_text_end |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 378 | clz x5, x5 |
| 379 | cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? |
| 380 | b.ge 1f // .. then skip additional level |
| 381 | |
Mark Rutland | 0c20856 | 2015-03-24 15:10:21 +0000 | [diff] [blame] | 382 | adr_l x6, idmap_t0sz |
| 383 | str x5, [x6] |
| 384 | dmb sy |
| 385 | dc ivac, x6 // Invalidate potentially stale cache line |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 386 | |
| 387 | create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 |
| 388 | 1: |
| 389 | #endif |
| 390 | |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 391 | create_pgd_entry x0, x3, x5, x6 |
Ard Biesheuvel | 5dfe9d7 | 2015-06-01 13:40:33 +0200 | [diff] [blame] | 392 | mov x5, x3 // __pa(__idmap_text_start) |
| 393 | adr_l x6, __idmap_text_end // __pa(__idmap_text_end) |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 394 | create_block_map x0, x7, x3, x5, x6 |
| 395 | |
| 396 | /* |
| 397 | * Map the kernel image (starting with PHYS_OFFSET). |
| 398 | */ |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 399 | adrp x0, swapper_pg_dir |
Ard Biesheuvel | 18b9c0d | 2016-04-18 17:09:46 +0200 | [diff] [blame] | 400 | mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 401 | add x5, x5, x23 // add KASLR displacement |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 402 | create_pgd_entry x0, x5, x3, x6 |
Ard Biesheuvel | 18b9c0d | 2016-04-18 17:09:46 +0200 | [diff] [blame] | 403 | adrp x6, _end // runtime __pa(_end) |
| 404 | adrp x3, _text // runtime __pa(_text) |
| 405 | sub x6, x6, x3 // _end - _text |
| 406 | add x6, x6, x5 // runtime __va(_end) |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 407 | create_block_map x0, x7, x3, x5, x6 |
| 408 | |
| 409 | /* |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 410 | * Since the page tables have been populated with non-cacheable |
| 411 | * accesses (MMU disabled), invalidate the idmap and swapper page |
| 412 | * tables again to remove any speculatively loaded cache lines. |
| 413 | */ |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 414 | adrp x0, idmap_pg_dir |
| 415 | adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE |
Mark Rutland | 91d5715 | 2015-03-24 13:50:27 +0000 | [diff] [blame] | 416 | dmb sy |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 417 | bl __inval_cache_range |
| 418 | |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 419 | ret x28 |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 420 | ENDPROC(__create_page_tables) |
| 421 | .ltorg |
| 422 | |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 423 | /* |
Ard Biesheuvel | a871d35 | 2015-03-04 11:51:48 +0100 | [diff] [blame] | 424 | * The following fragment of code is executed with the MMU enabled. |
Ard Biesheuvel | b929fe3 | 2016-08-31 12:05:15 +0100 | [diff] [blame] | 425 | * |
| 426 | * x0 = __PHYS_OFFSET |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 427 | */ |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 428 | __primary_switched: |
Ard Biesheuvel | 60699ba | 2016-08-31 12:05:16 +0100 | [diff] [blame] | 429 | adrp x4, init_thread_union |
| 430 | add sp, x4, #THREAD_SIZE |
| 431 | msr sp_el0, x4 // Save thread_info |
| 432 | |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 433 | adr_l x8, vectors // load VBAR_EL1 with virtual |
| 434 | msr vbar_el1, x8 // vector table address |
| 435 | isb |
| 436 | |
Ard Biesheuvel | 60699ba | 2016-08-31 12:05:16 +0100 | [diff] [blame] | 437 | stp xzr, x30, [sp, #-16]! |
| 438 | mov x29, sp |
| 439 | |
Ard Biesheuvel | b929fe3 | 2016-08-31 12:05:15 +0100 | [diff] [blame] | 440 | str_l x21, __fdt_pointer, x5 // Save FDT pointer |
| 441 | |
| 442 | ldr_l x4, kimage_vaddr // Save the offset between |
| 443 | sub x4, x4, x0 // the kernel virtual and |
| 444 | str_l x4, kimage_voffset, x5 // physical mappings |
| 445 | |
Mark Rutland | 2a803c4 | 2016-01-06 11:05:27 +0000 | [diff] [blame] | 446 | // Clear BSS |
| 447 | adr_l x0, __bss_start |
| 448 | mov x1, xzr |
| 449 | adr_l x2, __bss_stop |
| 450 | sub x2, x2, x0 |
| 451 | bl __pi_memset |
Mark Rutland | 5227cfa | 2016-01-25 11:44:57 +0000 | [diff] [blame] | 452 | dsb ishst // Make zero page visible to PTW |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 453 | |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 454 | #ifdef CONFIG_KASAN |
| 455 | bl kasan_early_init |
| 456 | #endif |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 457 | #ifdef CONFIG_RANDOMIZE_BASE |
Ard Biesheuvel | 08cdac6 | 2016-04-18 17:09:47 +0200 | [diff] [blame] | 458 | tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? |
| 459 | b.ne 0f |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 460 | mov x0, x21 // pass FDT address in x0 |
Ard Biesheuvel | 08cdac6 | 2016-04-18 17:09:47 +0200 | [diff] [blame] | 461 | mov x1, x23 // pass modulo offset in x1 |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 462 | bl kaslr_early_init // parse FDT for KASLR options |
| 463 | cbz x0, 0f // KASLR disabled? just proceed |
Ard Biesheuvel | 08cdac6 | 2016-04-18 17:09:47 +0200 | [diff] [blame] | 464 | orr x23, x23, x0 // record KASLR offset |
Ard Biesheuvel | 60699ba | 2016-08-31 12:05:16 +0100 | [diff] [blame] | 465 | ldp x29, x30, [sp], #16 // we must enable KASLR, return |
| 466 | ret // to __primary_switch() |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 467 | 0: |
| 468 | #endif |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 469 | b start_kernel |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 470 | ENDPROC(__primary_switched) |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 471 | |
| 472 | /* |
| 473 | * end early head section, begin head code that is also used for |
| 474 | * hotplug and needs to have the same protections as the text region |
| 475 | */ |
Will Deacon | 574e44d | 2018-04-03 12:09:23 +0100 | [diff] [blame] | 476 | .section ".idmap.text","awx" |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 477 | |
| 478 | ENTRY(kimage_vaddr) |
| 479 | .quad _text - TEXT_OFFSET |
| 480 | |
Laura Abbott | 034edab | 2014-11-21 13:50:41 -0800 | [diff] [blame] | 481 | /* |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 482 | * If we're fortunate enough to boot at EL2, ensure that the world is |
| 483 | * sane before dropping to EL1. |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 484 | * |
| 485 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if |
| 486 | * booted in EL1 or EL2 respectively. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 487 | */ |
| 488 | ENTRY(el2_setup) |
Marc Zyngier | 7dbd642 | 2017-09-26 15:57:16 +0100 | [diff] [blame] | 489 | msr SPsel, #1 // We want to use SP_EL{1,2} |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 490 | mrs x0, CurrentEL |
Marc Zyngier | 974c8e4 | 2014-06-06 14:16:21 +0100 | [diff] [blame] | 491 | cmp x0, #CurrentEL_EL2 |
Matthew Leach | 9cf7172 | 2013-10-11 14:52:17 +0100 | [diff] [blame] | 492 | b.ne 1f |
| 493 | mrs x0, sctlr_el2 |
| 494 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 |
| 495 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 |
| 496 | msr sctlr_el2, x0 |
| 497 | b 2f |
| 498 | 1: mrs x0, sctlr_el1 |
| 499 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 |
| 500 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 |
| 501 | msr sctlr_el1, x0 |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 502 | mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
Matthew Leach | 9cf7172 | 2013-10-11 14:52:17 +0100 | [diff] [blame] | 503 | isb |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 504 | ret |
| 505 | |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 506 | 2: |
| 507 | #ifdef CONFIG_ARM64_VHE |
| 508 | /* |
| 509 | * Check for VHE being present. For the rest of the EL2 setup, |
| 510 | * x2 being non-zero indicates that we do have VHE, and that the |
| 511 | * kernel is intended to run at EL2. |
| 512 | */ |
| 513 | mrs x2, id_aa64mmfr1_el1 |
| 514 | ubfx x2, x2, #8, #4 |
| 515 | #else |
| 516 | mov x2, xzr |
| 517 | #endif |
| 518 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 519 | /* Hyp configuration. */ |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 520 | mov x0, #HCR_RW // 64-bit EL1 |
| 521 | cbz x2, set_hcr |
| 522 | orr x0, x0, #HCR_TGE // Enable Host Extensions |
| 523 | orr x0, x0, #HCR_E2H |
| 524 | set_hcr: |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 525 | msr hcr_el2, x0 |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 526 | isb |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 527 | |
| 528 | /* Generic timers. */ |
| 529 | mrs x0, cnthctl_el2 |
| 530 | orr x0, x0, #3 // Enable EL1 physical timers |
| 531 | msr cnthctl_el2, x0 |
Will Deacon | 1f75ff0 | 2012-11-29 22:48:31 +0000 | [diff] [blame] | 532 | msr cntvoff_el2, xzr // Clear virtual offset |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 533 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 534 | #ifdef CONFIG_ARM_GIC_V3 |
| 535 | /* GICv3 system register access */ |
| 536 | mrs x0, id_aa64pfr0_el1 |
| 537 | ubfx x0, x0, #24, #4 |
| 538 | cmp x0, #1 |
| 539 | b.ne 3f |
| 540 | |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 541 | mrs_s x0, ICC_SRE_EL2 |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 542 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
| 543 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 544 | msr_s ICC_SRE_EL2, x0 |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 545 | isb // Make sure SRE is now set |
Marc Zyngier | d271976 | 2015-09-30 11:39:59 +0100 | [diff] [blame] | 546 | mrs_s x0, ICC_SRE_EL2 // Read SRE back, |
| 547 | tbz x0, #0, 3f // and check that it sticks |
Catalin Marinas | 72c5839 | 2014-07-24 14:14:42 +0100 | [diff] [blame] | 548 | msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 549 | |
| 550 | 3: |
| 551 | #endif |
| 552 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 553 | /* Populate ID registers. */ |
| 554 | mrs x0, midr_el1 |
| 555 | mrs x1, mpidr_el1 |
| 556 | msr vpidr_el2, x0 |
| 557 | msr vmpidr_el2, x1 |
| 558 | |
Dave Martin | 882416c | 2016-04-18 18:57:26 +0100 | [diff] [blame] | 559 | /* |
| 560 | * When VHE is not in use, early init of EL2 and EL1 needs to be |
| 561 | * done here. |
| 562 | * When VHE _is_ in use, EL1 will not be used in the host and |
| 563 | * requires no configuration, and all non-hyp-specific EL2 setup |
| 564 | * will be done via the _EL1 system register aliases in __cpu_setup. |
| 565 | */ |
| 566 | cbnz x2, 1f |
| 567 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 568 | /* sctlr_el1 */ |
| 569 | mov x0, #0x0800 // Set/clear RES{1,0} bits |
Matthew Leach | 9cf7172 | 2013-10-11 14:52:17 +0100 | [diff] [blame] | 570 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems |
| 571 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 572 | msr sctlr_el1, x0 |
| 573 | |
| 574 | /* Coprocessor traps. */ |
| 575 | mov x0, #0x33ff |
| 576 | msr cptr_el2, x0 // Disable copro. traps to EL2 |
Dave Martin | 882416c | 2016-04-18 18:57:26 +0100 | [diff] [blame] | 577 | 1: |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 578 | |
| 579 | #ifdef CONFIG_COMPAT |
| 580 | msr hstr_el2, xzr // Disable CP15 traps to EL2 |
| 581 | #endif |
| 582 | |
Will Deacon | d10bcd4 | 2015-09-02 18:49:28 +0100 | [diff] [blame] | 583 | /* EL2 debug */ |
Lorenzo Pieralisi | f436b2a | 2016-01-13 14:50:03 +0000 | [diff] [blame] | 584 | mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer |
| 585 | sbfx x0, x0, #8, #4 |
| 586 | cmp x0, #1 |
| 587 | b.lt 4f // Skip if no PMU present |
Will Deacon | d10bcd4 | 2015-09-02 18:49:28 +0100 | [diff] [blame] | 588 | mrs x0, pmcr_el0 // Disable debug access traps |
| 589 | ubfx x0, x0, #11, #5 // to EL2 and allow access to |
Lorenzo Pieralisi | f436b2a | 2016-01-13 14:50:03 +0000 | [diff] [blame] | 590 | 4: |
Marc Zyngier | 8505403 | 2016-10-17 13:47:34 +0100 | [diff] [blame] | 591 | csel x0, xzr, x0, lt // all PMU counters from EL1 |
| 592 | msr mdcr_el2, x0 // (if they exist) |
Will Deacon | d10bcd4 | 2015-09-02 18:49:28 +0100 | [diff] [blame] | 593 | |
Marc Zyngier | 7dbfbe5 | 2012-11-06 19:27:59 +0000 | [diff] [blame] | 594 | /* Stage-2 translation */ |
| 595 | msr vttbr_el2, xzr |
| 596 | |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 597 | cbz x2, install_el2_stub |
| 598 | |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 599 | mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
Marc Zyngier | 1f364c8 | 2014-02-19 09:33:14 +0000 | [diff] [blame] | 600 | isb |
| 601 | ret |
| 602 | |
| 603 | install_el2_stub: |
Marc Zyngier | 712c6ff | 2012-10-19 17:46:27 +0100 | [diff] [blame] | 604 | /* Hypervisor stub */ |
Laura Abbott | ac2dec5 | 2014-11-21 21:50:39 +0000 | [diff] [blame] | 605 | adrp x0, __hyp_stub_vectors |
| 606 | add x0, x0, #:lo12:__hyp_stub_vectors |
Marc Zyngier | 712c6ff | 2012-10-19 17:46:27 +0100 | [diff] [blame] | 607 | msr vbar_el2, x0 |
| 608 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 609 | /* spsr */ |
| 610 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ |
| 611 | PSR_MODE_EL1h) |
| 612 | msr spsr_el2, x0 |
| 613 | msr elr_el2, lr |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 614 | mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 615 | eret |
| 616 | ENDPROC(el2_setup) |
| 617 | |
Marc Zyngier | f35a920 | 2012-10-26 15:40:05 +0100 | [diff] [blame] | 618 | /* |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 619 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed |
| 620 | * in x20. See arch/arm64/include/asm/virt.h for more info. |
| 621 | */ |
Ard Biesheuvel | 190c056 | 2016-04-18 17:09:41 +0200 | [diff] [blame] | 622 | set_cpu_boot_mode_flag: |
Ard Biesheuvel | 6f4d57f | 2015-03-17 09:14:29 +0100 | [diff] [blame] | 623 | adr_l x1, __boot_cpu_mode |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 624 | cmp w0, #BOOT_CPU_MODE_EL2 |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 625 | b.ne 1f |
| 626 | add x1, x1, #4 |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 627 | 1: str w0, [x1] // This CPU has booted in EL1 |
Will Deacon | d048859 | 2014-05-02 16:24:13 +0100 | [diff] [blame] | 628 | dmb sy |
| 629 | dc ivac, x1 // Invalidate potentially stale cache line |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 630 | ret |
| 631 | ENDPROC(set_cpu_boot_mode_flag) |
| 632 | |
| 633 | /* |
James Morse | b611303 | 2016-08-24 18:27:29 +0100 | [diff] [blame] | 634 | * These values are written with the MMU off, but read with the MMU on. |
| 635 | * Writers will invalidate the corresponding address, discarding up to a |
| 636 | * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures |
| 637 | * sufficient alignment that the CWG doesn't overlap another section. |
| 638 | */ |
| 639 | .pushsection ".mmuoff.data.write", "aw" |
| 640 | /* |
Marc Zyngier | f35a920 | 2012-10-26 15:40:05 +0100 | [diff] [blame] | 641 | * We need to find out the CPU boot mode long after boot, so we need to |
| 642 | * store it in a writable variable. |
| 643 | * |
| 644 | * This is not in .bss, because we set it sufficiently early that the boot-time |
| 645 | * zeroing of .bss would clobber it. |
| 646 | */ |
Ard Biesheuvel | 947bb75 | 2015-03-13 16:21:18 +0100 | [diff] [blame] | 647 | ENTRY(__boot_cpu_mode) |
Marc Zyngier | f35a920 | 2012-10-26 15:40:05 +0100 | [diff] [blame] | 648 | .long BOOT_CPU_MODE_EL2 |
Mark Rutland | 424a383 | 2015-03-13 16:14:36 +0000 | [diff] [blame] | 649 | .long BOOT_CPU_MODE_EL1 |
James Morse | b611303 | 2016-08-24 18:27:29 +0100 | [diff] [blame] | 650 | /* |
| 651 | * The booting CPU updates the failed status @__early_cpu_boot_status, |
| 652 | * with MMU turned off. |
| 653 | */ |
| 654 | ENTRY(__early_cpu_boot_status) |
| 655 | .long 0 |
| 656 | |
Marc Zyngier | f35a920 | 2012-10-26 15:40:05 +0100 | [diff] [blame] | 657 | .popsection |
| 658 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 659 | /* |
| 660 | * This provides a "holding pen" for platforms to hold all secondary |
| 661 | * cores are held until we're ready for them to initialise. |
| 662 | */ |
| 663 | ENTRY(secondary_holding_pen) |
Ard Biesheuvel | 23c8a50 | 2016-08-31 12:05:12 +0100 | [diff] [blame] | 664 | bl el2_setup // Drop to EL1, w0=cpu_boot_mode |
Matthew Leach | 828e983 | 2013-10-11 14:52:16 +0100 | [diff] [blame] | 665 | bl set_cpu_boot_mode_flag |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 666 | mrs x0, mpidr_el1 |
Ard Biesheuvel | b03cc88 | 2016-04-18 17:09:45 +0200 | [diff] [blame] | 667 | mov_q x1, MPIDR_HWID_BITMASK |
Javi Merino | 0359b0e | 2012-08-29 18:32:18 +0100 | [diff] [blame] | 668 | and x0, x0, x1 |
Ard Biesheuvel | b1c9829 | 2015-03-10 15:00:03 +0100 | [diff] [blame] | 669 | adr_l x3, secondary_holding_pen_release |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 670 | pen: ldr x4, [x3] |
| 671 | cmp x4, x0 |
| 672 | b.eq secondary_startup |
| 673 | wfe |
| 674 | b pen |
| 675 | ENDPROC(secondary_holding_pen) |
Mark Rutland | 652af89 | 2013-10-24 20:30:16 +0100 | [diff] [blame] | 676 | |
| 677 | /* |
| 678 | * Secondary entry point that jumps straight into the kernel. Only to |
| 679 | * be used where CPUs are brought online dynamically by the kernel. |
| 680 | */ |
| 681 | ENTRY(secondary_entry) |
Mark Rutland | 652af89 | 2013-10-24 20:30:16 +0100 | [diff] [blame] | 682 | bl el2_setup // Drop to EL1 |
Lorenzo Pieralisi | 85cc00e | 2013-11-18 18:56:42 +0000 | [diff] [blame] | 683 | bl set_cpu_boot_mode_flag |
Mark Rutland | 652af89 | 2013-10-24 20:30:16 +0100 | [diff] [blame] | 684 | b secondary_startup |
| 685 | ENDPROC(secondary_entry) |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 686 | |
Ard Biesheuvel | 190c056 | 2016-04-18 17:09:41 +0200 | [diff] [blame] | 687 | secondary_startup: |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 688 | /* |
| 689 | * Common entry point for secondary CPUs. |
| 690 | */ |
Marc Zyngier | a591ede | 2015-03-18 14:55:20 +0000 | [diff] [blame] | 691 | bl __cpu_setup // initialise processor |
Ard Biesheuvel | 9dcf791 | 2016-08-31 12:05:14 +0100 | [diff] [blame] | 692 | bl __enable_mmu |
| 693 | ldr x8, =__secondary_switched |
| 694 | br x8 |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 695 | ENDPROC(secondary_startup) |
| 696 | |
Ard Biesheuvel | 190c056 | 2016-04-18 17:09:41 +0200 | [diff] [blame] | 697 | __secondary_switched: |
Ard Biesheuvel | 2bf31a4 | 2015-12-26 12:46:40 +0100 | [diff] [blame] | 698 | adr_l x5, vectors |
| 699 | msr vbar_el1, x5 |
| 700 | isb |
| 701 | |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 702 | adr_l x0, secondary_data |
| 703 | ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 704 | mov sp, x0 |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 705 | and x0, x0, #~(THREAD_SIZE - 1) |
| 706 | msr sp_el0, x0 // save thread_info |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 707 | mov x29, #0 |
| 708 | b secondary_start_kernel |
| 709 | ENDPROC(__secondary_switched) |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 710 | |
| 711 | /* |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 712 | * The booting CPU updates the failed status @__early_cpu_boot_status, |
| 713 | * with MMU turned off. |
| 714 | * |
| 715 | * update_early_cpu_boot_status tmp, status |
| 716 | * - Corrupts tmp1, tmp2 |
| 717 | * - Writes 'status' to __early_cpu_boot_status and makes sure |
| 718 | * it is committed to memory. |
| 719 | */ |
| 720 | |
| 721 | .macro update_early_cpu_boot_status status, tmp1, tmp2 |
| 722 | mov \tmp2, #\status |
Ard Biesheuvel | adb4907 | 2016-04-15 12:11:21 +0200 | [diff] [blame] | 723 | adr_l \tmp1, __early_cpu_boot_status |
| 724 | str \tmp2, [\tmp1] |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 725 | dmb sy |
| 726 | dc ivac, \tmp1 // Invalidate potentially stale cache line |
| 727 | .endm |
| 728 | |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 729 | /* |
Ard Biesheuvel | 8b0a957 | 2015-03-17 08:59:53 +0100 | [diff] [blame] | 730 | * Enable the MMU. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 731 | * |
Ard Biesheuvel | 8b0a957 | 2015-03-17 08:59:53 +0100 | [diff] [blame] | 732 | * x0 = SCTLR_EL1 value for turning on the MMU. |
Ard Biesheuvel | 8b0a957 | 2015-03-17 08:59:53 +0100 | [diff] [blame] | 733 | * |
Ard Biesheuvel | 9dcf791 | 2016-08-31 12:05:14 +0100 | [diff] [blame] | 734 | * Returns to the caller via x30/lr. This requires the caller to be covered |
| 735 | * by the .idmap.text section. |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 736 | * |
| 737 | * Checks if the selected granule size is supported by the CPU. |
| 738 | * If it isn't, park the CPU |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 739 | */ |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 740 | ENTRY(__enable_mmu) |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 741 | mrs x1, ID_AA64MMFR0_EL1 |
| 742 | ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 |
| 743 | cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED |
| 744 | b.ne __no_granule_support |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 745 | update_early_cpu_boot_status 0, x1, x2 |
Ard Biesheuvel | aea73ab | 2016-08-16 21:02:32 +0200 | [diff] [blame] | 746 | adrp x1, idmap_pg_dir |
| 747 | adrp x2, swapper_pg_dir |
| 748 | msr ttbr0_el1, x1 // load TTBR0 |
| 749 | msr ttbr1_el1, x2 // load TTBR1 |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 750 | isb |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 751 | msr sctlr_el1, x0 |
| 752 | isb |
Will Deacon | 8ec4198 | 2015-08-04 17:49:36 +0100 | [diff] [blame] | 753 | /* |
| 754 | * Invalidate the local I-cache so that any instructions fetched |
| 755 | * speculatively from the PoC are discarded, since they may have |
| 756 | * been dynamically patched at the PoU. |
| 757 | */ |
| 758 | ic iallu |
| 759 | dsb nsh |
| 760 | isb |
Ard Biesheuvel | 9dcf791 | 2016-08-31 12:05:14 +0100 | [diff] [blame] | 761 | ret |
Ard Biesheuvel | 8b0a957 | 2015-03-17 08:59:53 +0100 | [diff] [blame] | 762 | ENDPROC(__enable_mmu) |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 763 | |
| 764 | __no_granule_support: |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 765 | /* Indicate that this CPU can't boot and is stuck in the kernel */ |
| 766 | update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 |
| 767 | 1: |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 768 | wfe |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 769 | wfi |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 770 | b 1b |
Suzuki K. Poulose | 4bf8b96 | 2015-10-19 14:19:35 +0100 | [diff] [blame] | 771 | ENDPROC(__no_granule_support) |
Ard Biesheuvel | e5ebeec | 2016-04-18 17:09:42 +0200 | [diff] [blame] | 772 | |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 773 | #ifdef CONFIG_RELOCATABLE |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 774 | __relocate_kernel: |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 775 | /* |
| 776 | * Iterate over each entry in the relocation table, and apply the |
| 777 | * relocations in place. |
| 778 | */ |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 779 | ldr w9, =__rela_offset // offset to reloc table |
| 780 | ldr w10, =__rela_size // size of reloc table |
| 781 | |
Ard Biesheuvel | b03cc88 | 2016-04-18 17:09:45 +0200 | [diff] [blame] | 782 | mov_q x11, KIMAGE_VADDR // default virtual offset |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 783 | add x11, x11, x23 // actual virtual offset |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 784 | add x9, x9, x11 // __va(.rela) |
| 785 | add x10, x9, x10 // __va(.rela) + sizeof(.rela) |
| 786 | |
| 787 | 0: cmp x9, x10 |
Ard Biesheuvel | 08cc55b | 2016-07-24 14:00:13 +0200 | [diff] [blame] | 788 | b.hs 1f |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 789 | ldp x11, x12, [x9], #24 |
| 790 | ldr x13, [x9, #-8] |
| 791 | cmp w12, #R_AARCH64_RELATIVE |
Ard Biesheuvel | 08cc55b | 2016-07-24 14:00:13 +0200 | [diff] [blame] | 792 | b.ne 0b |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 793 | add x13, x13, x23 // relocate |
| 794 | str x13, [x11, x23] |
| 795 | b 0b |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 796 | 1: ret |
| 797 | ENDPROC(__relocate_kernel) |
| 798 | #endif |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 799 | |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 800 | __primary_switch: |
| 801 | #ifdef CONFIG_RANDOMIZE_BASE |
| 802 | mov x19, x0 // preserve new SCTLR_EL1 value |
| 803 | mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value |
| 804 | #endif |
| 805 | |
Ard Biesheuvel | 9dcf791 | 2016-08-31 12:05:14 +0100 | [diff] [blame] | 806 | bl __enable_mmu |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 807 | #ifdef CONFIG_RELOCATABLE |
| 808 | bl __relocate_kernel |
| 809 | #ifdef CONFIG_RANDOMIZE_BASE |
| 810 | ldr x8, =__primary_switched |
Ard Biesheuvel | b929fe3 | 2016-08-31 12:05:15 +0100 | [diff] [blame] | 811 | adrp x0, __PHYS_OFFSET |
Ard Biesheuvel | 3c5e9f2 | 2016-08-31 12:05:13 +0100 | [diff] [blame] | 812 | blr x8 |
| 813 | |
| 814 | /* |
| 815 | * If we return here, we have a KASLR displacement in x23 which we need |
| 816 | * to take into account by discarding the current kernel mapping and |
| 817 | * creating a new one. |
| 818 | */ |
| 819 | msr sctlr_el1, x20 // disable the MMU |
| 820 | isb |
| 821 | bl __create_page_tables // recreate kernel mapping |
| 822 | |
| 823 | tlbi vmalle1 // Remove any stale TLB entries |
| 824 | dsb nsh |
| 825 | |
| 826 | msr sctlr_el1, x19 // re-enable the MMU |
| 827 | isb |
| 828 | ic iallu // flush instructions fetched |
| 829 | dsb nsh // via old mapping |
| 830 | isb |
| 831 | |
| 832 | bl __relocate_kernel |
| 833 | #endif |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 834 | #endif |
| 835 | ldr x8, =__primary_switched |
Ard Biesheuvel | b929fe3 | 2016-08-31 12:05:15 +0100 | [diff] [blame] | 836 | adrp x0, __PHYS_OFFSET |
Ard Biesheuvel | 0cd3def | 2016-04-18 17:09:43 +0200 | [diff] [blame] | 837 | br x8 |
| 838 | ENDPROC(__primary_switch) |