blob: 96c9f80d9550b28ceafdab692fe996588c6dd180 [file] [log] [blame]
Yong Shen5e428d52010-12-14 14:00:55 +08001/*
2 * Regulator Driver for Freescale MC13892 PMIC
3 *
4 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
5 *
6 * Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/mfd/mc13892.h>
14#include <linux/regulator/machine.h>
15#include <linux/regulator/driver.h>
16#include <linux/platform_device.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/init.h>
20#include <linux/err.h>
Paul Gortmaker65602c32011-07-17 16:28:23 -040021#include <linux/module.h>
Yong Shen5e428d52010-12-14 14:00:55 +080022#include "mc13xxx.h"
23
24#define MC13892_REVISION 7
25
26#define MC13892_POWERCTL0 13
27#define MC13892_POWERCTL0_USEROFFSPI 3
28#define MC13892_POWERCTL0_VCOINCELLVSEL 20
29#define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20)
30#define MC13892_POWERCTL0_VCOINCELLEN (1<<23)
31
32#define MC13892_SWITCHERS0_SWxHI (1<<23)
33
34#define MC13892_SWITCHERS0 24
35#define MC13892_SWITCHERS0_SW1VSEL 0
36#define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0)
37#define MC13892_SWITCHERS0_SW1HI (1<<23)
38#define MC13892_SWITCHERS0_SW1EN 0
39
40#define MC13892_SWITCHERS1 25
41#define MC13892_SWITCHERS1_SW2VSEL 0
42#define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0)
43#define MC13892_SWITCHERS1_SW2HI (1<<23)
44#define MC13892_SWITCHERS1_SW2EN 0
45
46#define MC13892_SWITCHERS2 26
47#define MC13892_SWITCHERS2_SW3VSEL 0
48#define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0)
49#define MC13892_SWITCHERS2_SW3HI (1<<23)
50#define MC13892_SWITCHERS2_SW3EN 0
51
52#define MC13892_SWITCHERS3 27
53#define MC13892_SWITCHERS3_SW4VSEL 0
54#define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0)
55#define MC13892_SWITCHERS3_SW4HI (1<<23)
56#define MC13892_SWITCHERS3_SW4EN 0
57
58#define MC13892_SWITCHERS4 28
59#define MC13892_SWITCHERS4_SW1MODE 0
60#define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0)
61#define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0)
62#define MC13892_SWITCHERS4_SW2MODE 10
63#define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10)
64#define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10)
65
66#define MC13892_SWITCHERS5 29
67#define MC13892_SWITCHERS5_SW3MODE 0
68#define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0)
69#define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0)
70#define MC13892_SWITCHERS5_SW4MODE 8
71#define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8)
72#define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8)
73#define MC13892_SWITCHERS5_SWBSTEN (1<<20)
74
75#define MC13892_REGULATORSETTING0 30
76#define MC13892_REGULATORSETTING0_VGEN1VSEL 0
77#define MC13892_REGULATORSETTING0_VDIGVSEL 4
78#define MC13892_REGULATORSETTING0_VGEN2VSEL 6
79#define MC13892_REGULATORSETTING0_VPLLVSEL 9
80#define MC13892_REGULATORSETTING0_VUSB2VSEL 11
81#define MC13892_REGULATORSETTING0_VGEN3VSEL 14
82#define MC13892_REGULATORSETTING0_VCAMVSEL 16
83
84#define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
85#define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
86#define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6)
87#define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
88#define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
89#define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14)
90#define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
91
92#define MC13892_REGULATORSETTING1 31
93#define MC13892_REGULATORSETTING1_VVIDEOVSEL 2
94#define MC13892_REGULATORSETTING1_VAUDIOVSEL 4
95#define MC13892_REGULATORSETTING1_VSDVSEL 6
96
97#define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
98#define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
99#define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
100
101#define MC13892_REGULATORMODE0 32
102#define MC13892_REGULATORMODE0_VGEN1EN (1<<0)
103#define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1)
104#define MC13892_REGULATORMODE0_VGEN1MODE (1<<2)
105#define MC13892_REGULATORMODE0_VIOHIEN (1<<3)
106#define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4)
107#define MC13892_REGULATORMODE0_VIOHIMODE (1<<5)
108#define MC13892_REGULATORMODE0_VDIGEN (1<<9)
109#define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10)
110#define MC13892_REGULATORMODE0_VDIGMODE (1<<11)
111#define MC13892_REGULATORMODE0_VGEN2EN (1<<12)
112#define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13)
113#define MC13892_REGULATORMODE0_VGEN2MODE (1<<14)
114#define MC13892_REGULATORMODE0_VPLLEN (1<<15)
115#define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16)
116#define MC13892_REGULATORMODE0_VPLLMODE (1<<17)
117#define MC13892_REGULATORMODE0_VUSB2EN (1<<18)
118#define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19)
119#define MC13892_REGULATORMODE0_VUSB2MODE (1<<20)
120
121#define MC13892_REGULATORMODE1 33
122#define MC13892_REGULATORMODE1_VGEN3EN (1<<0)
123#define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1)
124#define MC13892_REGULATORMODE1_VGEN3MODE (1<<2)
125#define MC13892_REGULATORMODE1_VCAMEN (1<<6)
126#define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7)
127#define MC13892_REGULATORMODE1_VCAMMODE (1<<8)
128#define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
129#define MC13892_REGULATORMODE1_VVIDEOEN (1<<12)
130#define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13)
131#define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14)
132#define MC13892_REGULATORMODE1_VAUDIOEN (1<<15)
133#define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16)
134#define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17)
135#define MC13892_REGULATORMODE1_VSDEN (1<<18)
136#define MC13892_REGULATORMODE1_VSDSTDBY (1<<19)
137#define MC13892_REGULATORMODE1_VSDMODE (1<<20)
138
139#define MC13892_POWERMISC 34
140#define MC13892_POWERMISC_GPO1EN (1<<6)
141#define MC13892_POWERMISC_GPO2EN (1<<8)
142#define MC13892_POWERMISC_GPO3EN (1<<10)
143#define MC13892_POWERMISC_GPO4EN (1<<12)
144#define MC13892_POWERMISC_PWGT1SPIEN (1<<15)
145#define MC13892_POWERMISC_PWGT2SPIEN (1<<16)
146#define MC13892_POWERMISC_GPO4ADINEN (1<<21)
147
148#define MC13892_POWERMISC_PWGTSPI_M (3 << 15)
149
150#define MC13892_USB1 50
151#define MC13892_USB1_VUSBEN (1<<3)
152
Axel Lin34e74f32012-06-08 15:41:48 +0800153static const unsigned int mc13892_vcoincell[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800154 2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
155 3200000, 3300000,
156};
157
Axel Lin34e74f32012-06-08 15:41:48 +0800158static const unsigned int mc13892_sw1[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800159 600000, 625000, 650000, 675000, 700000, 725000,
160 750000, 775000, 800000, 825000, 850000, 875000,
161 900000, 925000, 950000, 975000, 1000000, 1025000,
162 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
163 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
164 1350000, 1375000
165};
166
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600167/*
168 * Note: this table is used to derive SWxVSEL by index into
169 * the array. Offset the values by the index of 1100000uV
170 * to get the actual register value for that voltage selector
171 * if the HI bit is to be set as well.
172 */
173#define MC13892_SWxHI_SEL_OFFSET 20
174
Axel Lin34e74f32012-06-08 15:41:48 +0800175static const unsigned int mc13892_sw[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800176 600000, 625000, 650000, 675000, 700000, 725000,
177 750000, 775000, 800000, 825000, 850000, 875000,
178 900000, 925000, 950000, 975000, 1000000, 1025000,
179 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
180 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
181 1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
182 1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
183 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
184 1800000, 1825000, 1850000, 1875000
185};
186
Axel Lin34e74f32012-06-08 15:41:48 +0800187static const unsigned int mc13892_swbst[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800188 5000000,
189};
190
Axel Lin34e74f32012-06-08 15:41:48 +0800191static const unsigned int mc13892_viohi[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800192 2775000,
193};
194
Axel Lin34e74f32012-06-08 15:41:48 +0800195static const unsigned int mc13892_vpll[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800196 1050000, 1250000, 1650000, 1800000,
197};
198
Axel Lin34e74f32012-06-08 15:41:48 +0800199static const unsigned int mc13892_vdig[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800200 1050000, 1250000, 1650000, 1800000,
201};
202
Axel Lin34e74f32012-06-08 15:41:48 +0800203static const unsigned int mc13892_vsd[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800204 1800000, 2000000, 2600000, 2700000,
205 2800000, 2900000, 3000000, 3150000,
206};
207
Axel Lin34e74f32012-06-08 15:41:48 +0800208static const unsigned int mc13892_vusb2[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800209 2400000, 2600000, 2700000, 2775000,
210};
211
Axel Lin34e74f32012-06-08 15:41:48 +0800212static const unsigned int mc13892_vvideo[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800213 2700000, 2775000, 2500000, 2600000,
214};
215
Axel Lin34e74f32012-06-08 15:41:48 +0800216static const unsigned int mc13892_vaudio[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800217 2300000, 2500000, 2775000, 3000000,
218};
219
Axel Lin34e74f32012-06-08 15:41:48 +0800220static const unsigned int mc13892_vcam[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800221 2500000, 2600000, 2750000, 3000000,
222};
223
Axel Lin34e74f32012-06-08 15:41:48 +0800224static const unsigned int mc13892_vgen1[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800225 1200000, 1500000, 2775000, 3150000,
226};
227
Axel Lin34e74f32012-06-08 15:41:48 +0800228static const unsigned int mc13892_vgen2[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800229 1200000, 1500000, 1600000, 1800000,
230 2700000, 2800000, 3000000, 3150000,
231};
232
Axel Lin34e74f32012-06-08 15:41:48 +0800233static const unsigned int mc13892_vgen3[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800234 1800000, 2900000,
235};
236
Axel Lin34e74f32012-06-08 15:41:48 +0800237static const unsigned int mc13892_vusb[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800238 3300000,
239};
240
Axel Lin34e74f32012-06-08 15:41:48 +0800241static const unsigned int mc13892_gpo[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800242 2750000,
243};
244
Axel Lin34e74f32012-06-08 15:41:48 +0800245static const unsigned int mc13892_pwgtdrv[] = {
Yong Shen5e428d52010-12-14 14:00:55 +0800246 5000000,
247};
248
249static struct regulator_ops mc13892_gpo_regulator_ops;
Yong Shen5e428d52010-12-14 14:00:55 +0800250static struct regulator_ops mc13892_sw_regulator_ops;
251
252
253#define MC13892_FIXED_DEFINE(name, reg, voltages) \
254 MC13xxx_FIXED_DEFINE(MC13892_, name, reg, voltages, \
255 mc13xxx_fixed_regulator_ops)
256
257#define MC13892_GPO_DEFINE(name, reg, voltages) \
258 MC13xxx_GPO_DEFINE(MC13892_, name, reg, voltages, \
259 mc13892_gpo_regulator_ops)
260
261#define MC13892_SW_DEFINE(name, reg, vsel_reg, voltages) \
262 MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
263 mc13892_sw_regulator_ops)
264
265#define MC13892_DEFINE_REGU(name, reg, vsel_reg, voltages) \
266 MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
267 mc13xxx_regulator_ops)
268
269static struct mc13xxx_regulator mc13892_regulators[] = {
Axel Lin327e15a2011-05-10 19:10:36 +0800270 MC13892_DEFINE_REGU(VCOINCELL, POWERCTL0, POWERCTL0, mc13892_vcoincell),
Yong Shen5e428d52010-12-14 14:00:55 +0800271 MC13892_SW_DEFINE(SW1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
272 MC13892_SW_DEFINE(SW2, SWITCHERS1, SWITCHERS1, mc13892_sw),
273 MC13892_SW_DEFINE(SW3, SWITCHERS2, SWITCHERS2, mc13892_sw),
274 MC13892_SW_DEFINE(SW4, SWITCHERS3, SWITCHERS3, mc13892_sw),
275 MC13892_FIXED_DEFINE(SWBST, SWITCHERS5, mc13892_swbst),
276 MC13892_FIXED_DEFINE(VIOHI, REGULATORMODE0, mc13892_viohi),
277 MC13892_DEFINE_REGU(VPLL, REGULATORMODE0, REGULATORSETTING0, \
278 mc13892_vpll),
279 MC13892_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \
280 mc13892_vdig),
281 MC13892_DEFINE_REGU(VSD, REGULATORMODE1, REGULATORSETTING1, \
282 mc13892_vsd),
283 MC13892_DEFINE_REGU(VUSB2, REGULATORMODE0, REGULATORSETTING0, \
284 mc13892_vusb2),
285 MC13892_DEFINE_REGU(VVIDEO, REGULATORMODE1, REGULATORSETTING1, \
286 mc13892_vvideo),
287 MC13892_DEFINE_REGU(VAUDIO, REGULATORMODE1, REGULATORSETTING1, \
288 mc13892_vaudio),
289 MC13892_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \
290 mc13892_vcam),
291 MC13892_DEFINE_REGU(VGEN1, REGULATORMODE0, REGULATORSETTING0, \
292 mc13892_vgen1),
293 MC13892_DEFINE_REGU(VGEN2, REGULATORMODE0, REGULATORSETTING0, \
294 mc13892_vgen2),
295 MC13892_DEFINE_REGU(VGEN3, REGULATORMODE1, REGULATORSETTING0, \
296 mc13892_vgen3),
297 MC13892_FIXED_DEFINE(VUSB, USB1, mc13892_vusb),
298 MC13892_GPO_DEFINE(GPO1, POWERMISC, mc13892_gpo),
299 MC13892_GPO_DEFINE(GPO2, POWERMISC, mc13892_gpo),
300 MC13892_GPO_DEFINE(GPO3, POWERMISC, mc13892_gpo),
301 MC13892_GPO_DEFINE(GPO4, POWERMISC, mc13892_gpo),
302 MC13892_GPO_DEFINE(PWGT1SPI, POWERMISC, mc13892_pwgtdrv),
303 MC13892_GPO_DEFINE(PWGT2SPI, POWERMISC, mc13892_pwgtdrv),
304};
305
Mark Brown27315cf2010-12-16 15:29:56 +0000306static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
307 u32 val)
Yong Shen5e428d52010-12-14 14:00:55 +0800308{
309 struct mc13xxx *mc13892 = priv->mc13xxx;
310 int ret;
311 u32 valread;
312
313 BUG_ON(val & ~mask);
314
Axel Lin825d1052012-07-19 11:17:15 +0800315 mc13xxx_lock(priv->mc13xxx);
Yong Shen5e428d52010-12-14 14:00:55 +0800316 ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
317 if (ret)
Axel Lin825d1052012-07-19 11:17:15 +0800318 goto out;
Yong Shen5e428d52010-12-14 14:00:55 +0800319
320 /* Update the stored state for Power Gates. */
321 priv->powermisc_pwgt_state =
322 (priv->powermisc_pwgt_state & ~mask) | val;
323 priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
324
325 /* Construct the new register value */
326 valread = (valread & ~mask) | val;
327 /* Overwrite the PWGTxEN with the stored version */
328 valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
329 priv->powermisc_pwgt_state;
330
Axel Lin825d1052012-07-19 11:17:15 +0800331 ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
332out:
333 mc13xxx_unlock(priv->mc13xxx);
334 return ret;
Yong Shen5e428d52010-12-14 14:00:55 +0800335}
336
337static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
338{
339 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
340 int id = rdev_get_id(rdev);
Yong Shen5e428d52010-12-14 14:00:55 +0800341 u32 en_val = mc13892_regulators[id].enable_bit;
342 u32 mask = mc13892_regulators[id].enable_bit;
343
344 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
345
346 /* Power Gate enable value is 0 */
347 if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
348 en_val = 0;
349
350 if (id == MC13892_GPO4)
351 mask |= MC13892_POWERMISC_GPO4ADINEN;
352
Axel Lin825d1052012-07-19 11:17:15 +0800353 return mc13892_powermisc_rmw(priv, mask, en_val);
Yong Shen5e428d52010-12-14 14:00:55 +0800354}
355
356static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
357{
358 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
359 int id = rdev_get_id(rdev);
Yong Shen5e428d52010-12-14 14:00:55 +0800360 u32 dis_val = 0;
361
362 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
363
364 /* Power Gate disable value is 1 */
365 if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
366 dis_val = mc13892_regulators[id].enable_bit;
367
Axel Lin825d1052012-07-19 11:17:15 +0800368 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
Yong Shen5e428d52010-12-14 14:00:55 +0800369 dis_val);
Yong Shen5e428d52010-12-14 14:00:55 +0800370}
371
372static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
373{
374 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
375 int ret, id = rdev_get_id(rdev);
376 unsigned int val;
377
378 mc13xxx_lock(priv->mc13xxx);
379 ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
380 mc13xxx_unlock(priv->mc13xxx);
381
382 if (ret)
383 return ret;
384
385 /* Power Gates state is stored in powermisc_pwgt_state
386 * where the meaning of bits is negated */
387 val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
388 (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
389
390 return (val & mc13892_regulators[id].enable_bit) != 0;
391}
392
393
394static struct regulator_ops mc13892_gpo_regulator_ops = {
395 .enable = mc13892_gpo_regulator_enable,
396 .disable = mc13892_gpo_regulator_disable,
397 .is_enabled = mc13892_gpo_regulator_is_enabled,
Axel Lin34e74f32012-06-08 15:41:48 +0800398 .list_voltage = regulator_list_voltage_table,
Yong Shen5e428d52010-12-14 14:00:55 +0800399 .set_voltage = mc13xxx_fixed_regulator_set_voltage,
Yong Shen5e428d52010-12-14 14:00:55 +0800400};
401
Axel Linf1dcf9e2012-07-19 15:11:39 +0800402static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
Yong Shen5e428d52010-12-14 14:00:55 +0800403{
404 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
405 int ret, id = rdev_get_id(rdev);
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600406 unsigned int val, selector;
Yong Shen5e428d52010-12-14 14:00:55 +0800407
408 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
409
410 mc13xxx_lock(priv->mc13xxx);
411 ret = mc13xxx_reg_read(priv->mc13xxx,
412 mc13892_regulators[id].vsel_reg, &val);
413 mc13xxx_unlock(priv->mc13xxx);
414 if (ret)
415 return ret;
416
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600417 /*
418 * Figure out if the HI bit is set inside the switcher mode register
419 * since this means the selector value we return is at a different
420 * offset into the selector table.
421 *
422 * According to the MC13892 documentation note 59 (Table 47) the SW1
423 * buck switcher does not support output range programming therefore
424 * the HI bit must always remain 0. So do not do anything strange if
425 * our register is MC13892_SWITCHERS0.
426 */
Yong Shen5e428d52010-12-14 14:00:55 +0800427
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600428 selector = val & mc13892_regulators[id].vsel_mask;
Yong Shen5e428d52010-12-14 14:00:55 +0800429
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600430 if ((mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) &&
431 (val & MC13892_SWITCHERS0_SWxHI)) {
432 selector += MC13892_SWxHI_SEL_OFFSET;
433 }
434
435 dev_dbg(rdev_get_dev(rdev), "%s id: %d val: 0x%08x selector: %d\n",
436 __func__, id, val, selector);
437
438 return selector;
Yong Shen5e428d52010-12-14 14:00:55 +0800439}
440
Axel Lin939b62d2012-03-20 10:46:35 +0800441static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
442 unsigned selector)
Yong Shen5e428d52010-12-14 14:00:55 +0800443{
444 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
Axel Lin8db98442012-07-19 15:10:31 +0800445 int volt, mask, id = rdev_get_id(rdev);
446 u32 reg_value;
Yong Shen5e428d52010-12-14 14:00:55 +0800447 int ret;
448
Axel Lin8db98442012-07-19 15:10:31 +0800449 volt = rdev->desc->volt_table[selector];
450 mask = mc13892_regulators[id].vsel_mask;
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600451 reg_value = selector;
Axel Lin8db98442012-07-19 15:10:31 +0800452
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600453 /*
454 * Don't mess with the HI bit or support HI voltage offsets for SW1.
455 *
456 * Since the get_voltage_sel callback has given a fudged value for
457 * the selector offset, we need to back out that offset if HI is
458 * to be set so we write the correct value to the register.
459 *
460 * The HI bit addition and selector offset handling COULD be more
461 * complicated by shifting and masking off the voltage selector part
462 * of the register then logical OR it back in, but since the selector
463 * is at bits 4:0 there is very little point. This makes the whole
464 * thing more readable and we do far less work.
465 */
466
467 if (mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) {
Axel Lin78040b62013-04-24 11:51:12 +0800468 mask |= MC13892_SWITCHERS0_SWxHI;
469
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600470 if (volt > 1375000) {
471 reg_value -= MC13892_SWxHI_SEL_OFFSET;
472 reg_value |= MC13892_SWITCHERS0_SWxHI;
Axel Lin78040b62013-04-24 11:51:12 +0800473 } else {
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600474 reg_value &= ~MC13892_SWITCHERS0_SWxHI;
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600475 }
Axel Lin8db98442012-07-19 15:10:31 +0800476 }
Yong Shen5e428d52010-12-14 14:00:55 +0800477
478 mc13xxx_lock(priv->mc13xxx);
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600479 ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg, mask,
Axel Lin8db98442012-07-19 15:10:31 +0800480 reg_value);
Yong Shen5e428d52010-12-14 14:00:55 +0800481 mc13xxx_unlock(priv->mc13xxx);
482
483 return ret;
484}
485
486static struct regulator_ops mc13892_sw_regulator_ops = {
Axel Lin34e74f32012-06-08 15:41:48 +0800487 .list_voltage = regulator_list_voltage_table,
Axel Lin3bdf5992013-04-24 20:42:29 +0800488 .map_voltage = regulator_map_voltage_ascend,
Axel Lin939b62d2012-03-20 10:46:35 +0800489 .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
Axel Linf1dcf9e2012-07-19 15:11:39 +0800490 .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
Yong Shen5e428d52010-12-14 14:00:55 +0800491};
492
493static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
494{
495 unsigned int en_val = 0;
496 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
497 int ret, id = rdev_get_id(rdev);
498
499 if (mode == REGULATOR_MODE_FAST)
500 en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
501
502 mc13xxx_lock(priv->mc13xxx);
503 ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
504 MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
505 mc13xxx_unlock(priv->mc13xxx);
506
507 return ret;
508}
509
Mark Brown27315cf2010-12-16 15:29:56 +0000510static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
Yong Shen5e428d52010-12-14 14:00:55 +0800511{
512 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
513 int ret, id = rdev_get_id(rdev);
514 unsigned int val;
515
516 mc13xxx_lock(priv->mc13xxx);
517 ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
518 mc13xxx_unlock(priv->mc13xxx);
519
520 if (ret)
521 return ret;
522
523 if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
524 return REGULATOR_MODE_FAST;
525
526 return REGULATOR_MODE_NORMAL;
527}
528
529
Bill Pembertona5023572012-11-19 13:22:22 -0500530static int mc13892_regulator_probe(struct platform_device *pdev)
Yong Shen5e428d52010-12-14 14:00:55 +0800531{
532 struct mc13xxx_regulator_priv *priv;
533 struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
Samuel Ortizc8a03c962011-04-08 01:55:01 +0200534 struct mc13xxx_regulator_platform_data *pdata =
535 dev_get_platdata(&pdev->dev);
Shawn Guo93bcb232011-12-21 23:00:46 +0800536 struct mc13xxx_regulator_init_data *mc13xxx_data;
Axel Lina9d58012012-04-10 13:51:06 +0800537 struct regulator_config config = { };
Yong Shen5e428d52010-12-14 14:00:55 +0800538 int i, ret;
Alexander Shiyaneb0d8e72013-04-27 10:29:24 +0400539 int num_regulators = 0;
Yong Shen5e428d52010-12-14 14:00:55 +0800540 u32 val;
541
Shawn Guo93bcb232011-12-21 23:00:46 +0800542 num_regulators = mc13xxx_get_num_regulators_dt(pdev);
Matt Sealey2c8a5dc2013-01-21 12:25:45 -0600543
Shawn Guo93bcb232011-12-21 23:00:46 +0800544 if (num_regulators <= 0 && pdata)
545 num_regulators = pdata->num_regulators;
546 if (num_regulators <= 0)
547 return -EINVAL;
548
Fabio Estevam4fef21e2011-12-29 20:05:00 -0200549 priv = devm_kzalloc(&pdev->dev, sizeof(*priv) +
Shawn Guo93bcb232011-12-21 23:00:46 +0800550 num_regulators * sizeof(priv->regulators[0]),
Yong Shen5e428d52010-12-14 14:00:55 +0800551 GFP_KERNEL);
552 if (!priv)
553 return -ENOMEM;
554
Shawn Guo93bcb232011-12-21 23:00:46 +0800555 priv->num_regulators = num_regulators;
Yong Shen5e428d52010-12-14 14:00:55 +0800556 priv->mc13xxx_regulators = mc13892_regulators;
557 priv->mc13xxx = mc13892;
Shawn Guo93bcb232011-12-21 23:00:46 +0800558 platform_set_drvdata(pdev, priv);
Yong Shen5e428d52010-12-14 14:00:55 +0800559
560 mc13xxx_lock(mc13892);
561 ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
562 if (ret)
Axel Lin5777d9b2012-03-15 12:49:09 +0800563 goto err_unlock;
Yong Shen5e428d52010-12-14 14:00:55 +0800564
Matt Sealeyccf3ed72013-01-21 11:38:40 -0600565 /* enable switch auto mode (on 2.0A silicon only) */
Yong Shen5e428d52010-12-14 14:00:55 +0800566 if ((val & 0x0000FFFF) == 0x45d0) {
567 ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
568 MC13892_SWITCHERS4_SW1MODE_M |
569 MC13892_SWITCHERS4_SW2MODE_M,
570 MC13892_SWITCHERS4_SW1MODE_AUTO |
571 MC13892_SWITCHERS4_SW2MODE_AUTO);
572 if (ret)
Axel Lin5777d9b2012-03-15 12:49:09 +0800573 goto err_unlock;
Yong Shen5e428d52010-12-14 14:00:55 +0800574
Axel Lin923430c2011-01-03 23:57:38 +0800575 ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
Yong Shen5e428d52010-12-14 14:00:55 +0800576 MC13892_SWITCHERS5_SW3MODE_M |
577 MC13892_SWITCHERS5_SW4MODE_M,
578 MC13892_SWITCHERS5_SW3MODE_AUTO |
579 MC13892_SWITCHERS5_SW4MODE_AUTO);
580 if (ret)
Axel Lin5777d9b2012-03-15 12:49:09 +0800581 goto err_unlock;
Yong Shen5e428d52010-12-14 14:00:55 +0800582 }
583 mc13xxx_unlock(mc13892);
584
585 mc13892_regulators[MC13892_VCAM].desc.ops->set_mode
586 = mc13892_vcam_set_mode;
587 mc13892_regulators[MC13892_VCAM].desc.ops->get_mode
588 = mc13892_vcam_get_mode;
Shawn Guo93bcb232011-12-21 23:00:46 +0800589
590 mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
Alexander Shiyaneb0d8e72013-04-27 10:29:24 +0400591 ARRAY_SIZE(mc13892_regulators));
Matt Sealey2c8a5dc2013-01-21 12:25:45 -0600592
Alexander Shiyaneb0d8e72013-04-27 10:29:24 +0400593 for (i = 0; i < priv->num_regulators; i++) {
Shawn Guo93bcb232011-12-21 23:00:46 +0800594 struct regulator_init_data *init_data;
595 struct regulator_desc *desc;
596 struct device_node *node = NULL;
597 int id;
598
599 if (mc13xxx_data) {
600 id = mc13xxx_data[i].id;
601 init_data = mc13xxx_data[i].init_data;
602 node = mc13xxx_data[i].node;
603 } else {
604 id = pdata->regulators[i].id;
605 init_data = pdata->regulators[i].init_data;
606 }
607 desc = &mc13892_regulators[id].desc;
608
Axel Lina9d58012012-04-10 13:51:06 +0800609 config.dev = &pdev->dev;
610 config.init_data = init_data;
611 config.driver_data = priv;
612 config.of_node = node;
Yong Shen5e428d52010-12-14 14:00:55 +0800613
Sachin Kamat8c0b4ab2013-09-04 12:01:00 +0530614 priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
615 &config);
Yong Shen5e428d52010-12-14 14:00:55 +0800616 if (IS_ERR(priv->regulators[i])) {
617 dev_err(&pdev->dev, "failed to register regulator %s\n",
618 mc13892_regulators[i].desc.name);
Sachin Kamat8c0b4ab2013-09-04 12:01:00 +0530619 return PTR_ERR(priv->regulators[i]);
Yong Shen5e428d52010-12-14 14:00:55 +0800620 }
621 }
622
Yong Shen5e428d52010-12-14 14:00:55 +0800623 return 0;
Yong Shen5e428d52010-12-14 14:00:55 +0800624
Axel Lin5777d9b2012-03-15 12:49:09 +0800625err_unlock:
Yong Shen5e428d52010-12-14 14:00:55 +0800626 mc13xxx_unlock(mc13892);
Yong Shen5e428d52010-12-14 14:00:55 +0800627 return ret;
628}
629
Yong Shen5e428d52010-12-14 14:00:55 +0800630static struct platform_driver mc13892_regulator_driver = {
631 .driver = {
632 .name = "mc13892-regulator",
633 .owner = THIS_MODULE,
634 },
Yong Shen5e428d52010-12-14 14:00:55 +0800635 .probe = mc13892_regulator_probe,
636};
637
638static int __init mc13892_regulator_init(void)
639{
640 return platform_driver_register(&mc13892_regulator_driver);
641}
642subsys_initcall(mc13892_regulator_init);
643
644static void __exit mc13892_regulator_exit(void)
645{
646 platform_driver_unregister(&mc13892_regulator_driver);
647}
648module_exit(mc13892_regulator_exit);
649
650MODULE_LICENSE("GPL v2");
651MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
652MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
653MODULE_ALIAS("platform:mc13892-regulator");