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Ben Dooks96ce2382006-06-18 23:06:41 +01001/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 * 25-Jul-2005 BJD Split from irq.c
22 *
23*/
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/ptrace.h>
30#include <linux/sysdev.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/io.h>
35
36#include <asm/mach/irq.h>
37
38#include <asm/arch/regs-irq.h>
39#include <asm/arch/regs-gpio.h>
40
41#include "cpu.h"
42#include "pm.h"
43#include "irq.h"
44
45/* camera irq */
46
47static void s3c_irq_demux_cam(unsigned int irq,
48 struct irqdesc *desc,
49 struct pt_regs *regs)
50{
51 unsigned int subsrc, submsk;
52 struct irqdesc *mydesc;
53
54 /* read the current pending interrupts, and the mask
55 * for what it is available */
56
57 subsrc = __raw_readl(S3C2410_SUBSRCPND);
58 submsk = __raw_readl(S3C2410_INTSUBMSK);
59
60 subsrc &= ~submsk;
61 subsrc >>= 11;
62 subsrc &= 3;
63
64 if (subsrc != 0) {
65 if (subsrc & 1) {
66 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
67 desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs);
68 }
69 if (subsrc & 2) {
70 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
71 desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs);
72 }
73 }
74}
75
76#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
77
78static void
79s3c_irq_cam_mask(unsigned int irqno)
80{
81 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
82}
83
84static void
85s3c_irq_cam_unmask(unsigned int irqno)
86{
87 s3c_irqsub_unmask(irqno, INTMSK_CAM);
88}
89
90static void
91s3c_irq_cam_ack(unsigned int irqno)
92{
93 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
94}
95
96static struct irqchip s3c_irq_cam = {
97 .mask = s3c_irq_cam_mask,
98 .unmask = s3c_irq_cam_unmask,
99 .ack = s3c_irq_cam_ack,
100};
101
102static int s3c244x_irq_add(struct sys_device *sysdev)
103{
104 unsigned int irqno;
105
106 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
107 set_irq_handler(IRQ_NFCON, do_level_IRQ);
108 set_irq_flags(IRQ_NFCON, IRQF_VALID);
109
110 /* add chained handler for camera */
111
112 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
113 set_irq_handler(IRQ_CAM, do_level_IRQ);
114 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
115
116 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
117 set_irq_chip(irqno, &s3c_irq_cam);
118 set_irq_handler(irqno, do_level_IRQ);
119 set_irq_flags(irqno, IRQF_VALID);
120 }
121
122 return 0;
123}
124
125static struct sysdev_driver s3c244x_irq_driver = {
126 .add = s3c244x_irq_add,
127};
128
129static int s3c2440_irq_init(void)
130{
131 return sysdev_driver_register(&s3c2440_sysclass, &s3c244x_irq_driver);
132}
133
134arch_initcall(s3c2440_irq_init);
135
136
137static int s3c2442_irq_init(void)
138{
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c244x_irq_driver);
140}
141
142arch_initcall(s3c2442_irq_init);