Alex Smith | ae02ab0 | 2016-01-04 12:34:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * JZ4780 NAND driver |
| 3 | * |
| 4 | * Copyright (c) 2015 Imagination Technologies |
| 5 | * Author: Alex Smith <alex.smith@imgtec.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published |
| 9 | * by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/gpio/consumer.h> |
| 20 | #include <linux/of_mtd.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/mtd/nand.h> |
| 25 | #include <linux/mtd/partitions.h> |
| 26 | |
| 27 | #include <linux/jz4780-nemc.h> |
| 28 | |
| 29 | #include "jz4780_bch.h" |
| 30 | |
| 31 | #define DRV_NAME "jz4780-nand" |
| 32 | |
| 33 | #define OFFSET_DATA 0x00000000 |
| 34 | #define OFFSET_CMD 0x00400000 |
| 35 | #define OFFSET_ADDR 0x00800000 |
| 36 | |
| 37 | /* Command delay when there is no R/B pin. */ |
| 38 | #define RB_DELAY_US 100 |
| 39 | |
| 40 | struct jz4780_nand_cs { |
| 41 | unsigned int bank; |
| 42 | void __iomem *base; |
| 43 | }; |
| 44 | |
| 45 | struct jz4780_nand_controller { |
| 46 | struct device *dev; |
| 47 | struct jz4780_bch *bch; |
| 48 | struct nand_hw_control controller; |
| 49 | unsigned int num_banks; |
| 50 | struct list_head chips; |
| 51 | int selected; |
| 52 | struct jz4780_nand_cs cs[]; |
| 53 | }; |
| 54 | |
| 55 | struct jz4780_nand_chip { |
| 56 | struct nand_chip chip; |
| 57 | struct list_head chip_list; |
| 58 | |
| 59 | struct nand_ecclayout ecclayout; |
| 60 | |
| 61 | struct gpio_desc *busy_gpio; |
| 62 | struct gpio_desc *wp_gpio; |
| 63 | unsigned int reading: 1; |
| 64 | }; |
| 65 | |
| 66 | static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd) |
| 67 | { |
| 68 | return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip); |
| 69 | } |
| 70 | |
| 71 | static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl) |
| 72 | { |
| 73 | return container_of(ctrl, struct jz4780_nand_controller, controller); |
| 74 | } |
| 75 | |
| 76 | static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr) |
| 77 | { |
| 78 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 79 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); |
| 80 | struct jz4780_nand_cs *cs; |
| 81 | |
| 82 | /* Ensure the currently selected chip is deasserted. */ |
| 83 | if (chipnr == -1 && nfc->selected >= 0) { |
| 84 | cs = &nfc->cs[nfc->selected]; |
| 85 | jz4780_nemc_assert(nfc->dev, cs->bank, false); |
| 86 | } |
| 87 | |
| 88 | nfc->selected = chipnr; |
| 89 | } |
| 90 | |
| 91 | static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, |
| 92 | unsigned int ctrl) |
| 93 | { |
| 94 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 95 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); |
| 96 | struct jz4780_nand_cs *cs; |
| 97 | |
| 98 | if (WARN_ON(nfc->selected < 0)) |
| 99 | return; |
| 100 | |
| 101 | cs = &nfc->cs[nfc->selected]; |
| 102 | |
| 103 | jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE); |
| 104 | |
| 105 | if (cmd == NAND_CMD_NONE) |
| 106 | return; |
| 107 | |
| 108 | if (ctrl & NAND_ALE) |
| 109 | writeb(cmd, cs->base + OFFSET_ADDR); |
| 110 | else if (ctrl & NAND_CLE) |
| 111 | writeb(cmd, cs->base + OFFSET_CMD); |
| 112 | } |
| 113 | |
| 114 | static int jz4780_nand_dev_ready(struct mtd_info *mtd) |
| 115 | { |
| 116 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 117 | |
| 118 | return !gpiod_get_value_cansleep(nand->busy_gpio); |
| 119 | } |
| 120 | |
| 121 | static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode) |
| 122 | { |
| 123 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 124 | |
| 125 | nand->reading = (mode == NAND_ECC_READ); |
| 126 | } |
| 127 | |
| 128 | static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat, |
| 129 | u8 *ecc_code) |
| 130 | { |
| 131 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 132 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); |
| 133 | struct jz4780_bch_params params; |
| 134 | |
| 135 | /* |
| 136 | * Don't need to generate the ECC when reading, BCH does it for us as |
| 137 | * part of decoding/correction. |
| 138 | */ |
| 139 | if (nand->reading) |
| 140 | return 0; |
| 141 | |
| 142 | params.size = nand->chip.ecc.size; |
| 143 | params.bytes = nand->chip.ecc.bytes; |
| 144 | params.strength = nand->chip.ecc.strength; |
| 145 | |
| 146 | return jz4780_bch_calculate(nfc->bch, ¶ms, dat, ecc_code); |
| 147 | } |
| 148 | |
| 149 | static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat, |
| 150 | u8 *read_ecc, u8 *calc_ecc) |
| 151 | { |
| 152 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); |
| 153 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); |
| 154 | struct jz4780_bch_params params; |
| 155 | |
| 156 | params.size = nand->chip.ecc.size; |
| 157 | params.bytes = nand->chip.ecc.bytes; |
| 158 | params.strength = nand->chip.ecc.strength; |
| 159 | |
| 160 | return jz4780_bch_correct(nfc->bch, ¶ms, dat, read_ecc); |
| 161 | } |
| 162 | |
| 163 | static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *dev) |
| 164 | { |
| 165 | struct nand_chip *chip = &nand->chip; |
| 166 | struct mtd_info *mtd = nand_to_mtd(chip); |
| 167 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller); |
| 168 | struct nand_ecclayout *layout = &nand->ecclayout; |
| 169 | u32 start, i; |
| 170 | |
| 171 | chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) * |
| 172 | (chip->ecc.strength / 8); |
| 173 | |
| 174 | if (nfc->bch && chip->ecc.mode == NAND_ECC_HW) { |
| 175 | chip->ecc.hwctl = jz4780_nand_ecc_hwctl; |
| 176 | chip->ecc.calculate = jz4780_nand_ecc_calculate; |
| 177 | chip->ecc.correct = jz4780_nand_ecc_correct; |
| 178 | } else if (!nfc->bch && chip->ecc.mode == NAND_ECC_HW) { |
| 179 | dev_err(dev, "HW BCH selected, but BCH controller not found\n"); |
| 180 | return -ENODEV; |
| 181 | } |
| 182 | |
| 183 | if (chip->ecc.mode == NAND_ECC_HW_SYNDROME) { |
| 184 | dev_err(dev, "ECC HW syndrome not supported\n"); |
| 185 | return -EINVAL; |
| 186 | } |
| 187 | |
| 188 | if (chip->ecc.mode != NAND_ECC_NONE) |
| 189 | dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n", |
| 190 | (nfc->bch) ? "hardware BCH" : "software ECC", |
| 191 | chip->ecc.strength, chip->ecc.size, chip->ecc.bytes); |
| 192 | else |
| 193 | dev_info(dev, "not using ECC\n"); |
| 194 | |
| 195 | /* The NAND core will generate the ECC layout. */ |
| 196 | if (chip->ecc.mode == NAND_ECC_SOFT || chip->ecc.mode == NAND_ECC_SOFT_BCH) |
| 197 | return 0; |
| 198 | |
| 199 | /* Generate ECC layout. ECC codes are right aligned in the OOB area. */ |
| 200 | layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes; |
| 201 | |
| 202 | if (layout->eccbytes > mtd->oobsize - 2) { |
| 203 | dev_err(dev, |
| 204 | "invalid ECC config: required %d ECC bytes, but only %d are available", |
| 205 | layout->eccbytes, mtd->oobsize - 2); |
| 206 | return -EINVAL; |
| 207 | } |
| 208 | |
| 209 | start = mtd->oobsize - layout->eccbytes; |
| 210 | for (i = 0; i < layout->eccbytes; i++) |
| 211 | layout->eccpos[i] = start + i; |
| 212 | |
| 213 | layout->oobfree[0].offset = 2; |
| 214 | layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2; |
| 215 | |
| 216 | chip->ecc.layout = layout; |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static int jz4780_nand_init_chip(struct platform_device *pdev, |
| 221 | struct jz4780_nand_controller *nfc, |
| 222 | struct device_node *np, |
| 223 | unsigned int chipnr) |
| 224 | { |
| 225 | struct device *dev = &pdev->dev; |
| 226 | struct jz4780_nand_chip *nand; |
| 227 | struct jz4780_nand_cs *cs; |
| 228 | struct resource *res; |
| 229 | struct nand_chip *chip; |
| 230 | struct mtd_info *mtd; |
| 231 | const __be32 *reg; |
| 232 | int ret = 0; |
| 233 | |
| 234 | cs = &nfc->cs[chipnr]; |
| 235 | |
| 236 | reg = of_get_property(np, "reg", NULL); |
| 237 | if (!reg) |
| 238 | return -EINVAL; |
| 239 | |
| 240 | cs->bank = be32_to_cpu(*reg); |
| 241 | |
| 242 | jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND); |
| 243 | |
| 244 | res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr); |
| 245 | cs->base = devm_ioremap_resource(dev, res); |
| 246 | if (IS_ERR(cs->base)) |
| 247 | return PTR_ERR(cs->base); |
| 248 | |
| 249 | nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL); |
| 250 | if (!nand) |
| 251 | return -ENOMEM; |
| 252 | |
| 253 | nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN); |
| 254 | |
| 255 | if (IS_ERR(nand->busy_gpio)) { |
| 256 | ret = PTR_ERR(nand->busy_gpio); |
| 257 | dev_err(dev, "failed to request busy GPIO: %d\n", ret); |
| 258 | return ret; |
| 259 | } else if (nand->busy_gpio) { |
| 260 | nand->chip.dev_ready = jz4780_nand_dev_ready; |
| 261 | } |
| 262 | |
| 263 | nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW); |
| 264 | |
| 265 | if (IS_ERR(nand->wp_gpio)) { |
| 266 | ret = PTR_ERR(nand->wp_gpio); |
| 267 | dev_err(dev, "failed to request WP GPIO: %d\n", ret); |
| 268 | return ret; |
| 269 | } |
| 270 | |
| 271 | chip = &nand->chip; |
| 272 | mtd = nand_to_mtd(chip); |
Alex Smith | ae02ab0 | 2016-01-04 12:34:43 +0000 | [diff] [blame] | 273 | mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), |
| 274 | cs->bank); |
| 275 | if (!mtd->name) |
| 276 | return -ENOMEM; |
| 277 | mtd->dev.parent = dev; |
| 278 | |
| 279 | chip->IO_ADDR_R = cs->base + OFFSET_DATA; |
| 280 | chip->IO_ADDR_W = cs->base + OFFSET_DATA; |
| 281 | chip->chip_delay = RB_DELAY_US; |
| 282 | chip->options = NAND_NO_SUBPAGE_WRITE; |
| 283 | chip->select_chip = jz4780_nand_select_chip; |
| 284 | chip->cmd_ctrl = jz4780_nand_cmd_ctrl; |
| 285 | chip->ecc.mode = NAND_ECC_HW; |
| 286 | chip->controller = &nfc->controller; |
| 287 | nand_set_flash_node(chip, np); |
| 288 | |
| 289 | ret = nand_scan_ident(mtd, 1, NULL); |
| 290 | if (ret) |
| 291 | return ret; |
| 292 | |
| 293 | ret = jz4780_nand_init_ecc(nand, dev); |
| 294 | if (ret) |
| 295 | return ret; |
| 296 | |
| 297 | ret = nand_scan_tail(mtd); |
| 298 | if (ret) |
| 299 | return ret; |
| 300 | |
| 301 | ret = mtd_device_register(mtd, NULL, 0); |
| 302 | if (ret) { |
| 303 | nand_release(mtd); |
| 304 | return ret; |
| 305 | } |
| 306 | |
| 307 | list_add_tail(&nand->chip_list, &nfc->chips); |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc) |
| 313 | { |
| 314 | struct jz4780_nand_chip *chip; |
| 315 | |
| 316 | while (!list_empty(&nfc->chips)) { |
| 317 | chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list); |
| 318 | nand_release(nand_to_mtd(&chip->chip)); |
| 319 | list_del(&chip->chip_list); |
| 320 | } |
| 321 | } |
| 322 | |
| 323 | static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc, |
| 324 | struct platform_device *pdev) |
| 325 | { |
| 326 | struct device *dev = &pdev->dev; |
| 327 | struct device_node *np; |
| 328 | int i = 0; |
| 329 | int ret; |
| 330 | int num_chips = of_get_child_count(dev->of_node); |
| 331 | |
| 332 | if (num_chips > nfc->num_banks) { |
| 333 | dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks); |
| 334 | return -EINVAL; |
| 335 | } |
| 336 | |
| 337 | for_each_child_of_node(dev->of_node, np) { |
| 338 | ret = jz4780_nand_init_chip(pdev, nfc, np, i); |
| 339 | if (ret) { |
| 340 | jz4780_nand_cleanup_chips(nfc); |
| 341 | return ret; |
| 342 | } |
| 343 | |
| 344 | i++; |
| 345 | } |
| 346 | |
| 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | static int jz4780_nand_probe(struct platform_device *pdev) |
| 351 | { |
| 352 | struct device *dev = &pdev->dev; |
| 353 | unsigned int num_banks; |
| 354 | struct jz4780_nand_controller *nfc; |
| 355 | int ret; |
| 356 | |
| 357 | num_banks = jz4780_nemc_num_banks(dev); |
| 358 | if (num_banks == 0) { |
| 359 | dev_err(dev, "no banks found\n"); |
| 360 | return -ENODEV; |
| 361 | } |
| 362 | |
| 363 | nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL); |
| 364 | if (!nfc) |
| 365 | return -ENOMEM; |
| 366 | |
| 367 | /* |
| 368 | * Check for BCH HW before we call nand_scan_ident, to prevent us from |
| 369 | * having to call it again if the BCH driver returns -EPROBE_DEFER. |
| 370 | */ |
| 371 | nfc->bch = of_jz4780_bch_get(dev->of_node); |
| 372 | if (IS_ERR(nfc->bch)) |
| 373 | return PTR_ERR(nfc->bch); |
| 374 | |
| 375 | nfc->dev = dev; |
| 376 | nfc->num_banks = num_banks; |
| 377 | |
| 378 | spin_lock_init(&nfc->controller.lock); |
| 379 | INIT_LIST_HEAD(&nfc->chips); |
| 380 | init_waitqueue_head(&nfc->controller.wq); |
| 381 | |
| 382 | ret = jz4780_nand_init_chips(nfc, pdev); |
| 383 | if (ret) { |
| 384 | if (nfc->bch) |
| 385 | jz4780_bch_release(nfc->bch); |
| 386 | return ret; |
| 387 | } |
| 388 | |
| 389 | platform_set_drvdata(pdev, nfc); |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | static int jz4780_nand_remove(struct platform_device *pdev) |
| 394 | { |
| 395 | struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev); |
| 396 | |
| 397 | if (nfc->bch) |
| 398 | jz4780_bch_release(nfc->bch); |
| 399 | |
| 400 | jz4780_nand_cleanup_chips(nfc); |
| 401 | |
| 402 | return 0; |
| 403 | } |
| 404 | |
| 405 | static const struct of_device_id jz4780_nand_dt_match[] = { |
| 406 | { .compatible = "ingenic,jz4780-nand" }, |
| 407 | {}, |
| 408 | }; |
| 409 | MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match); |
| 410 | |
| 411 | static struct platform_driver jz4780_nand_driver = { |
| 412 | .probe = jz4780_nand_probe, |
| 413 | .remove = jz4780_nand_remove, |
| 414 | .driver = { |
| 415 | .name = DRV_NAME, |
| 416 | .of_match_table = of_match_ptr(jz4780_nand_dt_match), |
| 417 | }, |
| 418 | }; |
| 419 | module_platform_driver(jz4780_nand_driver); |
| 420 | |
| 421 | MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); |
| 422 | MODULE_AUTHOR("Harvey Hunt <harvey.hunt@imgtec.com>"); |
| 423 | MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver"); |
| 424 | MODULE_LICENSE("GPL v2"); |