Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | /dts-v1/; |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 13 | #include "imx27.dtsi" |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 14 | |
| 15 | / { |
| 16 | model = "Phytec pcm038"; |
| 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; |
| 18 | |
| 19 | memory { |
Alexander Shiyan | 999f681 | 2013-06-23 10:54:49 +0400 | [diff] [blame] | 20 | reg = <0xa0000000 0x08000000>; |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 21 | }; |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 22 | }; |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 23 | |
Alexander Shiyan | a919c69 | 2013-08-10 12:51:51 +0400 | [diff] [blame] | 24 | &audmux { |
| 25 | status = "okay"; |
| 26 | |
| 27 | /* SSI0 <=> PINS_4 (MC13783 Audio) */ |
| 28 | ssi0 { |
| 29 | fsl,audmux-port = <0>; |
| 30 | fsl,port-config = <0xcb205000>; |
| 31 | }; |
| 32 | |
| 33 | pins4 { |
| 34 | fsl,audmux-port = <2>; |
| 35 | fsl,port-config = <0x00001000>; |
| 36 | }; |
| 37 | }; |
| 38 | |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 39 | &cspi1 { |
| 40 | fsl,spi-num-chipselects = <1>; |
| 41 | cs-gpios = <&gpio4 28 0>; |
| 42 | status = "okay"; |
| 43 | |
| 44 | pmic: mc13783@0 { |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <0>; |
| 47 | compatible = "fsl,mc13783"; |
| 48 | spi-max-frequency = <20000000>; |
| 49 | reg = <0>; |
| 50 | interrupt-parent = <&gpio2>; |
| 51 | interrupts = <23 0x4>; |
| 52 | fsl,mc13xxx-uses-adc; |
| 53 | fsl,mc13xxx-uses-rtc; |
| 54 | |
| 55 | regulators { |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 56 | /* SW1A and SW1B joined operation */ |
| 57 | sw1_reg: sw1a { |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 58 | regulator-min-microvolt = <1200000>; |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 59 | regulator-max-microvolt = <1520000>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 60 | regulator-always-on; |
| 61 | regulator-boot-on; |
| 62 | }; |
| 63 | |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 64 | /* SW2A and SW2B joined operation */ |
| 65 | sw2_reg: sw2a { |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 66 | regulator-min-microvolt = <1800000>; |
| 67 | regulator-max-microvolt = <1800000>; |
| 68 | regulator-always-on; |
| 69 | regulator-boot-on; |
| 70 | }; |
| 71 | |
| 72 | sw3_reg: sw3 { |
| 73 | regulator-min-microvolt = <5000000>; |
| 74 | regulator-max-microvolt = <5000000>; |
| 75 | regulator-always-on; |
| 76 | regulator-boot-on; |
| 77 | }; |
| 78 | |
| 79 | vaudio_reg: vaudio { |
| 80 | regulator-always-on; |
| 81 | regulator-boot-on; |
| 82 | }; |
| 83 | |
| 84 | violo_reg: violo { |
| 85 | regulator-min-microvolt = <1800000>; |
| 86 | regulator-max-microvolt = <1800000>; |
| 87 | regulator-always-on; |
| 88 | regulator-boot-on; |
| 89 | }; |
| 90 | |
| 91 | viohi_reg: viohi { |
| 92 | regulator-always-on; |
| 93 | regulator-boot-on; |
| 94 | }; |
| 95 | |
| 96 | vgen_reg: vgen { |
| 97 | regulator-min-microvolt = <1500000>; |
| 98 | regulator-max-microvolt = <1500000>; |
| 99 | regulator-always-on; |
| 100 | regulator-boot-on; |
| 101 | }; |
| 102 | |
| 103 | vcam_reg: vcam { |
| 104 | regulator-min-microvolt = <2800000>; |
| 105 | regulator-max-microvolt = <2800000>; |
| 106 | }; |
| 107 | |
| 108 | vrf1_reg: vrf1 { |
| 109 | regulator-min-microvolt = <2775000>; |
| 110 | regulator-max-microvolt = <2775000>; |
| 111 | regulator-always-on; |
| 112 | regulator-boot-on; |
| 113 | }; |
| 114 | |
| 115 | vrf2_reg: vrf2 { |
| 116 | regulator-min-microvolt = <2775000>; |
| 117 | regulator-max-microvolt = <2775000>; |
| 118 | regulator-always-on; |
| 119 | regulator-boot-on; |
| 120 | }; |
| 121 | |
| 122 | vmmc1_reg: vmmc1 { |
| 123 | regulator-min-microvolt = <1600000>; |
| 124 | regulator-max-microvolt = <3000000>; |
| 125 | }; |
| 126 | |
| 127 | gpo1_reg: gpo1 { }; |
| 128 | |
| 129 | pwgt1spi_reg: pwgt1spi { |
| 130 | regulator-always-on; |
| 131 | }; |
| 132 | }; |
| 133 | }; |
| 134 | }; |
| 135 | |
Alexander Shiyan | f0d8e3f | 2013-07-02 20:02:29 +0400 | [diff] [blame] | 136 | &fec { |
| 137 | phy-reset-gpios = <&gpio3 30 0>; |
| 138 | status = "okay"; |
| 139 | }; |
| 140 | |
| 141 | &i2c2 { |
| 142 | clock-frequency = <400000>; |
| 143 | status = "okay"; |
| 144 | |
| 145 | at24@52 { |
| 146 | compatible = "at,24c32"; |
| 147 | pagesize = <32>; |
| 148 | reg = <0x52>; |
| 149 | }; |
| 150 | |
| 151 | pcf8563@51 { |
| 152 | compatible = "nxp,pcf8563"; |
| 153 | reg = <0x51>; |
| 154 | }; |
| 155 | |
| 156 | lm75@4a { |
| 157 | compatible = "national,lm75"; |
| 158 | reg = <0x4a>; |
| 159 | }; |
| 160 | }; |
| 161 | |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 162 | &nfc { |
| 163 | nand-bus-width = <8>; |
| 164 | nand-ecc-mode = "hw"; |
| 165 | status = "okay"; |
| 166 | }; |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 167 | |
Alexander Shiyan | f0d8e3f | 2013-07-02 20:02:29 +0400 | [diff] [blame] | 168 | &uart1 { |
| 169 | status = "okay"; |
| 170 | }; |
| 171 | |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 172 | &weim { |
| 173 | status = "okay"; |
| 174 | |
| 175 | nor: nor@c0000000 { |
| 176 | compatible = "cfi-flash"; |
| 177 | reg = <0 0x00000000 0x02000000>; |
| 178 | bank-width = <2>; |
| 179 | linux,mtd-name = "physmap-flash.0"; |
| 180 | fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; |
| 181 | #address-cells = <1>; |
| 182 | #size-cells = <1>; |
| 183 | }; |
Alexander Shiyan | cff2a713 | 2013-07-02 20:02:27 +0400 | [diff] [blame] | 184 | |
| 185 | sram: sram@c8000000 { |
| 186 | compatible = "mtd-ram"; |
| 187 | reg = <1 0x00000000 0x00800000>; |
| 188 | bank-width = <2>; |
| 189 | linux,mtd-name = "mtd-ram.0"; |
| 190 | fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; |
| 191 | #address-cells = <1>; |
| 192 | #size-cells = <1>; |
| 193 | }; |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 194 | }; |