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gerrit-public.fairphone.software / kernel / msm-4.9 / f12ecbe2ea3c01b61e93af815723939a27511abc / . / arch / arm / boot / dts / kirkwood-ts219-6282.dts
blob: 9efcd2dc79d3f74eaffb2b95bc9ff4fb9c7662db [file] [log] [blame]
Andrew Lunn9eb61f42012-05-12 14:57:59 +0200[diff] [blame]1/dts-v1/;
2
Ezequiel Garcia0ab61292013-07-26 10:18:02 -0300[diff] [blame]3#include "kirkwood.dtsi"
4#include "kirkwood-6282.dtsi"
5#include "kirkwood-ts219.dtsi"
Andrew Lunn9eb61f42012-05-12 14:57:59 +0200[diff] [blame]6
7/ {
Ezequiel Garcia54397d82013-07-26 10:18:05 -0300[diff] [blame]8 mbus {
9 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
10 pcie-controller {
11 status = "okay";
12
13 pcie@2,0 {
14 status = "okay";
15 };
16 };
17 };
18
Andrew Lunn1f6e46b2012-11-17 17:00:46 +0100[diff] [blame]19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
Thomas Petazzonia4936cf2013-05-24 11:44:56 +0200[diff] [blame]22 pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
Andrew Lunn1f6e46b2012-11-17 17:00:46 +0100[diff] [blame]23 pinctrl-names = "default";
24
25 pmx_ram_size: pmx-ram-size {
26 /* RAM: 0: 256 MB, 1: 512 MB */
27 marvell,pins = "mpp36";
28 marvell,function = "gpio";
29 };
30 pmx_reset_button: pmx-reset-button {
31 marvell,pins = "mpp37";
32 marvell,function = "gpio";
33 };
34 pmx_USB_copy_button: pmx-USB-copy-button {
35 marvell,pins = "mpp43";
36 marvell,function = "gpio";
37 };
38 pmx_board_id: pmx-board-id {
39 /* 0: TS-11x, 1: TS-21x */
40 marvell,pins = "mpp44";
41 marvell,function = "gpio";
42 };
43 };
44 };
45
Andrew Lunn9eb61f42012-05-12 14:57:59 +0200[diff] [blame]46 gpio_keys {
47 compatible = "gpio-keys";
48 #address-cells = <1>;
49 #size-cells = <0>;
Thomas Petazzonia4936cf2013-05-24 11:44:56 +0200[diff] [blame]50 pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
51 pinctrl-names = "default";
52
Andrew Lunn9eb61f42012-05-12 14:57:59 +0200[diff] [blame]53 button@1 {
54 label = "USB Copy";
55 linux,code = <133>;
56 gpios = <&gpio1 11 1>;
57 };
58 button@2 {
59 label = "Reset";
60 linux,code = <0x198>;
61 gpios = <&gpio1 5 1>;
62 };
63 };
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +0200[diff] [blame]64};
65
66&ethphy0 { reg = <0>; };