blob: 386d4287021534345dcfbed2f3e2f6d5079dcf0f [file] [log] [blame]
David Brown56e2d8a2011-08-04 02:01:02 -07001/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8660 SURF";
7 compatible = "qcom,msm8660-surf", "qcom,msm8660";
8 interrupt-parent = <&intc>;
9
Stephen Boyd84071162012-09-05 12:28:54 -070010 intc: interrupt-controller@2080000 {
David Brown56e2d8a2011-08-04 02:01:02 -070011 compatible = "qcom,msm-8660-qgic";
12 interrupt-controller;
David Brown2b7b9a72012-04-23 15:34:20 -070013 #interrupt-cells = <3>;
David Brown56e2d8a2011-08-04 02:01:02 -070014 reg = < 0x02080000 0x1000 >,
15 < 0x02081000 0x1000 >;
16 };
17
Stephen Boyd28ba4722013-05-20 17:50:37 -070018 timer@2000000 {
Stephen Boydeebdb0c2013-03-14 20:31:38 -070019 compatible = "qcom,scss-timer", "qcom,msm-timer";
20 interrupts = <1 0 0x301>,
21 <1 1 0x301>,
22 <1 2 0x301>;
23 reg = <0x02000000 0x100>;
24 clock-frequency = <27000000>,
25 <32768>;
Stephen Boyd84071162012-09-05 12:28:54 -070026 cpu-offset = <0x40000>;
27 };
28
Rohit Vaswani43f68442013-06-10 15:50:21 -070029 msmgpio: gpio@800000 {
30 compatible = "qcom,msm-gpio";
31 reg = <0x00800000 0x1000>;
32 gpio-controller;
33 #gpio-cells = <2>;
34 ngpio = <173>;
35 interrupts = <0 32 0x4>;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 };
39
Stephen Boyd28ba4722013-05-20 17:50:37 -070040 serial@19c40000 {
Stephen Boyd9dfe59f12013-08-28 13:32:41 -070041 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
David Brown56e2d8a2011-08-04 02:01:02 -070042 reg = <0x19c40000 0x1000>,
43 <0x19c00000 0x1000>;
David Brown2b7b9a72012-04-23 15:34:20 -070044 interrupts = <0 195 0x0>;
David Brown56e2d8a2011-08-04 02:01:02 -070045 };
David Brown97f00f72013-03-12 11:41:50 -070046
47 qcom,ssbi@500000 {
48 compatible = "qcom,ssbi";
49 reg = <0x500000 0x1000>;
50 qcom,controller-type = "pmic-arbiter";
51 };
David Brown56e2d8a2011-08-04 02:01:02 -070052};