blob: 90004081a50103532ddb652edad3668ba747db36 [file] [log] [blame]
Ben Skeggs2a259a32012-05-08 10:24:27 +10001#ifndef __NOUVEAU_ABI16_H__
2#define __NOUVEAU_ABI16_H__
3
4#define ABI16_IOCTL_ARGS \
5 struct drm_device *dev, void *data, struct drm_file *file_priv
Ben Skeggsebb945a2012-07-20 08:17:34 +10006
Ben Skeggs2a259a32012-05-08 10:24:27 +10007int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
8int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
9int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
10int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
11int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
12int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
13int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
14
Ben Skeggsebb945a2012-07-20 08:17:34 +100015struct nouveau_abi16_ntfy {
16 struct list_head head;
17 struct nouveau_mm_node *node;
18 u32 handle;
19};
20
21struct nouveau_abi16_chan {
22 struct list_head head;
23 struct nouveau_channel *chan;
24 struct list_head notifiers;
25 struct nouveau_bo *ntfy;
26 struct nouveau_vma ntfy_vma;
27 struct nouveau_mm heap;
28};
29
30struct nouveau_abi16 {
31 struct nouveau_object *client;
32 struct nouveau_object *device;
33 struct list_head channels;
34 u64 handles;
35};
36
37struct nouveau_drm;
38struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *, struct drm_device *);
39int nouveau_abi16_put(struct nouveau_abi16 *, int);
40void nouveau_abi16_fini(struct nouveau_abi16 *);
41u16 nouveau_abi16_swclass(struct nouveau_drm *);
42
43#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
44#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
45
Ben Skeggs2a259a32012-05-08 10:24:27 +100046struct drm_nouveau_channel_alloc {
47 uint32_t fb_ctxdma_handle;
48 uint32_t tt_ctxdma_handle;
49
50 int channel;
51 uint32_t pushbuf_domains;
52
53 /* Notifier memory */
54 uint32_t notifier_handle;
55
56 /* DRM-enforced subchannel assignments */
57 struct {
58 uint32_t handle;
59 uint32_t grclass;
60 } subchan[8];
61 uint32_t nr_subchan;
62};
63
64struct drm_nouveau_channel_free {
65 int channel;
66};
67
68struct drm_nouveau_grobj_alloc {
69 int channel;
70 uint32_t handle;
71 int class;
72};
73
74struct drm_nouveau_notifierobj_alloc {
75 uint32_t channel;
76 uint32_t handle;
77 uint32_t size;
78 uint32_t offset;
79};
80
81struct drm_nouveau_gpuobj_free {
82 int channel;
83 uint32_t handle;
84};
85
86#define NOUVEAU_GETPARAM_PCI_VENDOR 3
87#define NOUVEAU_GETPARAM_PCI_DEVICE 4
88#define NOUVEAU_GETPARAM_BUS_TYPE 5
89#define NOUVEAU_GETPARAM_FB_SIZE 8
90#define NOUVEAU_GETPARAM_AGP_SIZE 9
91#define NOUVEAU_GETPARAM_CHIPSET_ID 11
92#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
93#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
94#define NOUVEAU_GETPARAM_PTIMER_TIME 14
95#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
96#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
97struct drm_nouveau_getparam {
98 uint64_t param;
99 uint64_t value;
100};
101
102struct drm_nouveau_setparam {
103 uint64_t param;
104 uint64_t value;
105};
106
107#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
108#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
109#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
110#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
111#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
112#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
113#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
114
115#endif