Abylay Ospan | c184dcd | 2009-03-03 11:06:00 -0300 | [diff] [blame] | 1 | /* |
| 2 | * cimax2.c |
| 3 | * |
| 4 | * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card |
| 5 | * |
| 6 | * Copyright (C) 2009 NetUP Inc. |
| 7 | * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> |
| 8 | * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | */ |
| 25 | |
| 26 | #include "cx23885.h" |
| 27 | #include "dvb_ca_en50221.h" |
| 28 | /**** Bit definitions for MC417_RWD and MC417_OEN registers *** |
| 29 | bits 31-16 |
| 30 | +-----------+ |
| 31 | | Reserved | |
| 32 | +-----------+ |
| 33 | bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 |
| 34 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 35 | | WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# | |
| 36 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 37 | bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 |
| 38 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 39 | | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0| |
| 40 | +-------+-------+-------+-------+-------+-------+-------+-------+ |
| 41 | ***/ |
| 42 | /* MC417 */ |
| 43 | #define NETUP_DATA 0x000000ff |
| 44 | #define NETUP_WR 0x00008000 |
| 45 | #define NETUP_RD 0x00004000 |
| 46 | #define NETUP_ACK 0x00001000 |
| 47 | #define NETUP_ADHI 0x00000800 |
| 48 | #define NETUP_ADLO 0x00000400 |
| 49 | #define NETUP_CS1 0x00000200 |
| 50 | #define NETUP_CS0 0x00000100 |
| 51 | #define NETUP_EN_ALL 0x00001000 |
| 52 | #define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD) |
| 53 | #define NETUP_CI_CTL 0x04 |
| 54 | #define NETUP_CI_RD 1 |
| 55 | |
| 56 | |
| 57 | static unsigned int ci_dbg; |
| 58 | module_param(ci_dbg, int, 0644); |
| 59 | MODULE_PARM_DESC(ci_dbg, "Enable CI debugging"); |
| 60 | |
| 61 | #define ci_dbg_print(args...) \ |
| 62 | do { \ |
| 63 | if (ci_dbg) \ |
| 64 | printk(KERN_DEBUG args); \ |
| 65 | } while (0) |
| 66 | |
| 67 | /* stores all private variables for communication with CI */ |
| 68 | struct netup_ci_state { |
| 69 | struct dvb_ca_en50221 ca; |
| 70 | struct mutex ca_mutex; |
| 71 | struct i2c_adapter *i2c_adap; |
| 72 | u8 ci_i2c_addr; |
| 73 | int status; |
| 74 | struct work_struct work; |
| 75 | void *priv; |
| 76 | }; |
| 77 | |
| 78 | struct mutex gpio_mutex;/* Two CiMax's uses same GPIO lines */ |
| 79 | |
| 80 | int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, |
| 81 | u8 *buf, int len) |
| 82 | { |
| 83 | int ret; |
| 84 | struct i2c_msg msg[] = { |
| 85 | { |
| 86 | .addr = addr, |
| 87 | .flags = 0, |
| 88 | .buf = ®, |
| 89 | .len = 1 |
| 90 | }, { |
| 91 | .addr = addr, |
| 92 | .flags = I2C_M_RD, |
| 93 | .buf = buf, |
| 94 | .len = len |
| 95 | } |
| 96 | }; |
| 97 | |
| 98 | ret = i2c_transfer(i2c_adap, msg, 2); |
| 99 | |
| 100 | if (ret != 2) { |
| 101 | ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n", |
| 102 | __func__, reg, ret); |
| 103 | |
| 104 | return -1; |
| 105 | } |
| 106 | |
| 107 | ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n", |
| 108 | __func__, addr, reg, buf[0]); |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, |
| 114 | u8 *buf, int len) |
| 115 | { |
| 116 | int ret; |
| 117 | u8 buffer[len + 1]; |
| 118 | |
| 119 | struct i2c_msg msg = { |
| 120 | .addr = addr, |
| 121 | .flags = 0, |
| 122 | .buf = &buffer[0], |
| 123 | .len = len + 1 |
| 124 | }; |
| 125 | |
| 126 | buffer[0] = reg; |
| 127 | memcpy(&buffer[1], buf, len); |
| 128 | |
| 129 | ret = i2c_transfer(i2c_adap, &msg, 1); |
| 130 | |
| 131 | if (ret != 1) { |
| 132 | ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n", |
| 133 | __func__, reg, ret); |
| 134 | return -1; |
| 135 | } |
| 136 | |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | int netup_ci_get_mem(struct cx23885_dev *dev) |
| 141 | { |
| 142 | int mem; |
| 143 | unsigned long timeout = jiffies + msecs_to_jiffies(1); |
| 144 | |
| 145 | for (;;) { |
| 146 | mem = cx_read(MC417_RWD); |
| 147 | if ((mem & NETUP_ACK) == 0) |
| 148 | break; |
| 149 | if (time_after(jiffies, timeout)) |
| 150 | break; |
| 151 | udelay(1); |
| 152 | } |
| 153 | |
| 154 | cx_set(MC417_RWD, NETUP_CTRL_OFF); |
| 155 | |
| 156 | return mem & 0xff; |
| 157 | } |
| 158 | |
| 159 | int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, |
Abylay Ospan | f1bee69 | 2009-03-17 18:13:52 -0300 | [diff] [blame^] | 160 | u8 flag, u8 read, int addr, u8 data) |
Abylay Ospan | c184dcd | 2009-03-03 11:06:00 -0300 | [diff] [blame] | 161 | { |
| 162 | struct netup_ci_state *state = en50221->data; |
| 163 | struct cx23885_tsport *port = state->priv; |
| 164 | struct cx23885_dev *dev = port->dev; |
| 165 | |
| 166 | u8 store; |
| 167 | int mem; |
| 168 | int ret; |
| 169 | |
| 170 | if (0 != slot) |
| 171 | return -EINVAL; |
| 172 | |
| 173 | ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 174 | 0, &store, 1); |
| 175 | if (ret != 0) |
| 176 | return ret; |
| 177 | |
| 178 | store &= ~0x0c; |
| 179 | store |= flag; |
| 180 | |
| 181 | ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 182 | 0, &store, 1); |
| 183 | if (ret != 0) |
| 184 | return ret; |
| 185 | |
| 186 | mutex_lock(&gpio_mutex); |
| 187 | |
| 188 | /* write addr */ |
| 189 | cx_write(MC417_OEN, NETUP_EN_ALL); |
| 190 | cx_write(MC417_RWD, NETUP_CTRL_OFF | |
| 191 | NETUP_ADLO | (0xff & addr)); |
| 192 | cx_clear(MC417_RWD, NETUP_ADLO); |
| 193 | cx_write(MC417_RWD, NETUP_CTRL_OFF | |
| 194 | NETUP_ADHI | (0xff & (addr >> 8))); |
| 195 | cx_clear(MC417_RWD, NETUP_ADHI); |
| 196 | |
| 197 | if (read) /* data in */ |
| 198 | cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA); |
| 199 | else /* data out */ |
| 200 | cx_write(MC417_RWD, NETUP_CTRL_OFF | data); |
| 201 | |
| 202 | /* choose chip */ |
| 203 | cx_clear(MC417_RWD, |
| 204 | (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1); |
| 205 | /* read/write */ |
| 206 | cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR); |
| 207 | mem = netup_ci_get_mem(dev); |
| 208 | |
| 209 | mutex_unlock(&gpio_mutex); |
| 210 | |
| 211 | if (!read) |
| 212 | if (mem < 0) |
| 213 | return -EREMOTEIO; |
| 214 | |
| 215 | ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__, |
| 216 | (read) ? "read" : "write", addr, |
| 217 | (flag == NETUP_CI_CTL) ? "ctl" : "mem", |
| 218 | (read) ? mem : data); |
| 219 | |
| 220 | if (read) |
| 221 | return mem; |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221, |
| 227 | int slot, int addr) |
| 228 | { |
| 229 | return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0); |
| 230 | } |
| 231 | |
| 232 | int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221, |
| 233 | int slot, int addr, u8 data) |
| 234 | { |
| 235 | return netup_ci_op_cam(en50221, slot, 0, 0, addr, data); |
| 236 | } |
| 237 | |
| 238 | int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, u8 addr) |
| 239 | { |
| 240 | return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, |
| 241 | NETUP_CI_RD, addr, 0); |
| 242 | } |
| 243 | |
| 244 | int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, |
| 245 | u8 addr, u8 data) |
| 246 | { |
| 247 | return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data); |
| 248 | } |
| 249 | |
| 250 | int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot) |
| 251 | { |
| 252 | struct netup_ci_state *state = en50221->data; |
| 253 | u8 buf = 0x80; |
| 254 | int ret; |
| 255 | |
| 256 | if (0 != slot) |
| 257 | return -EINVAL; |
| 258 | |
| 259 | udelay(500); |
| 260 | ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 261 | 0, &buf, 1); |
| 262 | |
| 263 | if (ret != 0) |
| 264 | return ret; |
| 265 | |
| 266 | udelay(500); |
| 267 | |
| 268 | buf = 0x00; |
| 269 | ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 270 | 0, &buf, 1); |
| 271 | |
| 272 | msleep(1000); |
| 273 | dvb_ca_en50221_camready_irq(&state->ca, 0); |
| 274 | |
| 275 | return 0; |
| 276 | |
| 277 | } |
| 278 | |
| 279 | int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot) |
| 280 | { |
| 281 | /* not implemented */ |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot) |
| 286 | { |
| 287 | struct netup_ci_state *state = en50221->data; |
| 288 | u8 buf = 0x60; |
| 289 | |
| 290 | if (0 != slot) |
| 291 | return -EINVAL; |
| 292 | |
| 293 | return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 294 | 0, &buf, 1); |
| 295 | } |
| 296 | |
| 297 | /* work handler */ |
| 298 | static void netup_read_ci_status(struct work_struct *work) |
| 299 | { |
| 300 | struct netup_ci_state *state = |
| 301 | container_of(work, struct netup_ci_state, work); |
| 302 | u8 buf[33]; |
| 303 | int ret; |
| 304 | |
| 305 | ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 306 | 0, &buf[0], 33); |
| 307 | |
| 308 | if (ret != 0) |
| 309 | return; |
| 310 | |
| 311 | ci_dbg_print("%s: Slot Status Addr=[0x%04x], Reg=[0x%02x], data=%02x, " |
| 312 | "TS config = %02x\n", __func__, state->ci_i2c_addr, 0, buf[0], |
| 313 | buf[32]); |
| 314 | |
| 315 | if (buf[0] && 1) |
| 316 | state->status = DVB_CA_EN50221_POLL_CAM_PRESENT | |
| 317 | DVB_CA_EN50221_POLL_CAM_READY; |
| 318 | else |
| 319 | state->status = 0; |
| 320 | } |
| 321 | |
| 322 | /* CI irq handler */ |
| 323 | int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status) |
| 324 | { |
| 325 | struct cx23885_tsport *port = NULL; |
| 326 | struct netup_ci_state *state = NULL; |
| 327 | |
| 328 | if (pci_status & PCI_MSK_GPIO0) |
| 329 | port = &dev->ts1; |
| 330 | else if (pci_status & PCI_MSK_GPIO1) |
| 331 | port = &dev->ts2; |
| 332 | else /* who calls ? */ |
| 333 | return 0; |
| 334 | |
| 335 | state = port->port_priv; |
| 336 | |
| 337 | schedule_work(&state->work); |
| 338 | |
| 339 | return 1; |
| 340 | } |
| 341 | |
| 342 | int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221, int slot, int open) |
| 343 | { |
| 344 | struct netup_ci_state *state = en50221->data; |
| 345 | |
| 346 | if (0 != slot) |
| 347 | return -EINVAL; |
| 348 | |
| 349 | return state->status; |
| 350 | } |
| 351 | |
| 352 | int netup_ci_init(struct cx23885_tsport *port) |
| 353 | { |
| 354 | struct netup_ci_state *state; |
| 355 | u8 cimax_init[34] = { |
| 356 | 0x00, /* module A control*/ |
| 357 | 0x00, /* auto select mask high A */ |
| 358 | 0x00, /* auto select mask low A */ |
| 359 | 0x00, /* auto select pattern high A */ |
| 360 | 0x00, /* auto select pattern low A */ |
| 361 | 0x44, /* memory access time A */ |
| 362 | 0x00, /* invert input A */ |
| 363 | 0x00, /* RFU */ |
| 364 | 0x00, /* RFU */ |
| 365 | 0x00, /* module B control*/ |
| 366 | 0x00, /* auto select mask high B */ |
| 367 | 0x00, /* auto select mask low B */ |
| 368 | 0x00, /* auto select pattern high B */ |
| 369 | 0x00, /* auto select pattern low B */ |
| 370 | 0x44, /* memory access time B */ |
| 371 | 0x00, /* invert input B */ |
| 372 | 0x00, /* RFU */ |
| 373 | 0x00, /* RFU */ |
| 374 | 0x00, /* auto select mask high Ext */ |
| 375 | 0x00, /* auto select mask low Ext */ |
| 376 | 0x00, /* auto select pattern high Ext */ |
| 377 | 0x00, /* auto select pattern low Ext */ |
| 378 | 0x00, /* RFU */ |
| 379 | 0x02, /* destination - module A */ |
| 380 | 0x01, /* power on (use it like store place) */ |
| 381 | 0x00, /* RFU */ |
| 382 | 0x00, /* int status read only */ |
| 383 | 0x01, /* all int unmasked */ |
| 384 | 0x04, /* int config */ |
| 385 | 0x00, /* USCG1 */ |
| 386 | 0x04, /* ack active low */ |
| 387 | 0x00, /* LOCK = 0 */ |
| 388 | 0x33, /* serial mode, rising in, rising out, MSB first*/ |
| 389 | 0x31, /* syncronization */ |
| 390 | }; |
| 391 | int ret; |
| 392 | |
| 393 | ci_dbg_print("%s\n", __func__); |
| 394 | state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL); |
| 395 | if (!state) { |
| 396 | ci_dbg_print("%s: Unable create CI structure!\n", __func__); |
| 397 | ret = -ENOMEM; |
| 398 | goto err; |
| 399 | } |
| 400 | |
| 401 | port->port_priv = state; |
| 402 | |
| 403 | switch (port->nr) { |
| 404 | case 1: |
| 405 | state->ci_i2c_addr = 0x40; |
| 406 | mutex_init(&gpio_mutex); |
| 407 | break; |
| 408 | case 2: |
| 409 | state->ci_i2c_addr = 0x41; |
| 410 | break; |
| 411 | } |
| 412 | |
| 413 | state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap; |
| 414 | state->ca.owner = THIS_MODULE; |
| 415 | state->ca.read_attribute_mem = netup_ci_read_attribute_mem; |
| 416 | state->ca.write_attribute_mem = netup_ci_write_attribute_mem; |
| 417 | state->ca.read_cam_control = netup_ci_read_cam_ctl; |
| 418 | state->ca.write_cam_control = netup_ci_write_cam_ctl; |
| 419 | state->ca.slot_reset = netup_ci_slot_reset; |
| 420 | state->ca.slot_shutdown = netup_ci_slot_shutdown; |
| 421 | state->ca.slot_ts_enable = netup_ci_slot_ts_ctl; |
| 422 | state->ca.poll_slot_status = netup_poll_ci_slot_status; |
| 423 | state->ca.data = state; |
| 424 | state->priv = port; |
| 425 | |
| 426 | ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 427 | 0, &cimax_init[0], 34); |
| 428 | /* lock registers */ |
| 429 | ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 430 | 0x1f, &cimax_init[0x18], 1); |
| 431 | /* power on slots */ |
| 432 | ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, |
| 433 | 0x18, &cimax_init[0x18], 1); |
| 434 | |
| 435 | if (0 != ret) |
| 436 | goto err; |
| 437 | |
| 438 | ret = dvb_ca_en50221_init(&port->frontends.adapter, |
| 439 | &state->ca, |
| 440 | /* flags */ 0, |
| 441 | /* n_slots */ 1); |
| 442 | if (0 != ret) |
| 443 | goto err; |
| 444 | |
| 445 | INIT_WORK(&state->work, netup_read_ci_status); |
| 446 | |
| 447 | ci_dbg_print("%s: CI initialized!\n", __func__); |
| 448 | |
| 449 | return 0; |
| 450 | err: |
| 451 | ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret); |
| 452 | kfree(state); |
| 453 | return ret; |
| 454 | } |
| 455 | |
| 456 | void netup_ci_exit(struct cx23885_tsport *port) |
| 457 | { |
| 458 | struct netup_ci_state *state; |
| 459 | |
| 460 | if (NULL == port) |
| 461 | return; |
| 462 | |
| 463 | state = (struct netup_ci_state *)port->port_priv; |
| 464 | if (NULL == state) |
| 465 | return; |
| 466 | |
| 467 | if (NULL == state->ca.data) |
| 468 | return; |
| 469 | |
| 470 | dvb_ca_en50221_release(&state->ca); |
| 471 | kfree(state); |
| 472 | } |