Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-i386/processor.h |
| 3 | * |
| 4 | * Copyright (C) 1994 Linus Torvalds |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_I386_PROCESSOR_H |
| 8 | #define __ASM_I386_PROCESSOR_H |
| 9 | |
| 10 | #include <asm/vm86.h> |
| 11 | #include <asm/math_emu.h> |
| 12 | #include <asm/segment.h> |
| 13 | #include <asm/page.h> |
| 14 | #include <asm/types.h> |
| 15 | #include <asm/sigcontext.h> |
| 16 | #include <asm/cpufeature.h> |
| 17 | #include <asm/msr.h> |
| 18 | #include <asm/system.h> |
| 19 | #include <linux/cache.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/threads.h> |
| 21 | #include <asm/percpu.h> |
Siddha, Suresh B | 1e9f28f | 2006-03-27 01:15:22 -0800 | [diff] [blame] | 22 | #include <linux/cpumask.h> |
Rusty Russell | d7cd561 | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 23 | #include <linux/init.h> |
Andi Kleen | b4531e8 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 24 | #include <asm/processor-flags.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
| 26 | /* flag for disabling the tsc */ |
| 27 | extern int tsc_disable; |
| 28 | |
| 29 | struct desc_struct { |
| 30 | unsigned long a,b; |
| 31 | }; |
| 32 | |
| 33 | #define desc_empty(desc) \ |
Zachary Amsden | 12aaa08 | 2005-08-16 12:05:09 -0700 | [diff] [blame] | 34 | (!((desc)->a | (desc)->b)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
| 36 | #define desc_equal(desc1, desc2) \ |
| 37 | (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) |
| 38 | /* |
| 39 | * Default implementation of macro that returns current |
| 40 | * instruction pointer ("program counter"). |
| 41 | */ |
| 42 | #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; }) |
| 43 | |
| 44 | /* |
| 45 | * CPU type and hardware bug flags. Kept separately for each CPU. |
| 46 | * Members of this structure are referenced in head.S, so think twice |
| 47 | * before touching them. [mj] |
| 48 | */ |
| 49 | |
| 50 | struct cpuinfo_x86 { |
| 51 | __u8 x86; /* CPU family */ |
| 52 | __u8 x86_vendor; /* CPU vendor */ |
| 53 | __u8 x86_model; |
| 54 | __u8 x86_mask; |
| 55 | char wp_works_ok; /* It doesn't on 386's */ |
| 56 | char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */ |
| 57 | char hard_math; |
| 58 | char rfu; |
| 59 | int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */ |
| 60 | unsigned long x86_capability[NCAPINTS]; |
| 61 | char x86_vendor_id[16]; |
| 62 | char x86_model_id[64]; |
| 63 | int x86_cache_size; /* in KB - valid for CPUS which support this |
| 64 | call */ |
| 65 | int x86_cache_alignment; /* In bytes */ |
Andi Kleen | 3f98bc4 | 2006-01-11 22:42:51 +0100 | [diff] [blame] | 66 | char fdiv_bug; |
| 67 | char f00f_bug; |
| 68 | char coma_bug; |
| 69 | char pad0; |
| 70 | int x86_power; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | unsigned long loops_per_jiffy; |
Siddha, Suresh B | 1e9f28f | 2006-03-27 01:15:22 -0800 | [diff] [blame] | 72 | #ifdef CONFIG_SMP |
| 73 | cpumask_t llc_shared_map; /* cpus sharing the last level cache */ |
| 74 | #endif |
Siddha, Suresh B | 94605ef | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 75 | unsigned char x86_max_cores; /* cpuid returned max cores value */ |
Siddha, Suresh B | 94605ef | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 76 | unsigned char apicid; |
Andi Kleen | 770d132 | 2006-12-07 02:14:05 +0100 | [diff] [blame] | 77 | unsigned short x86_clflush_size; |
Rohit Seth | 4b89aff | 2006-06-27 02:53:46 -0700 | [diff] [blame] | 78 | #ifdef CONFIG_SMP |
| 79 | unsigned char booted_cores; /* number of cores as seen by OS */ |
| 80 | __u8 phys_proc_id; /* Physical processor id. */ |
| 81 | __u8 cpu_core_id; /* Core id */ |
| 82 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); |
| 84 | |
| 85 | #define X86_VENDOR_INTEL 0 |
| 86 | #define X86_VENDOR_CYRIX 1 |
| 87 | #define X86_VENDOR_AMD 2 |
| 88 | #define X86_VENDOR_UMC 3 |
| 89 | #define X86_VENDOR_NEXGEN 4 |
| 90 | #define X86_VENDOR_CENTAUR 5 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | #define X86_VENDOR_TRANSMETA 7 |
| 92 | #define X86_VENDOR_NSC 8 |
| 93 | #define X86_VENDOR_NUM 9 |
| 94 | #define X86_VENDOR_UNKNOWN 0xff |
| 95 | |
| 96 | /* |
| 97 | * capabilities of CPUs |
| 98 | */ |
| 99 | |
| 100 | extern struct cpuinfo_x86 boot_cpu_data; |
| 101 | extern struct cpuinfo_x86 new_cpu_data; |
| 102 | extern struct tss_struct doublefault_tss; |
| 103 | DECLARE_PER_CPU(struct tss_struct, init_tss); |
| 104 | |
| 105 | #ifdef CONFIG_SMP |
| 106 | extern struct cpuinfo_x86 cpu_data[]; |
| 107 | #define current_cpu_data cpu_data[smp_processor_id()] |
| 108 | #else |
| 109 | #define cpu_data (&boot_cpu_data) |
| 110 | #define current_cpu_data boot_cpu_data |
| 111 | #endif |
| 112 | |
Mike Travis | b627847 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 113 | /* |
| 114 | * the following now lives in the per cpu area: |
| 115 | * extern int cpu_llc_id[NR_CPUS]; |
| 116 | */ |
| 117 | DECLARE_PER_CPU(u8, cpu_llc_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | extern char ignore_fpu_irq; |
| 119 | |
Rusty Russell | d7cd561 | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 120 | void __init cpu_detect(struct cpuinfo_x86 *c); |
| 121 | |
Jeremy Fitzhardinge | a6c4e07 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 122 | extern void identify_boot_cpu(void); |
| 123 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | extern void print_cpu_info(struct cpuinfo_x86 *); |
Venki Pallipadi | 1d67953 | 2007-07-11 12:18:32 -0700 | [diff] [blame] | 125 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 127 | extern unsigned short num_cache_leaves; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | |
| 129 | #ifdef CONFIG_X86_HT |
| 130 | extern void detect_ht(struct cpuinfo_x86 *c); |
| 131 | #else |
| 132 | static inline void detect_ht(struct cpuinfo_x86 *c) {} |
| 133 | #endif |
| 134 | |
Rusty Russell | 90a0a06 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 135 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
Rusty Russell | d3561b7 | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 136 | unsigned int *ecx, unsigned int *edx) |
Rusty Russell | 9f09339 | 2006-09-25 23:32:24 -0700 | [diff] [blame] | 137 | { |
| 138 | /* ecx is often an input as well as an output. */ |
| 139 | __asm__("cpuid" |
| 140 | : "=a" (*eax), |
| 141 | "=b" (*ebx), |
| 142 | "=c" (*ecx), |
| 143 | "=d" (*edx) |
| 144 | : "0" (*eax), "2" (*ecx)); |
| 145 | } |
| 146 | |
Zachary Amsden | 4bb0d3e | 2005-09-03 15:56:36 -0700 | [diff] [blame] | 147 | #define load_cr3(pgdir) write_cr3(__pa(pgdir)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | |
| 149 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | * Save the cr4 feature set we're using (ie |
| 151 | * Pentium 4MB enable and PPro Global page |
| 152 | * enable), so that any CPU's that boot up |
| 153 | * after us can get the correct flags. |
| 154 | */ |
| 155 | extern unsigned long mmu_cr4_features; |
| 156 | |
| 157 | static inline void set_in_cr4 (unsigned long mask) |
| 158 | { |
Zachary Amsden | 4bb0d3e | 2005-09-03 15:56:36 -0700 | [diff] [blame] | 159 | unsigned cr4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | mmu_cr4_features |= mask; |
Zachary Amsden | 4bb0d3e | 2005-09-03 15:56:36 -0700 | [diff] [blame] | 161 | cr4 = read_cr4(); |
| 162 | cr4 |= mask; |
| 163 | write_cr4(cr4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | static inline void clear_in_cr4 (unsigned long mask) |
| 167 | { |
Zachary Amsden | 4bb0d3e | 2005-09-03 15:56:36 -0700 | [diff] [blame] | 168 | unsigned cr4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | mmu_cr4_features &= ~mask; |
Zachary Amsden | 4bb0d3e | 2005-09-03 15:56:36 -0700 | [diff] [blame] | 170 | cr4 = read_cr4(); |
| 171 | cr4 &= ~mask; |
| 172 | write_cr4(cr4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | } |
| 174 | |
Andi Kleen | 487472b | 2006-01-11 22:45:27 +0100 | [diff] [blame] | 175 | /* Stop speculative execution */ |
| 176 | static inline void sync_core(void) |
Zachary Amsden | 245067d | 2005-09-03 15:56:37 -0700 | [diff] [blame] | 177 | { |
Andi Kleen | 487472b | 2006-01-11 22:45:27 +0100 | [diff] [blame] | 178 | int tmp; |
| 179 | asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory"); |
Zachary Amsden | 245067d | 2005-09-03 15:56:37 -0700 | [diff] [blame] | 180 | } |
| 181 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | static inline void __monitor(const void *eax, unsigned long ecx, |
| 183 | unsigned long edx) |
| 184 | { |
| 185 | /* "monitor %eax,%ecx,%edx;" */ |
| 186 | asm volatile( |
| 187 | ".byte 0x0f,0x01,0xc8;" |
| 188 | : :"a" (eax), "c" (ecx), "d"(edx)); |
| 189 | } |
| 190 | |
| 191 | static inline void __mwait(unsigned long eax, unsigned long ecx) |
| 192 | { |
| 193 | /* "mwait %eax,%ecx;" */ |
| 194 | asm volatile( |
| 195 | ".byte 0x0f,0x01,0xc9;" |
| 196 | : :"a" (eax), "c" (ecx)); |
| 197 | } |
| 198 | |
Venkatesh Pallipadi | 991528d | 2006-09-25 16:28:13 -0700 | [diff] [blame] | 199 | extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); |
| 200 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | /* from system description table in BIOS. Mostly for MCA use, but |
| 202 | others may find it useful. */ |
| 203 | extern unsigned int machine_id; |
| 204 | extern unsigned int machine_submodel_id; |
| 205 | extern unsigned int BIOS_revision; |
| 206 | extern unsigned int mca_pentium_flag; |
| 207 | |
| 208 | /* Boot loader type from the setup header */ |
| 209 | extern int bootloader_type; |
| 210 | |
| 211 | /* |
| 212 | * User space process size: 3GB (default). |
| 213 | */ |
| 214 | #define TASK_SIZE (PAGE_OFFSET) |
| 215 | |
| 216 | /* This decides where the kernel will search for a free chunk of vm |
| 217 | * space during mmap's. |
| 218 | */ |
| 219 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) |
| 220 | |
| 221 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
| 222 | |
Andrea Arcangeli | cf99aba | 2007-07-15 23:41:33 -0700 | [diff] [blame] | 223 | extern void hard_disable_TSC(void); |
| 224 | extern void disable_TSC(void); |
| 225 | extern void hard_enable_TSC(void); |
| 226 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | /* |
| 228 | * Size of io_bitmap. |
| 229 | */ |
| 230 | #define IO_BITMAP_BITS 65536 |
| 231 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) |
| 232 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) |
| 233 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap) |
| 234 | #define INVALID_IO_BITMAP_OFFSET 0x8000 |
| 235 | #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 |
| 236 | |
| 237 | struct i387_fsave_struct { |
| 238 | long cwd; |
| 239 | long swd; |
| 240 | long twd; |
| 241 | long fip; |
| 242 | long fcs; |
| 243 | long foo; |
| 244 | long fos; |
| 245 | long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ |
| 246 | long status; /* software status information */ |
| 247 | }; |
| 248 | |
| 249 | struct i387_fxsave_struct { |
| 250 | unsigned short cwd; |
| 251 | unsigned short swd; |
| 252 | unsigned short twd; |
| 253 | unsigned short fop; |
| 254 | long fip; |
| 255 | long fcs; |
| 256 | long foo; |
| 257 | long fos; |
| 258 | long mxcsr; |
| 259 | long mxcsr_mask; |
| 260 | long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ |
| 261 | long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ |
| 262 | long padding[56]; |
| 263 | } __attribute__ ((aligned (16))); |
| 264 | |
| 265 | struct i387_soft_struct { |
| 266 | long cwd; |
| 267 | long swd; |
| 268 | long twd; |
| 269 | long fip; |
| 270 | long fcs; |
| 271 | long foo; |
| 272 | long fos; |
| 273 | long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ |
| 274 | unsigned char ftop, changed, lookahead, no_update, rm, alimit; |
| 275 | struct info *info; |
| 276 | unsigned long entry_eip; |
| 277 | }; |
| 278 | |
| 279 | union i387_union { |
| 280 | struct i387_fsave_struct fsave; |
| 281 | struct i387_fxsave_struct fxsave; |
| 282 | struct i387_soft_struct soft; |
| 283 | }; |
| 284 | |
| 285 | typedef struct { |
| 286 | unsigned long seg; |
| 287 | } mm_segment_t; |
| 288 | |
| 289 | struct thread_struct; |
| 290 | |
Rusty Russell | a75c54f | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 291 | /* This is the TSS defined by the hardware. */ |
| 292 | struct i386_hw_tss { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | unsigned short back_link,__blh; |
| 294 | unsigned long esp0; |
| 295 | unsigned short ss0,__ss0h; |
| 296 | unsigned long esp1; |
| 297 | unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */ |
| 298 | unsigned long esp2; |
| 299 | unsigned short ss2,__ss2h; |
| 300 | unsigned long __cr3; |
| 301 | unsigned long eip; |
| 302 | unsigned long eflags; |
| 303 | unsigned long eax,ecx,edx,ebx; |
| 304 | unsigned long esp; |
| 305 | unsigned long ebp; |
| 306 | unsigned long esi; |
| 307 | unsigned long edi; |
| 308 | unsigned short es, __esh; |
| 309 | unsigned short cs, __csh; |
| 310 | unsigned short ss, __ssh; |
| 311 | unsigned short ds, __dsh; |
| 312 | unsigned short fs, __fsh; |
| 313 | unsigned short gs, __gsh; |
| 314 | unsigned short ldt, __ldth; |
| 315 | unsigned short trace, io_bitmap_base; |
Rusty Russell | a75c54f | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 316 | } __attribute__((packed)); |
| 317 | |
| 318 | struct tss_struct { |
| 319 | struct i386_hw_tss x86_tss; |
| 320 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | /* |
| 322 | * The extra 1 is there because the CPU will access an |
| 323 | * additional byte beyond the end of the IO permission |
| 324 | * bitmap. The extra byte must be all 1 bits, and must |
| 325 | * be within the limit. |
| 326 | */ |
| 327 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
| 328 | /* |
| 329 | * Cache the current maximum and the last task that used the bitmap: |
| 330 | */ |
| 331 | unsigned long io_bitmap_max; |
| 332 | struct thread_struct *io_bitmap_owner; |
| 333 | /* |
| 334 | * pads the TSS to be cacheline-aligned (size is 0x100) |
| 335 | */ |
| 336 | unsigned long __cacheline_filler[35]; |
| 337 | /* |
| 338 | * .. and then another 0x100 bytes for emergency kernel stack |
| 339 | */ |
| 340 | unsigned long stack[64]; |
| 341 | } __attribute__((packed)); |
| 342 | |
| 343 | #define ARCH_MIN_TASKALIGN 16 |
| 344 | |
| 345 | struct thread_struct { |
| 346 | /* cached TLS descriptors. */ |
| 347 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; |
| 348 | unsigned long esp0; |
| 349 | unsigned long sysenter_cs; |
| 350 | unsigned long eip; |
| 351 | unsigned long esp; |
| 352 | unsigned long fs; |
| 353 | unsigned long gs; |
| 354 | /* Hardware debugging registers */ |
| 355 | unsigned long debugreg[8]; /* %%db0-7 debug registers */ |
| 356 | /* fault info */ |
| 357 | unsigned long cr2, trap_no, error_code; |
| 358 | /* floating point info */ |
| 359 | union i387_union i387; |
| 360 | /* virtual 86 mode info */ |
| 361 | struct vm86_struct __user * vm86_info; |
| 362 | unsigned long screen_bitmap; |
| 363 | unsigned long v86flags, v86mask, saved_esp0; |
| 364 | unsigned int saved_fs, saved_gs; |
| 365 | /* IO permissions */ |
| 366 | unsigned long *io_bitmap_ptr; |
Zachary Amsden | a520112 | 2005-09-03 15:56:44 -0700 | [diff] [blame] | 367 | unsigned long iopl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 368 | /* max allowed port in the bitmap, in bytes: */ |
| 369 | unsigned long io_bitmap_max; |
| 370 | }; |
| 371 | |
| 372 | #define INIT_THREAD { \ |
Rusty Russell | 692174b | 2007-05-02 19:27:09 +0200 | [diff] [blame] | 373 | .esp0 = sizeof(init_stack) + (long)&init_stack, \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | .vm86_info = NULL, \ |
| 375 | .sysenter_cs = __KERNEL_CS, \ |
| 376 | .io_bitmap_ptr = NULL, \ |
Jeremy Fitzhardinge | 7c3576d | 2007-05-02 19:27:16 +0200 | [diff] [blame] | 377 | .fs = __KERNEL_PERCPU, \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | /* |
| 381 | * Note that the .io_bitmap member must be extra-big. This is because |
| 382 | * the CPU will access an additional byte beyond the end of the IO |
| 383 | * permission bitmap. The extra byte must be all 1 bits, and must |
| 384 | * be within the limit. |
| 385 | */ |
| 386 | #define INIT_TSS { \ |
Rusty Russell | a75c54f | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 387 | .x86_tss = { \ |
| 388 | .esp0 = sizeof(init_stack) + (long)&init_stack, \ |
| 389 | .ss0 = __KERNEL_DS, \ |
| 390 | .ss1 = __KERNEL_CS, \ |
| 391 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ |
| 392 | }, \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \ |
| 394 | } |
| 395 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | #define start_thread(regs, new_eip, new_esp) do { \ |
Jeremy Fitzhardinge | 464d1a7 | 2007-02-13 13:26:20 +0100 | [diff] [blame] | 397 | __asm__("movl %0,%%gs": :"r" (0)); \ |
| 398 | regs->xfs = 0; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | set_fs(USER_DS); \ |
| 400 | regs->xds = __USER_DS; \ |
| 401 | regs->xes = __USER_DS; \ |
| 402 | regs->xss = __USER_DS; \ |
| 403 | regs->xcs = __USER_CS; \ |
| 404 | regs->eip = new_eip; \ |
| 405 | regs->esp = new_esp; \ |
| 406 | } while (0) |
| 407 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | /* Forward declaration, a strange C thing */ |
| 409 | struct task_struct; |
| 410 | struct mm_struct; |
| 411 | |
| 412 | /* Free all resources held by a thread. */ |
| 413 | extern void release_thread(struct task_struct *); |
| 414 | |
| 415 | /* Prepare to copy thread state - unlazy all lazy status */ |
| 416 | extern void prepare_to_copy(struct task_struct *tsk); |
| 417 | |
| 418 | /* |
| 419 | * create a kernel thread without removing it from tasklists |
| 420 | */ |
| 421 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); |
| 422 | |
| 423 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
Jan Beulich | 176a271 | 2006-06-26 13:57:41 +0200 | [diff] [blame] | 424 | void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | |
| 426 | unsigned long get_wchan(struct task_struct *p); |
| 427 | |
| 428 | #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) |
| 429 | #define KSTK_TOP(info) \ |
| 430 | ({ \ |
| 431 | unsigned long *__ptr = (unsigned long *)(info); \ |
| 432 | (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ |
| 433 | }) |
| 434 | |
akpm@osdl.org | 07b047f | 2006-01-12 01:05:41 -0800 | [diff] [blame] | 435 | /* |
| 436 | * The below -8 is to reserve 8 bytes on top of the ring0 stack. |
| 437 | * This is necessary to guarantee that the entire "struct pt_regs" |
| 438 | * is accessable even if the CPU haven't stored the SS/ESP registers |
| 439 | * on the stack (interrupt gate does not save these registers |
| 440 | * when switching to the same priv ring). |
| 441 | * Therefore beware: accessing the xss/esp fields of the |
| 442 | * "struct pt_regs" is possible, but they may contain the |
| 443 | * completely wrong values. |
| 444 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | #define task_pt_regs(task) \ |
| 446 | ({ \ |
| 447 | struct pt_regs *__regs__; \ |
Al Viro | 65e0fdf | 2006-01-12 01:05:41 -0800 | [diff] [blame] | 448 | __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | __regs__ - 1; \ |
| 450 | }) |
| 451 | |
| 452 | #define KSTK_EIP(task) (task_pt_regs(task)->eip) |
| 453 | #define KSTK_ESP(task) (task_pt_regs(task)->esp) |
| 454 | |
| 455 | |
| 456 | struct microcode_header { |
| 457 | unsigned int hdrver; |
| 458 | unsigned int rev; |
| 459 | unsigned int date; |
| 460 | unsigned int sig; |
| 461 | unsigned int cksum; |
| 462 | unsigned int ldrver; |
| 463 | unsigned int pf; |
| 464 | unsigned int datasize; |
| 465 | unsigned int totalsize; |
| 466 | unsigned int reserved[3]; |
| 467 | }; |
| 468 | |
| 469 | struct microcode { |
| 470 | struct microcode_header hdr; |
| 471 | unsigned int bits[0]; |
| 472 | }; |
| 473 | |
| 474 | typedef struct microcode microcode_t; |
| 475 | typedef struct microcode_header microcode_header_t; |
| 476 | |
| 477 | /* microcode format is extended from prescott processors */ |
| 478 | struct extended_signature { |
| 479 | unsigned int sig; |
| 480 | unsigned int pf; |
| 481 | unsigned int cksum; |
| 482 | }; |
| 483 | |
| 484 | struct extended_sigtable { |
| 485 | unsigned int count; |
| 486 | unsigned int cksum; |
| 487 | unsigned int reserved[3]; |
| 488 | struct extended_signature sigs[0]; |
| 489 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | |
| 491 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
| 492 | static inline void rep_nop(void) |
| 493 | { |
| 494 | __asm__ __volatile__("rep;nop": : :"memory"); |
| 495 | } |
| 496 | |
| 497 | #define cpu_relax() rep_nop() |
| 498 | |
Rusty Russell | 90a0a06 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 499 | static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread) |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 500 | { |
Rusty Russell | a75c54f | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 501 | tss->x86_tss.esp0 = thread->esp0; |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 502 | /* This can only happen when SEP is enabled, no need to test "SEP"arately */ |
Rusty Russell | a75c54f | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 503 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
| 504 | tss->x86_tss.ss1 = thread->sysenter_cs; |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 505 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); |
| 506 | } |
| 507 | } |
| 508 | |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 509 | |
Rusty Russell | 90a0a06 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 510 | static inline unsigned long native_get_debugreg(int regno) |
| 511 | { |
| 512 | unsigned long val = 0; /* Damn you, gcc! */ |
| 513 | |
| 514 | switch (regno) { |
| 515 | case 0: |
| 516 | asm("movl %%db0, %0" :"=r" (val)); break; |
| 517 | case 1: |
| 518 | asm("movl %%db1, %0" :"=r" (val)); break; |
| 519 | case 2: |
| 520 | asm("movl %%db2, %0" :"=r" (val)); break; |
| 521 | case 3: |
| 522 | asm("movl %%db3, %0" :"=r" (val)); break; |
| 523 | case 6: |
| 524 | asm("movl %%db6, %0" :"=r" (val)); break; |
| 525 | case 7: |
| 526 | asm("movl %%db7, %0" :"=r" (val)); break; |
| 527 | default: |
| 528 | BUG(); |
| 529 | } |
| 530 | return val; |
| 531 | } |
| 532 | |
| 533 | static inline void native_set_debugreg(int regno, unsigned long value) |
| 534 | { |
| 535 | switch (regno) { |
| 536 | case 0: |
| 537 | asm("movl %0,%%db0" : /* no output */ :"r" (value)); |
| 538 | break; |
| 539 | case 1: |
| 540 | asm("movl %0,%%db1" : /* no output */ :"r" (value)); |
| 541 | break; |
| 542 | case 2: |
| 543 | asm("movl %0,%%db2" : /* no output */ :"r" (value)); |
| 544 | break; |
| 545 | case 3: |
| 546 | asm("movl %0,%%db3" : /* no output */ :"r" (value)); |
| 547 | break; |
| 548 | case 6: |
| 549 | asm("movl %0,%%db6" : /* no output */ :"r" (value)); |
| 550 | break; |
| 551 | case 7: |
| 552 | asm("movl %0,%%db7" : /* no output */ :"r" (value)); |
| 553 | break; |
| 554 | default: |
| 555 | BUG(); |
| 556 | } |
| 557 | } |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 558 | |
| 559 | /* |
| 560 | * Set IOPL bits in EFLAGS from given mask |
| 561 | */ |
Rusty Russell | 90a0a06 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 562 | static inline void native_set_iopl_mask(unsigned mask) |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 563 | { |
| 564 | unsigned int reg; |
| 565 | __asm__ __volatile__ ("pushfl;" |
| 566 | "popl %0;" |
| 567 | "andl %1, %0;" |
| 568 | "orl %2, %0;" |
| 569 | "pushl %0;" |
| 570 | "popfl" |
| 571 | : "=&r" (reg) |
| 572 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); |
| 573 | } |
| 574 | |
Rusty Russell | 90a0a06 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 575 | #ifdef CONFIG_PARAVIRT |
| 576 | #include <asm/paravirt.h> |
| 577 | #else |
| 578 | #define paravirt_enabled() 0 |
| 579 | #define __cpuid native_cpuid |
| 580 | |
| 581 | static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread) |
| 582 | { |
| 583 | native_load_esp0(tss, thread); |
| 584 | } |
| 585 | |
| 586 | /* |
| 587 | * These special macros can be used to get or set a debugging register |
| 588 | */ |
| 589 | #define get_debugreg(var, register) \ |
| 590 | (var) = native_get_debugreg(register) |
| 591 | #define set_debugreg(value, register) \ |
| 592 | native_set_debugreg(register, value) |
| 593 | |
| 594 | #define set_iopl_mask native_set_iopl_mask |
| 595 | #endif /* CONFIG_PARAVIRT */ |
| 596 | |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 597 | /* |
| 598 | * Generic CPUID function |
| 599 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx |
| 600 | * resulting in stale register contents being returned. |
| 601 | */ |
Satyam Sharma | ffecad9 | 2007-10-17 18:04:38 +0200 | [diff] [blame] | 602 | static inline void cpuid(unsigned int op, |
| 603 | unsigned int *eax, unsigned int *ebx, |
| 604 | unsigned int *ecx, unsigned int *edx) |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 605 | { |
| 606 | *eax = op; |
| 607 | *ecx = 0; |
| 608 | __cpuid(eax, ebx, ecx, edx); |
| 609 | } |
| 610 | |
| 611 | /* Some CPUID calls want 'count' to be placed in ecx */ |
Satyam Sharma | ffecad9 | 2007-10-17 18:04:38 +0200 | [diff] [blame] | 612 | static inline void cpuid_count(unsigned int op, int count, |
| 613 | unsigned int *eax, unsigned int *ebx, |
| 614 | unsigned int *ecx, unsigned int *edx) |
Rusty Russell | 139ec7c | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 615 | { |
| 616 | *eax = op; |
| 617 | *ecx = count; |
| 618 | __cpuid(eax, ebx, ecx, edx); |
| 619 | } |
| 620 | |
| 621 | /* |
| 622 | * CPUID functions returning a single datum |
| 623 | */ |
| 624 | static inline unsigned int cpuid_eax(unsigned int op) |
| 625 | { |
| 626 | unsigned int eax, ebx, ecx, edx; |
| 627 | |
| 628 | cpuid(op, &eax, &ebx, &ecx, &edx); |
| 629 | return eax; |
| 630 | } |
| 631 | static inline unsigned int cpuid_ebx(unsigned int op) |
| 632 | { |
| 633 | unsigned int eax, ebx, ecx, edx; |
| 634 | |
| 635 | cpuid(op, &eax, &ebx, &ecx, &edx); |
| 636 | return ebx; |
| 637 | } |
| 638 | static inline unsigned int cpuid_ecx(unsigned int op) |
| 639 | { |
| 640 | unsigned int eax, ebx, ecx, edx; |
| 641 | |
| 642 | cpuid(op, &eax, &ebx, &ecx, &edx); |
| 643 | return ecx; |
| 644 | } |
| 645 | static inline unsigned int cpuid_edx(unsigned int op) |
| 646 | { |
| 647 | unsigned int eax, ebx, ecx, edx; |
| 648 | |
| 649 | cpuid(op, &eax, &ebx, &ecx, &edx); |
| 650 | return edx; |
| 651 | } |
| 652 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | /* generic versions from gas */ |
| 654 | #define GENERIC_NOP1 ".byte 0x90\n" |
| 655 | #define GENERIC_NOP2 ".byte 0x89,0xf6\n" |
| 656 | #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n" |
| 657 | #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n" |
| 658 | #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4 |
| 659 | #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n" |
| 660 | #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n" |
| 661 | #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7 |
| 662 | |
| 663 | /* Opteron nops */ |
| 664 | #define K8_NOP1 GENERIC_NOP1 |
| 665 | #define K8_NOP2 ".byte 0x66,0x90\n" |
| 666 | #define K8_NOP3 ".byte 0x66,0x66,0x90\n" |
| 667 | #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n" |
| 668 | #define K8_NOP5 K8_NOP3 K8_NOP2 |
| 669 | #define K8_NOP6 K8_NOP3 K8_NOP3 |
| 670 | #define K8_NOP7 K8_NOP4 K8_NOP3 |
| 671 | #define K8_NOP8 K8_NOP4 K8_NOP4 |
| 672 | |
| 673 | /* K7 nops */ |
| 674 | /* uses eax dependencies (arbitary choice) */ |
| 675 | #define K7_NOP1 GENERIC_NOP1 |
| 676 | #define K7_NOP2 ".byte 0x8b,0xc0\n" |
| 677 | #define K7_NOP3 ".byte 0x8d,0x04,0x20\n" |
| 678 | #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n" |
| 679 | #define K7_NOP5 K7_NOP4 ASM_NOP1 |
| 680 | #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n" |
| 681 | #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n" |
| 682 | #define K7_NOP8 K7_NOP7 ASM_NOP1 |
| 683 | |
Jan Beulich | 32c464f | 2007-10-17 18:04:41 +0200 | [diff] [blame] | 684 | /* P6 nops */ |
| 685 | /* uses eax dependencies (Intel-recommended choice) */ |
| 686 | #define P6_NOP1 GENERIC_NOP1 |
| 687 | #define P6_NOP2 ".byte 0x66,0x90\n" |
| 688 | #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n" |
| 689 | #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n" |
| 690 | #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n" |
| 691 | #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n" |
| 692 | #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n" |
| 693 | #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n" |
| 694 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 695 | #ifdef CONFIG_MK8 |
| 696 | #define ASM_NOP1 K8_NOP1 |
| 697 | #define ASM_NOP2 K8_NOP2 |
| 698 | #define ASM_NOP3 K8_NOP3 |
| 699 | #define ASM_NOP4 K8_NOP4 |
| 700 | #define ASM_NOP5 K8_NOP5 |
| 701 | #define ASM_NOP6 K8_NOP6 |
| 702 | #define ASM_NOP7 K8_NOP7 |
| 703 | #define ASM_NOP8 K8_NOP8 |
| 704 | #elif defined(CONFIG_MK7) |
| 705 | #define ASM_NOP1 K7_NOP1 |
| 706 | #define ASM_NOP2 K7_NOP2 |
| 707 | #define ASM_NOP3 K7_NOP3 |
| 708 | #define ASM_NOP4 K7_NOP4 |
| 709 | #define ASM_NOP5 K7_NOP5 |
| 710 | #define ASM_NOP6 K7_NOP6 |
| 711 | #define ASM_NOP7 K7_NOP7 |
| 712 | #define ASM_NOP8 K7_NOP8 |
Jan Beulich | 32c464f | 2007-10-17 18:04:41 +0200 | [diff] [blame] | 713 | #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \ |
| 714 | defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \ |
| 715 | defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4) |
| 716 | #define ASM_NOP1 P6_NOP1 |
| 717 | #define ASM_NOP2 P6_NOP2 |
| 718 | #define ASM_NOP3 P6_NOP3 |
| 719 | #define ASM_NOP4 P6_NOP4 |
| 720 | #define ASM_NOP5 P6_NOP5 |
| 721 | #define ASM_NOP6 P6_NOP6 |
| 722 | #define ASM_NOP7 P6_NOP7 |
| 723 | #define ASM_NOP8 P6_NOP8 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | #else |
| 725 | #define ASM_NOP1 GENERIC_NOP1 |
| 726 | #define ASM_NOP2 GENERIC_NOP2 |
| 727 | #define ASM_NOP3 GENERIC_NOP3 |
| 728 | #define ASM_NOP4 GENERIC_NOP4 |
| 729 | #define ASM_NOP5 GENERIC_NOP5 |
| 730 | #define ASM_NOP6 GENERIC_NOP6 |
| 731 | #define ASM_NOP7 GENERIC_NOP7 |
| 732 | #define ASM_NOP8 GENERIC_NOP8 |
| 733 | #endif |
| 734 | |
| 735 | #define ASM_NOP_MAX 8 |
| 736 | |
| 737 | /* Prefetch instructions for Pentium III and AMD Athlon */ |
| 738 | /* It's not worth to care about 3dnow! prefetches for the K6 |
| 739 | because they are microcoded there and very slow. |
| 740 | However we don't do prefetches for pre XP Athlons currently |
| 741 | That should be fixed. */ |
| 742 | #define ARCH_HAS_PREFETCH |
Adrian Bunk | e2afe6745 | 2005-09-10 00:27:16 -0700 | [diff] [blame] | 743 | static inline void prefetch(const void *x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | { |
| 745 | alternative_input(ASM_NOP4, |
| 746 | "prefetchnta (%1)", |
| 747 | X86_FEATURE_XMM, |
| 748 | "r" (x)); |
| 749 | } |
| 750 | |
| 751 | #define ARCH_HAS_PREFETCH |
| 752 | #define ARCH_HAS_PREFETCHW |
| 753 | #define ARCH_HAS_SPINLOCK_PREFETCH |
| 754 | |
| 755 | /* 3dnow! prefetch to get an exclusive cache line. Useful for |
| 756 | spinlocks to avoid one state transition in the cache coherency protocol. */ |
Adrian Bunk | e2afe6745 | 2005-09-10 00:27:16 -0700 | [diff] [blame] | 757 | static inline void prefetchw(const void *x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | { |
| 759 | alternative_input(ASM_NOP4, |
| 760 | "prefetchw (%1)", |
| 761 | X86_FEATURE_3DNOW, |
| 762 | "r" (x)); |
| 763 | } |
| 764 | #define spin_lock_prefetch(x) prefetchw(x) |
| 765 | |
| 766 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
| 767 | |
| 768 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
| 769 | |
| 770 | extern unsigned long boot_option_idle_override; |
Li Shaohua | 6fe940d | 2005-06-25 14:54:53 -0700 | [diff] [blame] | 771 | extern void enable_sep_cpu(void); |
| 772 | extern int sysenter_setup(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
Jeremy Fitzhardinge | 297d9c0 | 2007-05-15 01:41:48 -0700 | [diff] [blame] | 774 | /* Defined in head.S */ |
| 775 | extern struct Xgt_desc_struct early_gdt_descr; |
| 776 | |
James Bottomley | 9ee79a3 | 2007-01-22 09:18:31 -0600 | [diff] [blame] | 777 | extern void cpu_set_gdt(int); |
Jeremy Fitzhardinge | c5413fb | 2007-05-02 19:27:16 +0200 | [diff] [blame] | 778 | extern void switch_to_new_gdt(void); |
Rusty Russell | d2cbcc4 | 2007-05-02 19:27:10 +0200 | [diff] [blame] | 779 | extern void cpu_init(void); |
Jeremy Fitzhardinge | 297d9c0 | 2007-05-15 01:41:48 -0700 | [diff] [blame] | 780 | extern void init_gdt(int cpu); |
Jeremy Fitzhardinge | 6211119 | 2006-12-07 02:14:02 +0100 | [diff] [blame] | 781 | |
Andi Kleen | f039b75 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 782 | extern int force_mwait; |
| 783 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | #endif /* __ASM_I386_PROCESSOR_H */ |