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Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +02001/*
2 * Marvell Orion SoCs IRQ chip driver.
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <asm/exception.h>
17#include <asm/mach/irq.h>
18
19#include "irqchip.h"
20
21/*
22 * Orion SoC main interrupt controller
23 */
24#define ORION_IRQS_PER_CHIP 32
25
26#define ORION_IRQ_CAUSE 0x00
27#define ORION_IRQ_MASK 0x04
28#define ORION_IRQ_FIQ_MASK 0x08
29#define ORION_IRQ_ENDP_MASK 0x0c
30
31static struct irq_domain *orion_irq_domain;
32
Stephen Boyd8783dd32014-03-04 16:40:30 -080033static void
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +020034__exception_irq_entry orion_handle_irq(struct pt_regs *regs)
35{
36 struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;
37 int n, base = 0;
38
39 for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) {
40 struct irq_chip_generic *gc =
41 irq_get_domain_generic_chip(orion_irq_domain, base);
42 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
43 gc->mask_cache;
44 while (stat) {
Sebastian Hesselbarthbffbc6e2014-04-28 23:12:08 +020045 u32 hwirq = __fls(stat);
Marc Zyngierf4bc9282014-08-26 11:03:25 +010046 handle_domain_irq(orion_irq_domain,
47 gc->irq_base + hwirq, regs);
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +020048 stat &= ~(1 << hwirq);
49 }
50 }
51}
52
53static int __init orion_irq_init(struct device_node *np,
54 struct device_node *parent)
55{
56 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
57 int n, ret, base, num_chips = 0;
58 struct resource r;
59
60 /* count number of irq chips by valid reg addresses */
61 while (of_address_to_resource(np, num_chips, &r) == 0)
62 num_chips++;
63
64 orion_irq_domain = irq_domain_add_linear(np,
65 num_chips * ORION_IRQS_PER_CHIP,
66 &irq_generic_chip_ops, NULL);
67 if (!orion_irq_domain)
68 panic("%s: unable to add irq domain\n", np->name);
69
70 ret = irq_alloc_domain_generic_chips(orion_irq_domain,
71 ORION_IRQS_PER_CHIP, 1, np->name,
72 handle_level_irq, clr, 0,
73 IRQ_GC_INIT_MASK_CACHE);
74 if (ret)
75 panic("%s: unable to alloc irq domain gc\n", np->name);
76
77 for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
78 struct irq_chip_generic *gc =
79 irq_get_domain_generic_chip(orion_irq_domain, base);
80
81 of_address_to_resource(np, n, &r);
82
83 if (!request_mem_region(r.start, resource_size(&r), np->name))
84 panic("%s: unable to request mem region %d",
85 np->name, n);
86
87 gc->reg_base = ioremap(r.start, resource_size(&r));
88 if (!gc->reg_base)
89 panic("%s: unable to map resource %d", np->name, n);
90
91 gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
92 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
93 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
94
95 /* mask all interrupts */
96 writel(0, gc->reg_base + ORION_IRQ_MASK);
97 }
98
99 set_handle_irq(orion_handle_irq);
100 return 0;
101}
102IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
103
104/*
105 * Orion SoC bridge interrupt controller
106 */
107#define ORION_BRIDGE_IRQ_CAUSE 0x00
108#define ORION_BRIDGE_IRQ_MASK 0x04
109
110static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
111{
112 struct irq_domain *d = irq_get_handler_data(irq);
Andrew Lunnd86e9af62014-02-07 00:41:58 +0100113
114 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200115 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
116 gc->mask_cache;
117
118 while (stat) {
Sebastian Hesselbarthbffbc6e2014-04-28 23:12:08 +0200119 u32 hwirq = __fls(stat);
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200120
121 generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq));
122 stat &= ~(1 << hwirq);
123 }
124}
125
Sebastian Hesselbarthe0318ec2014-01-24 00:10:32 +0100126/*
127 * Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register.
128 * To avoid interrupt events on stale irqs, we clear them before unmask.
129 */
130static unsigned int orion_bridge_irq_startup(struct irq_data *d)
131{
132 struct irq_chip_type *ct = irq_data_get_chip_type(d);
133
134 ct->chip.irq_ack(d);
135 ct->chip.irq_unmask(d);
136 return 0;
137}
138
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200139static int __init orion_bridge_irq_init(struct device_node *np,
140 struct device_node *parent)
141{
142 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
143 struct resource r;
144 struct irq_domain *domain;
145 struct irq_chip_generic *gc;
146 int ret, irq, nrirqs = 32;
147
148 /* get optional number of interrupts provided */
149 of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
150
151 domain = irq_domain_add_linear(np, nrirqs,
152 &irq_generic_chip_ops, NULL);
153 if (!domain) {
154 pr_err("%s: unable to add irq domain\n", np->name);
155 return -ENOMEM;
156 }
157
158 ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
Sebastian Hesselbarth5f400672014-01-23 23:38:05 +0100159 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200160 if (ret) {
161 pr_err("%s: unable to alloc irq domain gc\n", np->name);
162 return ret;
163 }
164
165 ret = of_address_to_resource(np, 0, &r);
166 if (ret) {
167 pr_err("%s: unable to get resource\n", np->name);
168 return ret;
169 }
170
171 if (!request_mem_region(r.start, resource_size(&r), np->name)) {
172 pr_err("%s: unable to request mem region\n", np->name);
173 return -ENOMEM;
174 }
175
176 /* Map the parent interrupt for the chained handler */
177 irq = irq_of_parse_and_map(np, 0);
178 if (irq <= 0) {
179 pr_err("%s: unable to parse irq\n", np->name);
180 return -EINVAL;
181 }
182
183 gc = irq_get_domain_generic_chip(domain, 0);
184 gc->reg_base = ioremap(r.start, resource_size(&r));
185 if (!gc->reg_base) {
186 pr_err("%s: unable to map resource\n", np->name);
187 return -ENOMEM;
188 }
189
190 gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
191 gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
Sebastian Hesselbarthe0318ec2014-01-24 00:10:32 +0100192 gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200193 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
194 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
195 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
196
Sebastian Hesselbarth7b119fd2014-01-23 23:38:04 +0100197 /* mask and clear all interrupts */
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200198 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
Sebastian Hesselbarth7b119fd2014-01-23 23:38:04 +0100199 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200200
201 irq_set_handler_data(irq, domain);
202 irq_set_chained_handler(irq, orion_bridge_irq_handler);
203
204 return 0;
205}
206IRQCHIP_DECLARE(orion_bridge_intc,
207 "marvell,orion-bridge-intc", orion_bridge_irq_init);