blob: c826137dc6517c2d9d5c5bcef23c45b063659f37 [file] [log] [blame]
Scott Feldman01f2e4e2008-09-15 09:17:11 -07001/*
2 * Copyright 2008 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#ifndef _VNIC_WQ_H_
21#define _VNIC_WQ_H_
22
23#include <linux/pci.h>
24
25#include "vnic_dev.h"
26#include "vnic_cq.h"
27
28/* Work queue control */
29struct vnic_wq_ctrl {
30 u64 ring_base; /* 0x00 */
31 u32 ring_size; /* 0x08 */
32 u32 pad0;
33 u32 posted_index; /* 0x10 */
34 u32 pad1;
35 u32 cq_index; /* 0x18 */
36 u32 pad2;
37 u32 enable; /* 0x20 */
38 u32 pad3;
39 u32 running; /* 0x28 */
40 u32 pad4;
41 u32 fetch_index; /* 0x30 */
42 u32 pad5;
43 u32 dca_value; /* 0x38 */
44 u32 pad6;
45 u32 error_interrupt_enable; /* 0x40 */
46 u32 pad7;
47 u32 error_interrupt_offset; /* 0x48 */
48 u32 pad8;
49 u32 error_status; /* 0x50 */
50 u32 pad9;
51};
52
53struct vnic_wq_buf {
54 struct vnic_wq_buf *next;
55 dma_addr_t dma_addr;
56 void *os_buf;
57 unsigned int len;
58 unsigned int index;
59 int sop;
60 void *desc;
61};
62
63/* Break the vnic_wq_buf allocations into blocks of 64 entries */
64#define VNIC_WQ_BUF_BLK_ENTRIES 64
65#define VNIC_WQ_BUF_BLK_SZ \
66 (VNIC_WQ_BUF_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
67#define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
68 DIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES)
69#define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
70
71struct vnic_wq {
72 unsigned int index;
73 struct vnic_dev *vdev;
74 struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
75 struct vnic_dev_ring ring;
76 struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
77 struct vnic_wq_buf *to_use;
78 struct vnic_wq_buf *to_clean;
79 unsigned int pkts_outstanding;
80};
81
82static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
83{
84 /* how many does SW own? */
85 return wq->ring.desc_avail;
86}
87
88static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
89{
90 /* how many does HW own? */
91 return wq->ring.desc_count - wq->ring.desc_avail - 1;
92}
93
94static inline void *vnic_wq_next_desc(struct vnic_wq *wq)
95{
96 return wq->to_use->desc;
97}
98
99static inline void vnic_wq_post(struct vnic_wq *wq,
100 void *os_buf, dma_addr_t dma_addr,
101 unsigned int len, int sop, int eop)
102{
103 struct vnic_wq_buf *buf = wq->to_use;
104
105 buf->sop = sop;
106 buf->os_buf = eop ? os_buf : NULL;
107 buf->dma_addr = dma_addr;
108 buf->len = len;
109
110 buf = buf->next;
Scott Feldman84596452008-11-21 21:29:01 -0800111 if (eop) {
112 /* Adding write memory barrier prevents compiler and/or CPU
113 * reordering, thus avoiding descriptor posting before
114 * descriptor is initialized. Otherwise, hardware can read
115 * stale descriptor fields.
116 */
117 wmb();
Scott Feldman01f2e4e2008-09-15 09:17:11 -0700118 iowrite32(buf->index, &wq->ctrl->posted_index);
Scott Feldman84596452008-11-21 21:29:01 -0800119 }
Scott Feldman01f2e4e2008-09-15 09:17:11 -0700120 wq->to_use = buf;
121
122 wq->ring.desc_avail--;
123}
124
125static inline void vnic_wq_service(struct vnic_wq *wq,
126 struct cq_desc *cq_desc, u16 completed_index,
127 void (*buf_service)(struct vnic_wq *wq,
128 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
129 void *opaque)
130{
131 struct vnic_wq_buf *buf;
132
133 buf = wq->to_clean;
134 while (1) {
135
136 (*buf_service)(wq, cq_desc, buf, opaque);
137
138 wq->ring.desc_avail++;
139
140 wq->to_clean = buf->next;
141
142 if (buf->index == completed_index)
143 break;
144
145 buf = wq->to_clean;
146 }
147}
148
149void vnic_wq_free(struct vnic_wq *wq);
150int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
151 unsigned int desc_count, unsigned int desc_size);
152void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
153 unsigned int error_interrupt_enable,
154 unsigned int error_interrupt_offset);
155unsigned int vnic_wq_error_status(struct vnic_wq *wq);
156void vnic_wq_enable(struct vnic_wq *wq);
157int vnic_wq_disable(struct vnic_wq *wq);
158void vnic_wq_clean(struct vnic_wq *wq,
159 void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
160
161#endif /* _VNIC_WQ_H_ */