| Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Synopsys Designware PCIe host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | struct pcie_port_info { |
| 15 | u32 cfg0_size; |
| 16 | u32 cfg1_size; |
| 17 | u32 io_size; |
| 18 | u32 mem_size; |
| 19 | phys_addr_t io_bus_addr; |
| 20 | phys_addr_t mem_bus_addr; |
| 21 | }; |
| 22 | |
| Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame^] | 23 | /* |
| 24 | * Maximum number of MSI IRQs can be 256 per controller. But keep |
| 25 | * it 32 as of now. Probably we will never need more than 32. If needed, |
| 26 | * then increment it in multiple of 32. |
| 27 | */ |
| 28 | #define MAX_MSI_IRQS 32 |
| 29 | #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) |
| 30 | |
| Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 31 | struct pcie_port { |
| 32 | struct device *dev; |
| 33 | u8 root_bus_nr; |
| 34 | void __iomem *dbi_base; |
| 35 | u64 cfg0_base; |
| 36 | void __iomem *va_cfg0_base; |
| 37 | u64 cfg1_base; |
| 38 | void __iomem *va_cfg1_base; |
| 39 | u64 io_base; |
| 40 | u64 mem_base; |
| 41 | spinlock_t conf_lock; |
| 42 | struct resource cfg; |
| 43 | struct resource io; |
| 44 | struct resource mem; |
| 45 | struct pcie_port_info config; |
| 46 | int irq; |
| 47 | u32 lanes; |
| 48 | struct pcie_host_ops *ops; |
| Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame^] | 49 | int msi_irq; |
| 50 | int msi_irq_start; |
| 51 | unsigned long msi_data; |
| 52 | DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); |
| Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | struct pcie_host_ops { |
| 56 | void (*readl_rc)(struct pcie_port *pp, |
| 57 | void __iomem *dbi_base, u32 *val); |
| 58 | void (*writel_rc)(struct pcie_port *pp, |
| 59 | u32 val, void __iomem *dbi_base); |
| 60 | int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); |
| 61 | int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); |
| 62 | int (*link_up)(struct pcie_port *pp); |
| 63 | void (*host_init)(struct pcie_port *pp); |
| 64 | }; |
| 65 | |
| 66 | extern unsigned long global_io_offset; |
| 67 | |
| 68 | int cfg_read(void __iomem *addr, int where, int size, u32 *val); |
| 69 | int cfg_write(void __iomem *addr, int where, int size, u32 val); |
| 70 | int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val); |
| 71 | int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val); |
| Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame^] | 72 | void dw_handle_msi_irq(struct pcie_port *pp); |
| 73 | void dw_pcie_msi_init(struct pcie_port *pp); |
| Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 74 | int dw_pcie_link_up(struct pcie_port *pp); |
| 75 | void dw_pcie_setup_rc(struct pcie_port *pp); |
| 76 | int dw_pcie_host_init(struct pcie_port *pp); |
| 77 | int dw_pcie_setup(int nr, struct pci_sys_data *sys); |
| 78 | struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); |
| 79 | int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); |