Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 1 | /* |
| 2 | * TI OMAP4 ISS V4L2 Driver |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments. |
| 5 | * |
| 6 | * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _OMAP4_ISS_H_ |
| 15 | #define _OMAP4_ISS_H_ |
| 16 | |
| 17 | #include <media/v4l2-device.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/wait.h> |
| 22 | |
| 23 | #include <media/omap4iss.h> |
| 24 | |
| 25 | #include "iss_regs.h" |
| 26 | #include "iss_csiphy.h" |
| 27 | #include "iss_csi2.h" |
| 28 | #include "iss_ipipeif.h" |
| 29 | #include "iss_ipipe.h" |
| 30 | #include "iss_resizer.h" |
| 31 | |
| 32 | #define to_iss_device(ptr_module) \ |
| 33 | container_of(ptr_module, struct iss_device, ptr_module) |
| 34 | #define to_device(ptr_module) \ |
| 35 | (to_iss_device(ptr_module)->dev) |
| 36 | |
| 37 | enum iss_mem_resources { |
| 38 | OMAP4_ISS_MEM_TOP, |
| 39 | OMAP4_ISS_MEM_CSI2_A_REGS1, |
| 40 | OMAP4_ISS_MEM_CAMERARX_CORE1, |
| 41 | OMAP4_ISS_MEM_CSI2_B_REGS1, |
| 42 | OMAP4_ISS_MEM_CAMERARX_CORE2, |
| 43 | OMAP4_ISS_MEM_BTE, |
| 44 | OMAP4_ISS_MEM_ISP_SYS1, |
| 45 | OMAP4_ISS_MEM_ISP_RESIZER, |
| 46 | OMAP4_ISS_MEM_ISP_IPIPE, |
| 47 | OMAP4_ISS_MEM_ISP_ISIF, |
| 48 | OMAP4_ISS_MEM_ISP_IPIPEIF, |
| 49 | OMAP4_ISS_MEM_LAST, |
| 50 | }; |
| 51 | |
| 52 | enum iss_subclk_resource { |
| 53 | OMAP4_ISS_SUBCLK_SIMCOP = (1 << 0), |
| 54 | OMAP4_ISS_SUBCLK_ISP = (1 << 1), |
| 55 | OMAP4_ISS_SUBCLK_CSI2_A = (1 << 2), |
| 56 | OMAP4_ISS_SUBCLK_CSI2_B = (1 << 3), |
| 57 | OMAP4_ISS_SUBCLK_CCP2 = (1 << 4), |
| 58 | }; |
| 59 | |
| 60 | enum iss_isp_subclk_resource { |
| 61 | OMAP4_ISS_ISP_SUBCLK_BL = (1 << 0), |
| 62 | OMAP4_ISS_ISP_SUBCLK_ISIF = (1 << 1), |
| 63 | OMAP4_ISS_ISP_SUBCLK_H3A = (1 << 2), |
| 64 | OMAP4_ISS_ISP_SUBCLK_RSZ = (1 << 3), |
| 65 | OMAP4_ISS_ISP_SUBCLK_IPIPE = (1 << 4), |
| 66 | OMAP4_ISS_ISP_SUBCLK_IPIPEIF = (1 << 5), |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * struct iss_reg - Structure for ISS register values. |
| 71 | * @reg: 32-bit Register address. |
| 72 | * @val: 32-bit Register value. |
| 73 | */ |
| 74 | struct iss_reg { |
| 75 | enum iss_mem_resources mmio_range; |
| 76 | u32 reg; |
| 77 | u32 val; |
| 78 | }; |
| 79 | |
Laurent Pinchart | f3632ba | 2013-10-09 11:52:45 -0300 | [diff] [blame^] | 80 | /* |
| 81 | * struct iss_device - ISS device structure. |
| 82 | * @crashed: Bitmask of crashed entities (indexed by entity ID) |
| 83 | */ |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 84 | struct iss_device { |
| 85 | struct v4l2_device v4l2_dev; |
| 86 | struct media_device media_dev; |
| 87 | struct device *dev; |
| 88 | u32 revision; |
| 89 | |
| 90 | /* platform HW resources */ |
| 91 | struct iss_platform_data *pdata; |
| 92 | unsigned int irq_num; |
| 93 | |
| 94 | struct resource *res[OMAP4_ISS_MEM_LAST]; |
| 95 | void __iomem *regs[OMAP4_ISS_MEM_LAST]; |
| 96 | |
| 97 | u64 raw_dmamask; |
| 98 | |
| 99 | struct mutex iss_mutex; /* For handling ref_count field */ |
Laurent Pinchart | f3632ba | 2013-10-09 11:52:45 -0300 | [diff] [blame^] | 100 | bool crashed; |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 101 | int has_context; |
| 102 | int ref_count; |
| 103 | |
| 104 | struct clk *iss_fck; |
| 105 | struct clk *iss_ctrlclk; |
| 106 | |
| 107 | /* ISS modules */ |
| 108 | struct iss_csi2_device csi2a; |
| 109 | struct iss_csi2_device csi2b; |
| 110 | struct iss_csiphy csiphy1; |
| 111 | struct iss_csiphy csiphy2; |
| 112 | struct iss_ipipeif_device ipipeif; |
| 113 | struct iss_ipipe_device ipipe; |
| 114 | struct iss_resizer_device resizer; |
| 115 | |
| 116 | unsigned int subclk_resources; |
| 117 | unsigned int isp_subclk_resources; |
| 118 | }; |
| 119 | |
| 120 | #define v4l2_dev_to_iss_device(dev) \ |
| 121 | container_of(dev, struct iss_device, v4l2_dev) |
| 122 | |
| 123 | int omap4iss_get_external_info(struct iss_pipeline *pipe, |
| 124 | struct media_link *link); |
| 125 | |
| 126 | int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, |
| 127 | atomic_t *stopping); |
| 128 | |
| 129 | int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait, |
| 130 | atomic_t *stopping); |
| 131 | |
| 132 | int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe, |
| 133 | enum iss_pipeline_stream_state state); |
| 134 | |
| 135 | void omap4iss_configure_bridge(struct iss_device *iss, |
| 136 | enum ipipeif_input_entity input); |
| 137 | |
| 138 | struct iss_device *omap4iss_get(struct iss_device *iss); |
| 139 | void omap4iss_put(struct iss_device *iss); |
| 140 | int omap4iss_subclk_enable(struct iss_device *iss, |
| 141 | enum iss_subclk_resource res); |
| 142 | int omap4iss_subclk_disable(struct iss_device *iss, |
| 143 | enum iss_subclk_resource res); |
Laurent Pinchart | 68c03a6 | 2013-11-03 20:28:24 -0300 | [diff] [blame] | 144 | void omap4iss_isp_subclk_enable(struct iss_device *iss, |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 145 | enum iss_isp_subclk_resource res); |
Laurent Pinchart | 68c03a6 | 2013-11-03 20:28:24 -0300 | [diff] [blame] | 146 | void omap4iss_isp_subclk_disable(struct iss_device *iss, |
| 147 | enum iss_isp_subclk_resource res); |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 148 | |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 149 | int omap4iss_pipeline_pm_use(struct media_entity *entity, int use); |
| 150 | |
| 151 | int omap4iss_register_entities(struct platform_device *pdev, |
| 152 | struct v4l2_device *v4l2_dev); |
| 153 | void omap4iss_unregister_entities(struct platform_device *pdev); |
| 154 | |
Laurent Pinchart | 11abbfd | 2013-08-30 22:23:17 -0300 | [diff] [blame] | 155 | /* |
| 156 | * iss_reg_read - Read the value of an OMAP4 ISS register |
| 157 | * @iss: the ISS device |
| 158 | * @res: memory resource in which the register is located |
| 159 | * @offset: register offset in the memory resource |
| 160 | * |
| 161 | * Return the register value. |
| 162 | */ |
| 163 | static inline |
| 164 | u32 iss_reg_read(struct iss_device *iss, enum iss_mem_resources res, |
| 165 | u32 offset) |
| 166 | { |
| 167 | return readl(iss->regs[res] + offset); |
| 168 | } |
| 169 | |
| 170 | /* |
| 171 | * iss_reg_write - Write a value to an OMAP4 ISS register |
| 172 | * @iss: the ISS device |
| 173 | * @res: memory resource in which the register is located |
| 174 | * @offset: register offset in the memory resource |
| 175 | * @value: value to be written |
| 176 | */ |
| 177 | static inline |
| 178 | void iss_reg_write(struct iss_device *iss, enum iss_mem_resources res, |
| 179 | u32 offset, u32 value) |
| 180 | { |
| 181 | writel(value, iss->regs[res] + offset); |
| 182 | } |
| 183 | |
| 184 | /* |
| 185 | * iss_reg_clr - Clear bits in an OMAP4 ISS register |
| 186 | * @iss: the ISS device |
| 187 | * @res: memory resource in which the register is located |
| 188 | * @offset: register offset in the memory resource |
| 189 | * @clr: bit mask to be cleared |
| 190 | */ |
| 191 | static inline |
| 192 | void iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res, |
| 193 | u32 offset, u32 clr) |
| 194 | { |
| 195 | u32 v = iss_reg_read(iss, res, offset); |
| 196 | |
| 197 | iss_reg_write(iss, res, offset, v & ~clr); |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * iss_reg_set - Set bits in an OMAP4 ISS register |
| 202 | * @iss: the ISS device |
| 203 | * @res: memory resource in which the register is located |
| 204 | * @offset: register offset in the memory resource |
| 205 | * @set: bit mask to be set |
| 206 | */ |
| 207 | static inline |
| 208 | void iss_reg_set(struct iss_device *iss, enum iss_mem_resources res, |
| 209 | u32 offset, u32 set) |
| 210 | { |
| 211 | u32 v = iss_reg_read(iss, res, offset); |
| 212 | |
| 213 | iss_reg_write(iss, res, offset, v | set); |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * iss_reg_update - Clear and set bits in an OMAP4 ISS register |
| 218 | * @iss: the ISS device |
| 219 | * @res: memory resource in which the register is located |
| 220 | * @offset: register offset in the memory resource |
| 221 | * @clr: bit mask to be cleared |
| 222 | * @set: bit mask to be set |
| 223 | * |
| 224 | * Clear the clr mask first and then set the set mask. |
| 225 | */ |
| 226 | static inline |
| 227 | void iss_reg_update(struct iss_device *iss, enum iss_mem_resources res, |
| 228 | u32 offset, u32 clr, u32 set) |
| 229 | { |
| 230 | u32 v = iss_reg_read(iss, res, offset); |
| 231 | |
| 232 | iss_reg_write(iss, res, offset, (v & ~clr) | set); |
| 233 | } |
| 234 | |
Sergio Aguirre | 59f0ad8 | 2011-01-24 15:48:19 -0300 | [diff] [blame] | 235 | #endif /* _OMAP4_ISS_H_ */ |