Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, Sony Mobile Communications AB. |
| 3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 and |
| 7 | * only version 2 as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/irqdomain.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/pinctrl/machine.h> |
| 22 | #include <linux/pinctrl/pinctrl.h> |
| 23 | #include <linux/pinctrl/pinmux.h> |
| 24 | #include <linux/pinctrl/pinconf.h> |
| 25 | #include <linux/pinctrl/pinconf-generic.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/gpio.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/irq.h> |
| 30 | #include <linux/irqchip/chained_irq.h> |
| 31 | #include <linux/of_irq.h> |
| 32 | #include <linux/spinlock.h> |
| 33 | |
| 34 | #include "core.h" |
| 35 | #include "pinconf.h" |
| 36 | #include "pinctrl-msm.h" |
| 37 | #include "pinctrl-utils.h" |
| 38 | |
| 39 | /** |
| 40 | * struct msm_pinctrl - state for a pinctrl-msm device |
| 41 | * @dev: device handle. |
| 42 | * @pctrl: pinctrl handle. |
| 43 | * @domain: irqdomain handle. |
| 44 | * @chip: gpiochip handle. |
| 45 | * @irq: parent irq for the TLMM irq_chip. |
| 46 | * @lock: Spinlock to protect register resources as well |
| 47 | * as msm_pinctrl data structures. |
| 48 | * @enabled_irqs: Bitmap of currently enabled irqs. |
| 49 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge |
| 50 | * detection. |
| 51 | * @wake_irqs: Bitmap of irqs with requested as wakeup source. |
| 52 | * @soc; Reference to soc_data of platform specific data. |
| 53 | * @regs: Base address for the TLMM register map. |
| 54 | */ |
| 55 | struct msm_pinctrl { |
| 56 | struct device *dev; |
| 57 | struct pinctrl_dev *pctrl; |
| 58 | struct irq_domain *domain; |
| 59 | struct gpio_chip chip; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 60 | int irq; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 61 | |
| 62 | spinlock_t lock; |
| 63 | |
| 64 | unsigned long *enabled_irqs; |
| 65 | unsigned long *dual_edge_irqs; |
| 66 | unsigned long *wake_irqs; |
| 67 | |
| 68 | const struct msm_pinctrl_soc_data *soc; |
| 69 | void __iomem *regs; |
| 70 | }; |
| 71 | |
| 72 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) |
| 73 | { |
| 74 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 75 | |
| 76 | return pctrl->soc->ngroups; |
| 77 | } |
| 78 | |
| 79 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, |
| 80 | unsigned group) |
| 81 | { |
| 82 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 83 | |
| 84 | return pctrl->soc->groups[group].name; |
| 85 | } |
| 86 | |
| 87 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, |
| 88 | unsigned group, |
| 89 | const unsigned **pins, |
| 90 | unsigned *num_pins) |
| 91 | { |
| 92 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 93 | |
| 94 | *pins = pctrl->soc->groups[group].pins; |
| 95 | *num_pins = pctrl->soc->groups[group].npins; |
| 96 | return 0; |
| 97 | } |
| 98 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 99 | static const struct pinctrl_ops msm_pinctrl_ops = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 100 | .get_groups_count = msm_get_groups_count, |
| 101 | .get_group_name = msm_get_group_name, |
| 102 | .get_group_pins = msm_get_group_pins, |
| 103 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
| 104 | .dt_free_map = pinctrl_utils_dt_free_map, |
| 105 | }; |
| 106 | |
| 107 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) |
| 108 | { |
| 109 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 110 | |
| 111 | return pctrl->soc->nfunctions; |
| 112 | } |
| 113 | |
| 114 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, |
| 115 | unsigned function) |
| 116 | { |
| 117 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 118 | |
| 119 | return pctrl->soc->functions[function].name; |
| 120 | } |
| 121 | |
| 122 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, |
| 123 | unsigned function, |
| 124 | const char * const **groups, |
| 125 | unsigned * const num_groups) |
| 126 | { |
| 127 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 128 | |
| 129 | *groups = pctrl->soc->functions[function].groups; |
| 130 | *num_groups = pctrl->soc->functions[function].ngroups; |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | static int msm_pinmux_enable(struct pinctrl_dev *pctldev, |
| 135 | unsigned function, |
| 136 | unsigned group) |
| 137 | { |
| 138 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 139 | const struct msm_pingroup *g; |
| 140 | unsigned long flags; |
| 141 | u32 val; |
| 142 | int i; |
| 143 | |
| 144 | g = &pctrl->soc->groups[group]; |
| 145 | |
| 146 | if (WARN_ON(g->mux_bit < 0)) |
| 147 | return -EINVAL; |
| 148 | |
| 149 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { |
| 150 | if (g->funcs[i] == function) |
| 151 | break; |
| 152 | } |
| 153 | |
| 154 | if (WARN_ON(i == ARRAY_SIZE(g->funcs))) |
| 155 | return -EINVAL; |
| 156 | |
| 157 | spin_lock_irqsave(&pctrl->lock, flags); |
| 158 | |
| 159 | val = readl(pctrl->regs + g->ctl_reg); |
| 160 | val &= ~(0x7 << g->mux_bit); |
| 161 | val |= i << g->mux_bit; |
| 162 | writel(val, pctrl->regs + g->ctl_reg); |
| 163 | |
| 164 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | static void msm_pinmux_disable(struct pinctrl_dev *pctldev, |
| 170 | unsigned function, |
| 171 | unsigned group) |
| 172 | { |
| 173 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 174 | const struct msm_pingroup *g; |
| 175 | unsigned long flags; |
| 176 | u32 val; |
| 177 | |
| 178 | g = &pctrl->soc->groups[group]; |
| 179 | |
| 180 | if (WARN_ON(g->mux_bit < 0)) |
| 181 | return; |
| 182 | |
| 183 | spin_lock_irqsave(&pctrl->lock, flags); |
| 184 | |
| 185 | /* Clear the mux bits to select gpio mode */ |
| 186 | val = readl(pctrl->regs + g->ctl_reg); |
| 187 | val &= ~(0x7 << g->mux_bit); |
| 188 | writel(val, pctrl->regs + g->ctl_reg); |
| 189 | |
| 190 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 191 | } |
| 192 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 193 | static const struct pinmux_ops msm_pinmux_ops = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 194 | .get_functions_count = msm_get_functions_count, |
| 195 | .get_function_name = msm_get_function_name, |
| 196 | .get_function_groups = msm_get_function_groups, |
| 197 | .enable = msm_pinmux_enable, |
| 198 | .disable = msm_pinmux_disable, |
| 199 | }; |
| 200 | |
| 201 | static int msm_config_reg(struct msm_pinctrl *pctrl, |
| 202 | const struct msm_pingroup *g, |
| 203 | unsigned param, |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 204 | s16 *reg, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 205 | unsigned *mask, |
| 206 | unsigned *bit) |
| 207 | { |
| 208 | switch (param) { |
| 209 | case PIN_CONFIG_BIAS_DISABLE: |
| 210 | *reg = g->ctl_reg; |
| 211 | *bit = g->pull_bit; |
| 212 | *mask = 3; |
| 213 | break; |
| 214 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 215 | *reg = g->ctl_reg; |
| 216 | *bit = g->pull_bit; |
| 217 | *mask = 3; |
| 218 | break; |
| 219 | case PIN_CONFIG_BIAS_PULL_UP: |
| 220 | *reg = g->ctl_reg; |
| 221 | *bit = g->pull_bit; |
| 222 | *mask = 3; |
| 223 | break; |
| 224 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 225 | *reg = g->ctl_reg; |
| 226 | *bit = g->drv_bit; |
| 227 | *mask = 7; |
| 228 | break; |
| 229 | default: |
| 230 | dev_err(pctrl->dev, "Invalid config param %04x\n", param); |
| 231 | return -ENOTSUPP; |
| 232 | } |
| 233 | |
| 234 | if (*reg < 0) { |
| 235 | dev_err(pctrl->dev, "Config param %04x not supported on group %s\n", |
| 236 | param, g->name); |
| 237 | return -ENOTSUPP; |
| 238 | } |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | static int msm_config_get(struct pinctrl_dev *pctldev, |
| 244 | unsigned int pin, |
| 245 | unsigned long *config) |
| 246 | { |
| 247 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); |
| 248 | return -ENOTSUPP; |
| 249 | } |
| 250 | |
| 251 | static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, |
| 252 | unsigned long *configs, unsigned num_configs) |
| 253 | { |
| 254 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); |
| 255 | return -ENOTSUPP; |
| 256 | } |
| 257 | |
| 258 | #define MSM_NO_PULL 0 |
| 259 | #define MSM_PULL_DOWN 1 |
| 260 | #define MSM_PULL_UP 3 |
| 261 | |
| 262 | static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; |
| 263 | static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 }; |
| 264 | |
| 265 | static int msm_config_group_get(struct pinctrl_dev *pctldev, |
| 266 | unsigned int group, |
| 267 | unsigned long *config) |
| 268 | { |
| 269 | const struct msm_pingroup *g; |
| 270 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 271 | unsigned param = pinconf_to_config_param(*config); |
| 272 | unsigned mask; |
| 273 | unsigned arg; |
| 274 | unsigned bit; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 275 | s16 reg; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 276 | int ret; |
| 277 | u32 val; |
| 278 | |
| 279 | g = &pctrl->soc->groups[group]; |
| 280 | |
| 281 | ret = msm_config_reg(pctrl, g, param, ®, &mask, &bit); |
| 282 | if (ret < 0) |
| 283 | return ret; |
| 284 | |
| 285 | val = readl(pctrl->regs + reg); |
| 286 | arg = (val >> bit) & mask; |
| 287 | |
| 288 | /* Convert register value to pinconf value */ |
| 289 | switch (param) { |
| 290 | case PIN_CONFIG_BIAS_DISABLE: |
| 291 | arg = arg == MSM_NO_PULL; |
| 292 | break; |
| 293 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 294 | arg = arg == MSM_PULL_DOWN; |
| 295 | break; |
| 296 | case PIN_CONFIG_BIAS_PULL_UP: |
| 297 | arg = arg == MSM_PULL_UP; |
| 298 | break; |
| 299 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 300 | arg = msm_regval_to_drive[arg]; |
| 301 | break; |
| 302 | default: |
| 303 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", |
| 304 | param); |
| 305 | return -EINVAL; |
| 306 | } |
| 307 | |
| 308 | *config = pinconf_to_config_packed(param, arg); |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | static int msm_config_group_set(struct pinctrl_dev *pctldev, |
| 314 | unsigned group, |
| 315 | unsigned long *configs, |
| 316 | unsigned num_configs) |
| 317 | { |
| 318 | const struct msm_pingroup *g; |
| 319 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 320 | unsigned long flags; |
| 321 | unsigned param; |
| 322 | unsigned mask; |
| 323 | unsigned arg; |
| 324 | unsigned bit; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 325 | s16 reg; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 326 | int ret; |
| 327 | u32 val; |
| 328 | int i; |
| 329 | |
| 330 | g = &pctrl->soc->groups[group]; |
| 331 | |
| 332 | for (i = 0; i < num_configs; i++) { |
| 333 | param = pinconf_to_config_param(configs[i]); |
| 334 | arg = pinconf_to_config_argument(configs[i]); |
| 335 | |
| 336 | ret = msm_config_reg(pctrl, g, param, ®, &mask, &bit); |
| 337 | if (ret < 0) |
| 338 | return ret; |
| 339 | |
| 340 | /* Convert pinconf values to register values */ |
| 341 | switch (param) { |
| 342 | case PIN_CONFIG_BIAS_DISABLE: |
| 343 | arg = MSM_NO_PULL; |
| 344 | break; |
| 345 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 346 | arg = MSM_PULL_DOWN; |
| 347 | break; |
| 348 | case PIN_CONFIG_BIAS_PULL_UP: |
| 349 | arg = MSM_PULL_UP; |
| 350 | break; |
| 351 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 352 | /* Check for invalid values */ |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 353 | if (arg >= ARRAY_SIZE(msm_drive_to_regval)) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 354 | arg = -1; |
| 355 | else |
| 356 | arg = msm_drive_to_regval[arg]; |
| 357 | break; |
| 358 | default: |
| 359 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", |
| 360 | param); |
| 361 | return -EINVAL; |
| 362 | } |
| 363 | |
| 364 | /* Range-check user-supplied value */ |
| 365 | if (arg & ~mask) { |
| 366 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); |
| 367 | return -EINVAL; |
| 368 | } |
| 369 | |
| 370 | spin_lock_irqsave(&pctrl->lock, flags); |
| 371 | val = readl(pctrl->regs + reg); |
| 372 | val &= ~(mask << bit); |
| 373 | val |= arg << bit; |
| 374 | writel(val, pctrl->regs + reg); |
| 375 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 376 | } |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 381 | static const struct pinconf_ops msm_pinconf_ops = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 382 | .pin_config_get = msm_config_get, |
| 383 | .pin_config_set = msm_config_set, |
| 384 | .pin_config_group_get = msm_config_group_get, |
| 385 | .pin_config_group_set = msm_config_group_set, |
| 386 | }; |
| 387 | |
| 388 | static struct pinctrl_desc msm_pinctrl_desc = { |
| 389 | .pctlops = &msm_pinctrl_ops, |
| 390 | .pmxops = &msm_pinmux_ops, |
| 391 | .confops = &msm_pinconf_ops, |
| 392 | .owner = THIS_MODULE, |
| 393 | }; |
| 394 | |
| 395 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 396 | { |
| 397 | const struct msm_pingroup *g; |
| 398 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 399 | unsigned long flags; |
| 400 | u32 val; |
| 401 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 402 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 403 | if (WARN_ON(g->io_reg < 0)) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 404 | return -EINVAL; |
| 405 | |
| 406 | spin_lock_irqsave(&pctrl->lock, flags); |
| 407 | |
| 408 | val = readl(pctrl->regs + g->ctl_reg); |
| 409 | val &= ~BIT(g->oe_bit); |
| 410 | writel(val, pctrl->regs + g->ctl_reg); |
| 411 | |
| 412 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 413 | |
| 414 | return 0; |
| 415 | } |
| 416 | |
| 417 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) |
| 418 | { |
| 419 | const struct msm_pingroup *g; |
| 420 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 421 | unsigned long flags; |
| 422 | u32 val; |
| 423 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 424 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 425 | if (WARN_ON(g->io_reg < 0)) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 426 | return -EINVAL; |
| 427 | |
| 428 | spin_lock_irqsave(&pctrl->lock, flags); |
| 429 | |
| 430 | writel(value ? BIT(g->out_bit) : 0, pctrl->regs + g->io_reg); |
| 431 | |
| 432 | val = readl(pctrl->regs + g->ctl_reg); |
| 433 | val |= BIT(g->oe_bit); |
| 434 | writel(val, pctrl->regs + g->ctl_reg); |
| 435 | |
| 436 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 442 | { |
| 443 | const struct msm_pingroup *g; |
| 444 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 445 | u32 val; |
| 446 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 447 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 448 | if (WARN_ON(g->io_reg < 0)) |
| 449 | return -EINVAL; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 450 | |
| 451 | val = readl(pctrl->regs + g->io_reg); |
| 452 | return !!(val & BIT(g->in_bit)); |
| 453 | } |
| 454 | |
| 455 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 456 | { |
| 457 | const struct msm_pingroup *g; |
| 458 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 459 | unsigned long flags; |
| 460 | u32 val; |
| 461 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 462 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 463 | if (WARN_ON(g->io_reg < 0)) |
| 464 | return; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 465 | |
| 466 | spin_lock_irqsave(&pctrl->lock, flags); |
| 467 | |
| 468 | val = readl(pctrl->regs + g->io_reg); |
| 469 | val |= BIT(g->out_bit); |
| 470 | writel(val, pctrl->regs + g->io_reg); |
| 471 | |
| 472 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 473 | } |
| 474 | |
| 475 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 476 | { |
| 477 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 478 | |
| 479 | return irq_find_mapping(pctrl->domain, offset); |
| 480 | } |
| 481 | |
| 482 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 483 | { |
| 484 | int gpio = chip->base + offset; |
| 485 | return pinctrl_request_gpio(gpio); |
| 486 | } |
| 487 | |
| 488 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 489 | { |
| 490 | int gpio = chip->base + offset; |
| 491 | return pinctrl_free_gpio(gpio); |
| 492 | } |
| 493 | |
| 494 | #ifdef CONFIG_DEBUG_FS |
| 495 | #include <linux/seq_file.h> |
| 496 | |
| 497 | static void msm_gpio_dbg_show_one(struct seq_file *s, |
| 498 | struct pinctrl_dev *pctldev, |
| 499 | struct gpio_chip *chip, |
| 500 | unsigned offset, |
| 501 | unsigned gpio) |
| 502 | { |
| 503 | const struct msm_pingroup *g; |
| 504 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); |
| 505 | unsigned func; |
| 506 | int is_out; |
| 507 | int drive; |
| 508 | int pull; |
| 509 | u32 ctl_reg; |
| 510 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 511 | static const char * const pulls[] = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 512 | "no pull", |
| 513 | "pull down", |
| 514 | "keeper", |
| 515 | "pull up" |
| 516 | }; |
| 517 | |
| 518 | g = &pctrl->soc->groups[offset]; |
| 519 | ctl_reg = readl(pctrl->regs + g->ctl_reg); |
| 520 | |
| 521 | is_out = !!(ctl_reg & BIT(g->oe_bit)); |
| 522 | func = (ctl_reg >> g->mux_bit) & 7; |
| 523 | drive = (ctl_reg >> g->drv_bit) & 7; |
| 524 | pull = (ctl_reg >> g->pull_bit) & 3; |
| 525 | |
| 526 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); |
| 527 | seq_printf(s, " %dmA", msm_regval_to_drive[drive]); |
| 528 | seq_printf(s, " %s", pulls[pull]); |
| 529 | } |
| 530 | |
| 531 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 532 | { |
| 533 | unsigned gpio = chip->base; |
| 534 | unsigned i; |
| 535 | |
| 536 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
| 537 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 538 | seq_puts(s, "\n"); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 539 | } |
| 540 | } |
| 541 | |
| 542 | #else |
| 543 | #define msm_gpio_dbg_show NULL |
| 544 | #endif |
| 545 | |
| 546 | static struct gpio_chip msm_gpio_template = { |
| 547 | .direction_input = msm_gpio_direction_input, |
| 548 | .direction_output = msm_gpio_direction_output, |
| 549 | .get = msm_gpio_get, |
| 550 | .set = msm_gpio_set, |
| 551 | .to_irq = msm_gpio_to_irq, |
| 552 | .request = msm_gpio_request, |
| 553 | .free = msm_gpio_free, |
| 554 | .dbg_show = msm_gpio_dbg_show, |
| 555 | }; |
| 556 | |
| 557 | /* For dual-edge interrupts in software, since some hardware has no |
| 558 | * such support: |
| 559 | * |
| 560 | * At appropriate moments, this function may be called to flip the polarity |
| 561 | * settings of both-edge irq lines to try and catch the next edge. |
| 562 | * |
| 563 | * The attempt is considered successful if: |
| 564 | * - the status bit goes high, indicating that an edge was caught, or |
| 565 | * - the input value of the gpio doesn't change during the attempt. |
| 566 | * If the value changes twice during the process, that would cause the first |
| 567 | * test to fail but would force the second, as two opposite |
| 568 | * transitions would cause a detection no matter the polarity setting. |
| 569 | * |
| 570 | * The do-loop tries to sledge-hammer closed the timing hole between |
| 571 | * the initial value-read and the polarity-write - if the line value changes |
| 572 | * during that window, an interrupt is lost, the new polarity setting is |
| 573 | * incorrect, and the first success test will fail, causing a retry. |
| 574 | * |
| 575 | * Algorithm comes from Google's msmgpio driver. |
| 576 | */ |
| 577 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, |
| 578 | const struct msm_pingroup *g, |
| 579 | struct irq_data *d) |
| 580 | { |
| 581 | int loop_limit = 100; |
| 582 | unsigned val, val2, intstat; |
| 583 | unsigned pol; |
| 584 | |
| 585 | do { |
| 586 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); |
| 587 | |
| 588 | pol = readl(pctrl->regs + g->intr_cfg_reg); |
| 589 | pol ^= BIT(g->intr_polarity_bit); |
| 590 | writel(pol, pctrl->regs + g->intr_cfg_reg); |
| 591 | |
| 592 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); |
| 593 | intstat = readl(pctrl->regs + g->intr_status_reg); |
| 594 | if (intstat || (val == val2)) |
| 595 | return; |
| 596 | } while (loop_limit-- > 0); |
| 597 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", |
| 598 | val, val2); |
| 599 | } |
| 600 | |
| 601 | static void msm_gpio_irq_mask(struct irq_data *d) |
| 602 | { |
| 603 | const struct msm_pingroup *g; |
| 604 | struct msm_pinctrl *pctrl; |
| 605 | unsigned long flags; |
| 606 | u32 val; |
| 607 | |
| 608 | pctrl = irq_data_get_irq_chip_data(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 609 | g = &pctrl->soc->groups[d->hwirq]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 610 | if (WARN_ON(g->intr_cfg_reg < 0)) |
| 611 | return; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 612 | |
| 613 | spin_lock_irqsave(&pctrl->lock, flags); |
| 614 | |
| 615 | val = readl(pctrl->regs + g->intr_cfg_reg); |
| 616 | val &= ~BIT(g->intr_enable_bit); |
| 617 | writel(val, pctrl->regs + g->intr_cfg_reg); |
| 618 | |
| 619 | clear_bit(d->hwirq, pctrl->enabled_irqs); |
| 620 | |
| 621 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 622 | } |
| 623 | |
| 624 | static void msm_gpio_irq_unmask(struct irq_data *d) |
| 625 | { |
| 626 | const struct msm_pingroup *g; |
| 627 | struct msm_pinctrl *pctrl; |
| 628 | unsigned long flags; |
| 629 | u32 val; |
| 630 | |
| 631 | pctrl = irq_data_get_irq_chip_data(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 632 | g = &pctrl->soc->groups[d->hwirq]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 633 | if (WARN_ON(g->intr_status_reg < 0)) |
| 634 | return; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 635 | |
| 636 | spin_lock_irqsave(&pctrl->lock, flags); |
| 637 | |
| 638 | val = readl(pctrl->regs + g->intr_status_reg); |
| 639 | val &= ~BIT(g->intr_status_bit); |
| 640 | writel(val, pctrl->regs + g->intr_status_reg); |
| 641 | |
| 642 | val = readl(pctrl->regs + g->intr_cfg_reg); |
| 643 | val |= BIT(g->intr_enable_bit); |
| 644 | writel(val, pctrl->regs + g->intr_cfg_reg); |
| 645 | |
| 646 | set_bit(d->hwirq, pctrl->enabled_irqs); |
| 647 | |
| 648 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 649 | } |
| 650 | |
| 651 | static void msm_gpio_irq_ack(struct irq_data *d) |
| 652 | { |
| 653 | const struct msm_pingroup *g; |
| 654 | struct msm_pinctrl *pctrl; |
| 655 | unsigned long flags; |
| 656 | u32 val; |
| 657 | |
| 658 | pctrl = irq_data_get_irq_chip_data(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 659 | g = &pctrl->soc->groups[d->hwirq]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 660 | if (WARN_ON(g->intr_status_reg < 0)) |
| 661 | return; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 662 | |
| 663 | spin_lock_irqsave(&pctrl->lock, flags); |
| 664 | |
| 665 | val = readl(pctrl->regs + g->intr_status_reg); |
| 666 | val &= ~BIT(g->intr_status_bit); |
| 667 | writel(val, pctrl->regs + g->intr_status_reg); |
| 668 | |
| 669 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) |
| 670 | msm_gpio_update_dual_edge_pos(pctrl, g, d); |
| 671 | |
| 672 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 673 | } |
| 674 | |
| 675 | #define INTR_TARGET_PROC_APPS 4 |
| 676 | |
| 677 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
| 678 | { |
| 679 | const struct msm_pingroup *g; |
| 680 | struct msm_pinctrl *pctrl; |
| 681 | unsigned long flags; |
| 682 | u32 val; |
| 683 | |
| 684 | pctrl = irq_data_get_irq_chip_data(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 685 | g = &pctrl->soc->groups[d->hwirq]; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 686 | if (WARN_ON(g->intr_cfg_reg < 0)) |
| 687 | return -EINVAL; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 688 | |
| 689 | spin_lock_irqsave(&pctrl->lock, flags); |
| 690 | |
| 691 | /* |
| 692 | * For hw without possibility of detecting both edges |
| 693 | */ |
| 694 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) |
| 695 | set_bit(d->hwirq, pctrl->dual_edge_irqs); |
| 696 | else |
| 697 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); |
| 698 | |
| 699 | /* Route interrupts to application cpu */ |
| 700 | val = readl(pctrl->regs + g->intr_target_reg); |
| 701 | val &= ~(7 << g->intr_target_bit); |
| 702 | val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; |
| 703 | writel(val, pctrl->regs + g->intr_target_reg); |
| 704 | |
| 705 | /* Update configuration for gpio. |
| 706 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the |
| 707 | * internal circuitry of TLMM, toggling the RAW_STATUS |
| 708 | * could cause the INTR_STATUS to be set for EDGE interrupts. |
| 709 | */ |
| 710 | val = readl(pctrl->regs + g->intr_cfg_reg); |
| 711 | val |= BIT(g->intr_raw_status_bit); |
| 712 | if (g->intr_detection_width == 2) { |
| 713 | val &= ~(3 << g->intr_detection_bit); |
| 714 | val &= ~(1 << g->intr_polarity_bit); |
| 715 | switch (type) { |
| 716 | case IRQ_TYPE_EDGE_RISING: |
| 717 | val |= 1 << g->intr_detection_bit; |
| 718 | val |= BIT(g->intr_polarity_bit); |
| 719 | break; |
| 720 | case IRQ_TYPE_EDGE_FALLING: |
| 721 | val |= 2 << g->intr_detection_bit; |
| 722 | val |= BIT(g->intr_polarity_bit); |
| 723 | break; |
| 724 | case IRQ_TYPE_EDGE_BOTH: |
| 725 | val |= 3 << g->intr_detection_bit; |
| 726 | val |= BIT(g->intr_polarity_bit); |
| 727 | break; |
| 728 | case IRQ_TYPE_LEVEL_LOW: |
| 729 | break; |
| 730 | case IRQ_TYPE_LEVEL_HIGH: |
| 731 | val |= BIT(g->intr_polarity_bit); |
| 732 | break; |
| 733 | } |
| 734 | } else if (g->intr_detection_width == 1) { |
| 735 | val &= ~(1 << g->intr_detection_bit); |
| 736 | val &= ~(1 << g->intr_polarity_bit); |
| 737 | switch (type) { |
| 738 | case IRQ_TYPE_EDGE_RISING: |
| 739 | val |= BIT(g->intr_detection_bit); |
| 740 | val |= BIT(g->intr_polarity_bit); |
| 741 | break; |
| 742 | case IRQ_TYPE_EDGE_FALLING: |
| 743 | val |= BIT(g->intr_detection_bit); |
| 744 | break; |
| 745 | case IRQ_TYPE_EDGE_BOTH: |
| 746 | val |= BIT(g->intr_detection_bit); |
| 747 | break; |
| 748 | case IRQ_TYPE_LEVEL_LOW: |
| 749 | break; |
| 750 | case IRQ_TYPE_LEVEL_HIGH: |
| 751 | val |= BIT(g->intr_polarity_bit); |
| 752 | break; |
| 753 | } |
| 754 | } else { |
| 755 | BUG(); |
| 756 | } |
| 757 | writel(val, pctrl->regs + g->intr_cfg_reg); |
| 758 | |
| 759 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) |
| 760 | msm_gpio_update_dual_edge_pos(pctrl, g, d); |
| 761 | |
| 762 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 763 | |
| 764 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
| 765 | __irq_set_handler_locked(d->irq, handle_level_irq); |
| 766 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 767 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
| 768 | |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
| 773 | { |
| 774 | struct msm_pinctrl *pctrl; |
| 775 | unsigned long flags; |
| 776 | unsigned ngpio; |
| 777 | |
| 778 | pctrl = irq_data_get_irq_chip_data(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 779 | ngpio = pctrl->chip.ngpio; |
| 780 | |
| 781 | spin_lock_irqsave(&pctrl->lock, flags); |
| 782 | |
| 783 | if (on) { |
| 784 | if (bitmap_empty(pctrl->wake_irqs, ngpio)) |
| 785 | enable_irq_wake(pctrl->irq); |
| 786 | set_bit(d->hwirq, pctrl->wake_irqs); |
| 787 | } else { |
| 788 | clear_bit(d->hwirq, pctrl->wake_irqs); |
| 789 | if (bitmap_empty(pctrl->wake_irqs, ngpio)) |
| 790 | disable_irq_wake(pctrl->irq); |
| 791 | } |
| 792 | |
| 793 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 794 | |
| 795 | return 0; |
| 796 | } |
| 797 | |
| 798 | static unsigned int msm_gpio_irq_startup(struct irq_data *d) |
| 799 | { |
| 800 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); |
| 801 | |
| 802 | if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { |
| 803 | dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", |
| 804 | d->hwirq); |
| 805 | } |
| 806 | msm_gpio_irq_unmask(d); |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | static void msm_gpio_irq_shutdown(struct irq_data *d) |
| 811 | { |
| 812 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); |
| 813 | |
| 814 | msm_gpio_irq_mask(d); |
| 815 | gpio_unlock_as_irq(&pctrl->chip, d->hwirq); |
| 816 | } |
| 817 | |
| 818 | static struct irq_chip msm_gpio_irq_chip = { |
| 819 | .name = "msmgpio", |
| 820 | .irq_mask = msm_gpio_irq_mask, |
| 821 | .irq_unmask = msm_gpio_irq_unmask, |
| 822 | .irq_ack = msm_gpio_irq_ack, |
| 823 | .irq_set_type = msm_gpio_irq_set_type, |
| 824 | .irq_set_wake = msm_gpio_irq_set_wake, |
| 825 | .irq_startup = msm_gpio_irq_startup, |
| 826 | .irq_shutdown = msm_gpio_irq_shutdown, |
| 827 | }; |
| 828 | |
| 829 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 830 | { |
| 831 | const struct msm_pingroup *g; |
| 832 | struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc); |
| 833 | struct irq_chip *chip = irq_get_chip(irq); |
| 834 | int irq_pin; |
| 835 | int handled = 0; |
| 836 | u32 val; |
| 837 | int i; |
| 838 | |
| 839 | chained_irq_enter(chip, desc); |
| 840 | |
| 841 | /* |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 842 | * Each pin has it's own IRQ status register, so use |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 843 | * enabled_irq bitmap to limit the number of reads. |
| 844 | */ |
| 845 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { |
| 846 | g = &pctrl->soc->groups[i]; |
| 847 | val = readl(pctrl->regs + g->intr_status_reg); |
| 848 | if (val & BIT(g->intr_status_bit)) { |
| 849 | irq_pin = irq_find_mapping(pctrl->domain, i); |
| 850 | generic_handle_irq(irq_pin); |
| 851 | handled++; |
| 852 | } |
| 853 | } |
| 854 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 855 | /* No interrupts were flagged */ |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 856 | if (handled == 0) |
| 857 | handle_bad_irq(irq, desc); |
| 858 | |
| 859 | chained_irq_exit(chip, desc); |
| 860 | } |
| 861 | |
| 862 | static int msm_gpio_init(struct msm_pinctrl *pctrl) |
| 863 | { |
| 864 | struct gpio_chip *chip; |
| 865 | int irq; |
| 866 | int ret; |
| 867 | int i; |
| 868 | int r; |
| 869 | |
| 870 | chip = &pctrl->chip; |
| 871 | chip->base = 0; |
| 872 | chip->ngpio = pctrl->soc->ngpios; |
| 873 | chip->label = dev_name(pctrl->dev); |
| 874 | chip->dev = pctrl->dev; |
| 875 | chip->owner = THIS_MODULE; |
| 876 | chip->of_node = pctrl->dev->of_node; |
| 877 | |
| 878 | pctrl->enabled_irqs = devm_kzalloc(pctrl->dev, |
| 879 | sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio), |
| 880 | GFP_KERNEL); |
| 881 | if (!pctrl->enabled_irqs) { |
| 882 | dev_err(pctrl->dev, "Failed to allocate enabled_irqs bitmap\n"); |
| 883 | return -ENOMEM; |
| 884 | } |
| 885 | |
| 886 | pctrl->dual_edge_irqs = devm_kzalloc(pctrl->dev, |
| 887 | sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio), |
| 888 | GFP_KERNEL); |
| 889 | if (!pctrl->dual_edge_irqs) { |
| 890 | dev_err(pctrl->dev, "Failed to allocate dual_edge_irqs bitmap\n"); |
| 891 | return -ENOMEM; |
| 892 | } |
| 893 | |
| 894 | pctrl->wake_irqs = devm_kzalloc(pctrl->dev, |
| 895 | sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio), |
| 896 | GFP_KERNEL); |
| 897 | if (!pctrl->wake_irqs) { |
| 898 | dev_err(pctrl->dev, "Failed to allocate wake_irqs bitmap\n"); |
| 899 | return -ENOMEM; |
| 900 | } |
| 901 | |
| 902 | ret = gpiochip_add(&pctrl->chip); |
| 903 | if (ret) { |
| 904 | dev_err(pctrl->dev, "Failed register gpiochip\n"); |
| 905 | return ret; |
| 906 | } |
| 907 | |
| 908 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); |
| 909 | if (ret) { |
| 910 | dev_err(pctrl->dev, "Failed to add pin range\n"); |
| 911 | return ret; |
| 912 | } |
| 913 | |
| 914 | pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio, |
| 915 | &irq_domain_simple_ops, NULL); |
| 916 | if (!pctrl->domain) { |
| 917 | dev_err(pctrl->dev, "Failed to register irq domain\n"); |
| 918 | r = gpiochip_remove(&pctrl->chip); |
| 919 | return -ENOSYS; |
| 920 | } |
| 921 | |
| 922 | for (i = 0; i < chip->ngpio; i++) { |
| 923 | irq = irq_create_mapping(pctrl->domain, i); |
| 924 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq); |
| 925 | irq_set_chip_data(irq, pctrl); |
| 926 | } |
| 927 | |
| 928 | irq_set_handler_data(pctrl->irq, pctrl); |
| 929 | irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler); |
| 930 | |
| 931 | return 0; |
| 932 | } |
| 933 | |
| 934 | int msm_pinctrl_probe(struct platform_device *pdev, |
| 935 | const struct msm_pinctrl_soc_data *soc_data) |
| 936 | { |
| 937 | struct msm_pinctrl *pctrl; |
| 938 | struct resource *res; |
| 939 | int ret; |
| 940 | |
| 941 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); |
| 942 | if (!pctrl) { |
| 943 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); |
| 944 | return -ENOMEM; |
| 945 | } |
| 946 | pctrl->dev = &pdev->dev; |
| 947 | pctrl->soc = soc_data; |
| 948 | pctrl->chip = msm_gpio_template; |
| 949 | |
| 950 | spin_lock_init(&pctrl->lock); |
| 951 | |
| 952 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 953 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); |
| 954 | if (IS_ERR(pctrl->regs)) |
| 955 | return PTR_ERR(pctrl->regs); |
| 956 | |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 957 | pctrl->irq = platform_get_irq(pdev, 0); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 958 | if (pctrl->irq < 0) { |
| 959 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); |
| 960 | return pctrl->irq; |
| 961 | } |
| 962 | |
| 963 | msm_pinctrl_desc.name = dev_name(&pdev->dev); |
| 964 | msm_pinctrl_desc.pins = pctrl->soc->pins; |
| 965 | msm_pinctrl_desc.npins = pctrl->soc->npins; |
| 966 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); |
| 967 | if (!pctrl->pctrl) { |
| 968 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
| 969 | return -ENODEV; |
| 970 | } |
| 971 | |
| 972 | ret = msm_gpio_init(pctrl); |
| 973 | if (ret) { |
| 974 | pinctrl_unregister(pctrl->pctrl); |
| 975 | return ret; |
| 976 | } |
| 977 | |
| 978 | platform_set_drvdata(pdev, pctrl); |
| 979 | |
| 980 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); |
| 981 | |
| 982 | return 0; |
| 983 | } |
| 984 | EXPORT_SYMBOL(msm_pinctrl_probe); |
| 985 | |
| 986 | int msm_pinctrl_remove(struct platform_device *pdev) |
| 987 | { |
| 988 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 989 | int ret; |
| 990 | |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame^] | 991 | ret = gpiochip_remove(&pctrl->chip); |
| 992 | if (ret) { |
| 993 | dev_err(&pdev->dev, "Failed to remove gpiochip\n"); |
| 994 | return ret; |
| 995 | } |
| 996 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 997 | irq_set_chained_handler(pctrl->irq, NULL); |
| 998 | irq_domain_remove(pctrl->domain); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 999 | pinctrl_unregister(pctrl->pctrl); |
| 1000 | |
| 1001 | return 0; |
| 1002 | } |
| 1003 | EXPORT_SYMBOL(msm_pinctrl_remove); |
| 1004 | |