| Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2008 |
| 3 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> |
| 4 | * |
| 5 | * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef _IPU_INTERN_H_ |
| 13 | #define _IPU_INTERN_H_ |
| 14 | |
| 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | |
| 19 | /* IPU Common registers */ |
| 20 | #define IPU_CONF 0x00 |
| 21 | #define IPU_CHA_BUF0_RDY 0x04 |
| 22 | #define IPU_CHA_BUF1_RDY 0x08 |
| 23 | #define IPU_CHA_DB_MODE_SEL 0x0C |
| 24 | #define IPU_CHA_CUR_BUF 0x10 |
| 25 | #define IPU_FS_PROC_FLOW 0x14 |
| 26 | #define IPU_FS_DISP_FLOW 0x18 |
| 27 | #define IPU_TASKS_STAT 0x1C |
| 28 | #define IPU_IMA_ADDR 0x20 |
| 29 | #define IPU_IMA_DATA 0x24 |
| 30 | #define IPU_INT_CTRL_1 0x28 |
| 31 | #define IPU_INT_CTRL_2 0x2C |
| 32 | #define IPU_INT_CTRL_3 0x30 |
| 33 | #define IPU_INT_CTRL_4 0x34 |
| 34 | #define IPU_INT_CTRL_5 0x38 |
| 35 | #define IPU_INT_STAT_1 0x3C |
| 36 | #define IPU_INT_STAT_2 0x40 |
| 37 | #define IPU_INT_STAT_3 0x44 |
| 38 | #define IPU_INT_STAT_4 0x48 |
| 39 | #define IPU_INT_STAT_5 0x4C |
| 40 | #define IPU_BRK_CTRL_1 0x50 |
| 41 | #define IPU_BRK_CTRL_2 0x54 |
| 42 | #define IPU_BRK_STAT 0x58 |
| 43 | #define IPU_DIAGB_CTRL 0x5C |
| 44 | |
| 45 | /* IPU_CONF Register bits */ |
| 46 | #define IPU_CONF_CSI_EN 0x00000001 |
| 47 | #define IPU_CONF_IC_EN 0x00000002 |
| 48 | #define IPU_CONF_ROT_EN 0x00000004 |
| 49 | #define IPU_CONF_PF_EN 0x00000008 |
| 50 | #define IPU_CONF_SDC_EN 0x00000010 |
| 51 | #define IPU_CONF_ADC_EN 0x00000020 |
| 52 | #define IPU_CONF_DI_EN 0x00000040 |
| 53 | #define IPU_CONF_DU_EN 0x00000080 |
| 54 | #define IPU_CONF_PXL_ENDIAN 0x00000100 |
| 55 | |
| 56 | /* Image Converter Registers */ |
| 57 | #define IC_CONF 0x88 |
| 58 | #define IC_PRP_ENC_RSC 0x8C |
| 59 | #define IC_PRP_VF_RSC 0x90 |
| 60 | #define IC_PP_RSC 0x94 |
| 61 | #define IC_CMBP_1 0x98 |
| 62 | #define IC_CMBP_2 0x9C |
| 63 | #define PF_CONF 0xA0 |
| 64 | #define IDMAC_CONF 0xA4 |
| 65 | #define IDMAC_CHA_EN 0xA8 |
| 66 | #define IDMAC_CHA_PRI 0xAC |
| 67 | #define IDMAC_CHA_BUSY 0xB0 |
| 68 | |
| 69 | /* Image Converter Register bits */ |
| 70 | #define IC_CONF_PRPENC_EN 0x00000001 |
| 71 | #define IC_CONF_PRPENC_CSC1 0x00000002 |
| 72 | #define IC_CONF_PRPENC_ROT_EN 0x00000004 |
| 73 | #define IC_CONF_PRPVF_EN 0x00000100 |
| 74 | #define IC_CONF_PRPVF_CSC1 0x00000200 |
| 75 | #define IC_CONF_PRPVF_CSC2 0x00000400 |
| 76 | #define IC_CONF_PRPVF_CMB 0x00000800 |
| 77 | #define IC_CONF_PRPVF_ROT_EN 0x00001000 |
| 78 | #define IC_CONF_PP_EN 0x00010000 |
| 79 | #define IC_CONF_PP_CSC1 0x00020000 |
| 80 | #define IC_CONF_PP_CSC2 0x00040000 |
| 81 | #define IC_CONF_PP_CMB 0x00080000 |
| 82 | #define IC_CONF_PP_ROT_EN 0x00100000 |
| 83 | #define IC_CONF_IC_GLB_LOC_A 0x10000000 |
| 84 | #define IC_CONF_KEY_COLOR_EN 0x20000000 |
| 85 | #define IC_CONF_RWS_EN 0x40000000 |
| 86 | #define IC_CONF_CSI_MEM_WR_EN 0x80000000 |
| 87 | |
| 88 | #define IDMA_CHAN_INVALID 0x000000FF |
| 89 | #define IDMA_IC_0 0x00000001 |
| 90 | #define IDMA_IC_1 0x00000002 |
| 91 | #define IDMA_IC_2 0x00000004 |
| 92 | #define IDMA_IC_3 0x00000008 |
| 93 | #define IDMA_IC_4 0x00000010 |
| 94 | #define IDMA_IC_5 0x00000020 |
| 95 | #define IDMA_IC_6 0x00000040 |
| 96 | #define IDMA_IC_7 0x00000080 |
| 97 | #define IDMA_IC_8 0x00000100 |
| 98 | #define IDMA_IC_9 0x00000200 |
| 99 | #define IDMA_IC_10 0x00000400 |
| 100 | #define IDMA_IC_11 0x00000800 |
| 101 | #define IDMA_IC_12 0x00001000 |
| 102 | #define IDMA_IC_13 0x00002000 |
| 103 | #define IDMA_SDC_BG 0x00004000 |
| 104 | #define IDMA_SDC_FG 0x00008000 |
| 105 | #define IDMA_SDC_MASK 0x00010000 |
| 106 | #define IDMA_SDC_PARTIAL 0x00020000 |
| 107 | #define IDMA_ADC_SYS1_WR 0x00040000 |
| 108 | #define IDMA_ADC_SYS2_WR 0x00080000 |
| 109 | #define IDMA_ADC_SYS1_CMD 0x00100000 |
| 110 | #define IDMA_ADC_SYS2_CMD 0x00200000 |
| 111 | #define IDMA_ADC_SYS1_RD 0x00400000 |
| 112 | #define IDMA_ADC_SYS2_RD 0x00800000 |
| 113 | #define IDMA_PF_QP 0x01000000 |
| 114 | #define IDMA_PF_BSP 0x02000000 |
| 115 | #define IDMA_PF_Y_IN 0x04000000 |
| 116 | #define IDMA_PF_U_IN 0x08000000 |
| 117 | #define IDMA_PF_V_IN 0x10000000 |
| 118 | #define IDMA_PF_Y_OUT 0x20000000 |
| 119 | #define IDMA_PF_U_OUT 0x40000000 |
| 120 | #define IDMA_PF_V_OUT 0x80000000 |
| 121 | |
| 122 | #define TSTAT_PF_H264_PAUSE 0x00000001 |
| 123 | #define TSTAT_CSI2MEM_MASK 0x0000000C |
| 124 | #define TSTAT_CSI2MEM_OFFSET 2 |
| 125 | #define TSTAT_VF_MASK 0x00000600 |
| 126 | #define TSTAT_VF_OFFSET 9 |
| 127 | #define TSTAT_VF_ROT_MASK 0x000C0000 |
| 128 | #define TSTAT_VF_ROT_OFFSET 18 |
| 129 | #define TSTAT_ENC_MASK 0x00000180 |
| 130 | #define TSTAT_ENC_OFFSET 7 |
| 131 | #define TSTAT_ENC_ROT_MASK 0x00030000 |
| 132 | #define TSTAT_ENC_ROT_OFFSET 16 |
| 133 | #define TSTAT_PP_MASK 0x00001800 |
| 134 | #define TSTAT_PP_OFFSET 11 |
| 135 | #define TSTAT_PP_ROT_MASK 0x00300000 |
| 136 | #define TSTAT_PP_ROT_OFFSET 20 |
| 137 | #define TSTAT_PF_MASK 0x00C00000 |
| 138 | #define TSTAT_PF_OFFSET 22 |
| 139 | #define TSTAT_ADCSYS1_MASK 0x03000000 |
| 140 | #define TSTAT_ADCSYS1_OFFSET 24 |
| 141 | #define TSTAT_ADCSYS2_MASK 0x0C000000 |
| 142 | #define TSTAT_ADCSYS2_OFFSET 26 |
| 143 | |
| 144 | #define TASK_STAT_IDLE 0 |
| 145 | #define TASK_STAT_ACTIVE 1 |
| 146 | #define TASK_STAT_WAIT4READY 2 |
| 147 | |
| 148 | struct idmac { |
| 149 | struct dma_device dma; |
| 150 | }; |
| 151 | |
| 152 | struct ipu { |
| 153 | void __iomem *reg_ipu; |
| 154 | void __iomem *reg_ic; |
| 155 | unsigned int irq_fn; /* IPU Function IRQ to the CPU */ |
| 156 | unsigned int irq_err; /* IPU Error IRQ to the CPU */ |
| 157 | unsigned int irq_base; /* Beginning of the IPU IRQ range */ |
| 158 | unsigned long channel_init_mask; |
| 159 | spinlock_t lock; |
| 160 | struct clk *ipu_clk; |
| 161 | struct device *dev; |
| 162 | struct idmac idmac; |
| 163 | struct idmac_channel channel[IPU_CHANNELS_NUM]; |
| 164 | struct tasklet_struct tasklet; |
| 165 | }; |
| 166 | |
| 167 | #define to_idmac(d) container_of(d, struct idmac, dma) |
| 168 | |
| 169 | extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev); |
| 170 | extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev); |
| 171 | |
| 172 | extern bool ipu_irq_status(uint32_t irq); |
| 173 | extern int ipu_irq_map(unsigned int source); |
| 174 | extern int ipu_irq_unmap(unsigned int source); |
| 175 | |
| 176 | #endif |