Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Machine check handler. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 3 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 5 | * Rest from unknown author(s). |
| 6 | * 2004 Andi Kleen. Rewrote most of it. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 7 | * Copyright 2008 Intel Corporation |
| 8 | * Author: Andi Kleen |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | */ |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 10 | #include <linux/thread_info.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 11 | #include <linux/capability.h> |
| 12 | #include <linux/miscdevice.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 13 | #include <linux/interrupt.h> |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 14 | #include <linux/ratelimit.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 15 | #include <linux/kallsyms.h> |
| 16 | #include <linux/rcupdate.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 17 | #include <linux/kobject.h> |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 18 | #include <linux/uaccess.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 19 | #include <linux/kdebug.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/percpu.h> |
| 22 | #include <linux/string.h> |
| 23 | #include <linux/sysdev.h> |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 24 | #include <linux/delay.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 25 | #include <linux/ctype.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/sysfs.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/kmod.h> |
| 31 | #include <linux/poll.h> |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 32 | #include <linux/nmi.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 33 | #include <linux/cpu.h> |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 34 | #include <linux/smp.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 35 | #include <linux/fs.h> |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 36 | #include <linux/mm.h> |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 37 | #include <linux/debugfs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 39 | #include <asm/processor.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 40 | #include <asm/hw_irq.h> |
| 41 | #include <asm/apic.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 42 | #include <asm/idle.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 43 | #include <asm/ipi.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 44 | #include <asm/mce.h> |
| 45 | #include <asm/msr.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 46 | |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 47 | #include "mce-internal.h" |
Ingo Molnar | 711c2e4 | 2009-04-08 12:31:26 +0200 | [diff] [blame] | 48 | |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 49 | int mce_disabled __read_mostly; |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 50 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 51 | #define MISC_MCELOG_MINOR 227 |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 52 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 53 | #define SPINUNIT 100 /* 100ns */ |
| 54 | |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 55 | atomic_t mce_entry; |
| 56 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 57 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
| 58 | |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 59 | /* |
| 60 | * Tolerant levels: |
| 61 | * 0: always panic on uncorrected errors, log corrected errors |
| 62 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors |
| 63 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors |
| 64 | * 3: never panic or SIGBUS, log all errors (for testing only) |
| 65 | */ |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 66 | static int tolerant __read_mostly = 1; |
| 67 | static int banks __read_mostly; |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 68 | static int rip_msr __read_mostly; |
| 69 | static int mce_bootlog __read_mostly = -1; |
| 70 | static int monarch_timeout __read_mostly = -1; |
| 71 | static int mce_panic_timeout __read_mostly; |
| 72 | static int mce_dont_log_ce __read_mostly; |
| 73 | int mce_cmci_disabled __read_mostly; |
| 74 | int mce_ignore_ce __read_mostly; |
| 75 | int mce_ser __read_mostly; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 76 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 77 | struct mce_bank *mce_banks __read_mostly; |
| 78 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 79 | /* User mode helper program triggered by machine check event */ |
| 80 | static unsigned long mce_need_notify; |
| 81 | static char mce_helper[128]; |
| 82 | static char *mce_helper_argv[2] = { mce_helper, NULL }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 84 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 85 | static DEFINE_PER_CPU(struct mce, mces_seen); |
| 86 | static int cpu_missing; |
| 87 | |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 88 | static void default_decode_mce(struct mce *m) |
| 89 | { |
| 90 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); |
| 91 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * CPU/chipset specific EDAC code can register a callback here to print |
| 96 | * MCE errors in a human-readable form: |
| 97 | */ |
| 98 | void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce; |
| 99 | EXPORT_SYMBOL(x86_mce_decode_callback); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 100 | |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 101 | /* MCA banks polled by the period polling timer for corrected events */ |
| 102 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
| 103 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL |
| 104 | }; |
| 105 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 106 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
| 107 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 108 | /* Do initial initialization of a struct mce */ |
| 109 | void mce_setup(struct mce *m) |
| 110 | { |
| 111 | memset(m, 0, sizeof(struct mce)); |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 112 | m->cpu = m->extcpu = smp_processor_id(); |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 113 | rdtscll(m->tsc); |
Andi Kleen | 8ee0834 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 114 | /* We hope get_seconds stays lockless */ |
| 115 | m->time = get_seconds(); |
| 116 | m->cpuvendor = boot_cpu_data.x86_vendor; |
| 117 | m->cpuid = cpuid_eax(1); |
| 118 | #ifdef CONFIG_SMP |
| 119 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
| 120 | #endif |
| 121 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
| 122 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 125 | DEFINE_PER_CPU(struct mce, injectm); |
| 126 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); |
| 127 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | /* |
| 129 | * Lockless MCE logging infrastructure. |
| 130 | * This avoids deadlocks on printk locks without having to break locks. Also |
| 131 | * separate MCEs from kernel messages to avoid bogus bug reports. |
| 132 | */ |
| 133 | |
Adrian Bunk | 231fd90 | 2008-01-30 13:30:30 +0100 | [diff] [blame] | 134 | static struct mce_log mcelog = { |
Andi Kleen | f6fb0ac | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 135 | .signature = MCE_LOG_SIGNATURE, |
| 136 | .len = MCE_LOG_LEN, |
| 137 | .recordlen = sizeof(struct mce), |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 138 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | |
| 140 | void mce_log(struct mce *mce) |
| 141 | { |
| 142 | unsigned next, entry; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 143 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | mce->finished = 0; |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 145 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | for (;;) { |
| 147 | entry = rcu_dereference(mcelog.next); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 148 | for (;;) { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 149 | /* |
| 150 | * When the buffer fills up discard new entries. |
| 151 | * Assume that the earlier errors are the more |
| 152 | * interesting ones: |
| 153 | */ |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 154 | if (entry >= MCE_LOG_LEN) { |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 155 | set_bit(MCE_OVERFLOW, |
| 156 | (unsigned long *)&mcelog.flags); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 157 | return; |
| 158 | } |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 159 | /* Old left over entry. Skip: */ |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 160 | if (mcelog.entry[entry].finished) { |
| 161 | entry++; |
| 162 | continue; |
| 163 | } |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 164 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | smp_rmb(); |
| 167 | next = entry + 1; |
| 168 | if (cmpxchg(&mcelog.next, entry, next) == entry) |
| 169 | break; |
| 170 | } |
| 171 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 172 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | mcelog.entry[entry].finished = 1; |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 174 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 176 | mce->finished = 1; |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 177 | set_bit(0, &mce_need_notify); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | } |
| 179 | |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 180 | static void print_mce(struct mce *m) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 182 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 183 | m->extcpu, m->mcgstatus, m->bank, m->status); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 184 | |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 185 | if (m->ip) { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 186 | pr_emerg("RIP%s %02x:<%016Lx> ", |
| 187 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
| 188 | m->cs, m->ip); |
| 189 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | if (m->cs == __KERNEL_CS) |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 191 | print_symbol("{%s}", m->ip); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 192 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | } |
Borislav Petkov | 549d042 | 2009-07-24 13:51:42 +0200 | [diff] [blame] | 194 | |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 195 | pr_emerg("TSC %llx ", m->tsc); |
| 196 | if (m->addr) |
| 197 | pr_cont("ADDR %llx ", m->addr); |
| 198 | if (m->misc) |
| 199 | pr_cont("MISC %llx ", m->misc); |
| 200 | |
| 201 | pr_cont("\n"); |
| 202 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
| 203 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); |
| 204 | |
| 205 | /* |
| 206 | * Print out human-readable details about the MCE error, |
| 207 | * (if the CPU has an implementation for that): |
| 208 | */ |
| 209 | x86_mce_decode_callback(m); |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 210 | } |
| 211 | |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 212 | static void print_mce_head(void) |
| 213 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 214 | pr_emerg("\nHARDWARE ERROR\n"); |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 215 | } |
| 216 | |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 217 | static void print_mce_tail(void) |
| 218 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 219 | pr_emerg("This is not a software problem!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 222 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
| 223 | |
| 224 | static atomic_t mce_paniced; |
| 225 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 226 | static int fake_panic; |
| 227 | static atomic_t mce_fake_paniced; |
| 228 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 229 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
| 230 | static void wait_for_panic(void) |
| 231 | { |
| 232 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 233 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 234 | preempt_disable(); |
| 235 | local_irq_enable(); |
| 236 | while (timeout-- > 0) |
| 237 | udelay(1); |
Andi Kleen | 29b0f59 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 238 | if (panic_timeout == 0) |
| 239 | panic_timeout = mce_panic_timeout; |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 240 | panic("Panicing machine check CPU died"); |
| 241 | } |
| 242 | |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 243 | static void mce_panic(char *msg, struct mce *final, char *exp) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 244 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | int i; |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 246 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 247 | if (!fake_panic) { |
| 248 | /* |
| 249 | * Make sure only one CPU runs in machine check panic |
| 250 | */ |
| 251 | if (atomic_inc_return(&mce_paniced) > 1) |
| 252 | wait_for_panic(); |
| 253 | barrier(); |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 254 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 255 | bust_spinlocks(1); |
| 256 | console_verbose(); |
| 257 | } else { |
| 258 | /* Don't log too much for fake panic */ |
| 259 | if (atomic_inc_return(&mce_fake_paniced) > 1) |
| 260 | return; |
| 261 | } |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 262 | print_mce_head(); |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 263 | /* First print corrected ones that are still unlogged */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | for (i = 0; i < MCE_LOG_LEN; i++) { |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 265 | struct mce *m = &mcelog.entry[i]; |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 266 | if (!(m->status & MCI_STATUS_VAL)) |
| 267 | continue; |
| 268 | if (!(m->status & MCI_STATUS_UC)) |
| 269 | print_mce(m); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | } |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 271 | /* Now print uncorrected but with the final one last */ |
| 272 | for (i = 0; i < MCE_LOG_LEN; i++) { |
| 273 | struct mce *m = &mcelog.entry[i]; |
| 274 | if (!(m->status & MCI_STATUS_VAL)) |
| 275 | continue; |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 276 | if (!(m->status & MCI_STATUS_UC)) |
| 277 | continue; |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 278 | if (!final || memcmp(m, final, sizeof(struct mce))) |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 279 | print_mce(m); |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 280 | } |
| 281 | if (final) |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 282 | print_mce(final); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 283 | if (cpu_missing) |
| 284 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 285 | print_mce_tail(); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 286 | if (exp) |
| 287 | printk(KERN_EMERG "Machine check: %s\n", exp); |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 288 | if (!fake_panic) { |
| 289 | if (panic_timeout == 0) |
| 290 | panic_timeout = mce_panic_timeout; |
| 291 | panic(msg); |
| 292 | } else |
| 293 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 294 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 296 | /* Support code for software error injection */ |
| 297 | |
| 298 | static int msr_to_offset(u32 msr) |
| 299 | { |
| 300 | unsigned bank = __get_cpu_var(injectm.bank); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame^] | 301 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 302 | if (msr == rip_msr) |
| 303 | return offsetof(struct mce, ip); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 304 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 305 | return offsetof(struct mce, status); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 306 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 307 | return offsetof(struct mce, addr); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 308 | if (msr == MSR_IA32_MCx_MISC(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 309 | return offsetof(struct mce, misc); |
| 310 | if (msr == MSR_IA32_MCG_STATUS) |
| 311 | return offsetof(struct mce, mcgstatus); |
| 312 | return -1; |
| 313 | } |
| 314 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 315 | /* MSR access wrappers used for error injection */ |
| 316 | static u64 mce_rdmsrl(u32 msr) |
| 317 | { |
| 318 | u64 v; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 319 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 320 | if (__get_cpu_var(injectm).finished) { |
| 321 | int offset = msr_to_offset(msr); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 322 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 323 | if (offset < 0) |
| 324 | return 0; |
| 325 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); |
| 326 | } |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 327 | |
| 328 | if (rdmsrl_safe(msr, &v)) { |
| 329 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); |
| 330 | /* |
| 331 | * Return zero in case the access faulted. This should |
| 332 | * not happen normally but can happen if the CPU does |
| 333 | * something weird, or if the code is buggy. |
| 334 | */ |
| 335 | v = 0; |
| 336 | } |
| 337 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 338 | return v; |
| 339 | } |
| 340 | |
| 341 | static void mce_wrmsrl(u32 msr, u64 v) |
| 342 | { |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 343 | if (__get_cpu_var(injectm).finished) { |
| 344 | int offset = msr_to_offset(msr); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 345 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 346 | if (offset >= 0) |
| 347 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; |
| 348 | return; |
| 349 | } |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 350 | wrmsrl(msr, v); |
| 351 | } |
| 352 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 353 | /* |
| 354 | * Simple lockless ring to communicate PFNs from the exception handler with the |
| 355 | * process context work function. This is vastly simplified because there's |
| 356 | * only a single reader and a single writer. |
| 357 | */ |
| 358 | #define MCE_RING_SIZE 16 /* we use one entry less */ |
| 359 | |
| 360 | struct mce_ring { |
| 361 | unsigned short start; |
| 362 | unsigned short end; |
| 363 | unsigned long ring[MCE_RING_SIZE]; |
| 364 | }; |
| 365 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); |
| 366 | |
| 367 | /* Runs with CPU affinity in workqueue */ |
| 368 | static int mce_ring_empty(void) |
| 369 | { |
| 370 | struct mce_ring *r = &__get_cpu_var(mce_ring); |
| 371 | |
| 372 | return r->start == r->end; |
| 373 | } |
| 374 | |
| 375 | static int mce_ring_get(unsigned long *pfn) |
| 376 | { |
| 377 | struct mce_ring *r; |
| 378 | int ret = 0; |
| 379 | |
| 380 | *pfn = 0; |
| 381 | get_cpu(); |
| 382 | r = &__get_cpu_var(mce_ring); |
| 383 | if (r->start == r->end) |
| 384 | goto out; |
| 385 | *pfn = r->ring[r->start]; |
| 386 | r->start = (r->start + 1) % MCE_RING_SIZE; |
| 387 | ret = 1; |
| 388 | out: |
| 389 | put_cpu(); |
| 390 | return ret; |
| 391 | } |
| 392 | |
| 393 | /* Always runs in MCE context with preempt off */ |
| 394 | static int mce_ring_add(unsigned long pfn) |
| 395 | { |
| 396 | struct mce_ring *r = &__get_cpu_var(mce_ring); |
| 397 | unsigned next; |
| 398 | |
| 399 | next = (r->end + 1) % MCE_RING_SIZE; |
| 400 | if (next == r->start) |
| 401 | return -1; |
| 402 | r->ring[r->end] = pfn; |
| 403 | wmb(); |
| 404 | r->end = next; |
| 405 | return 0; |
| 406 | } |
| 407 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 408 | int mce_available(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | { |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 410 | if (mce_disabled) |
Andi Kleen | 5b4408f | 2009-02-12 13:39:30 +0100 | [diff] [blame] | 411 | return 0; |
Akinobu Mita | 3d1712c | 2006-03-24 03:15:11 -0800 | [diff] [blame] | 412 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | } |
| 414 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 415 | static void mce_schedule_work(void) |
| 416 | { |
| 417 | if (!mce_ring_empty()) { |
| 418 | struct work_struct *work = &__get_cpu_var(mce_work); |
| 419 | if (!work_pending(work)) |
| 420 | schedule_work(work); |
| 421 | } |
| 422 | } |
| 423 | |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 424 | /* |
| 425 | * Get the address of the instruction at the time of the machine check |
| 426 | * error. |
| 427 | */ |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 428 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
| 429 | { |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 430 | |
| 431 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 432 | m->ip = regs->ip; |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 433 | m->cs = regs->cs; |
| 434 | } else { |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 435 | m->ip = 0; |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 436 | m->cs = 0; |
| 437 | } |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 438 | if (rip_msr) |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 439 | m->ip = mce_rdmsrl(rip_msr); |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 440 | } |
| 441 | |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 442 | #ifdef CONFIG_X86_LOCAL_APIC |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 443 | /* |
| 444 | * Called after interrupts have been reenabled again |
| 445 | * when a MCE happened during an interrupts off region |
| 446 | * in the kernel. |
| 447 | */ |
| 448 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) |
| 449 | { |
| 450 | ack_APIC_irq(); |
| 451 | exit_idle(); |
| 452 | irq_enter(); |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 453 | mce_notify_irq(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 454 | mce_schedule_work(); |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 455 | irq_exit(); |
| 456 | } |
| 457 | #endif |
| 458 | |
| 459 | static void mce_report_event(struct pt_regs *regs) |
| 460 | { |
| 461 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 462 | mce_notify_irq(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 463 | /* |
| 464 | * Triggering the work queue here is just an insurance |
| 465 | * policy in case the syscall exit notify handler |
| 466 | * doesn't run soon enough or ends up running on the |
| 467 | * wrong CPU (can happen when audit sleeps) |
| 468 | */ |
| 469 | mce_schedule_work(); |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 470 | return; |
| 471 | } |
| 472 | |
| 473 | #ifdef CONFIG_X86_LOCAL_APIC |
| 474 | /* |
| 475 | * Without APIC do not notify. The event will be picked |
| 476 | * up eventually. |
| 477 | */ |
| 478 | if (!cpu_has_apic) |
| 479 | return; |
| 480 | |
| 481 | /* |
| 482 | * When interrupts are disabled we cannot use |
| 483 | * kernel services safely. Trigger an self interrupt |
| 484 | * through the APIC to instead do the notification |
| 485 | * after interrupts are reenabled again. |
| 486 | */ |
| 487 | apic->send_IPI_self(MCE_SELF_VECTOR); |
| 488 | |
| 489 | /* |
| 490 | * Wait for idle afterwards again so that we don't leave the |
| 491 | * APIC in a non idle state because the normal APIC writes |
| 492 | * cannot exclude us. |
| 493 | */ |
| 494 | apic_wait_icr_idle(); |
| 495 | #endif |
| 496 | } |
| 497 | |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 498 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
| 499 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 500 | /* |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 501 | * Poll for corrected events or events that happened before reset. |
| 502 | * Those are just logged through /dev/mcelog. |
| 503 | * |
| 504 | * This is executed in standard interrupt context. |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 505 | * |
| 506 | * Note: spec recommends to panic for fatal unsignalled |
| 507 | * errors here. However this would be quite problematic -- |
| 508 | * we would need to reimplement the Monarch handling and |
| 509 | * it would mess up the exclusion between exception handler |
| 510 | * and poll hander -- * so we skip this for now. |
| 511 | * These cases should not happen anyways, or only when the CPU |
| 512 | * is already totally * confused. In this case it's likely it will |
| 513 | * not fully execute the machine check handler either. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 514 | */ |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 515 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 516 | { |
| 517 | struct mce m; |
| 518 | int i; |
| 519 | |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 520 | __get_cpu_var(mce_poll_count)++; |
| 521 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 522 | mce_setup(&m); |
| 523 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 524 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 525 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 526 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 527 | continue; |
| 528 | |
| 529 | m.misc = 0; |
| 530 | m.addr = 0; |
| 531 | m.bank = i; |
| 532 | m.tsc = 0; |
| 533 | |
| 534 | barrier(); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 535 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 536 | if (!(m.status & MCI_STATUS_VAL)) |
| 537 | continue; |
| 538 | |
| 539 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 540 | * Uncorrected or signalled events are handled by the exception |
| 541 | * handler when it is enabled, so don't process those here. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 542 | * |
| 543 | * TBD do the same check for MCI_STATUS_EN here? |
| 544 | */ |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 545 | if (!(flags & MCP_UC) && |
| 546 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 547 | continue; |
| 548 | |
| 549 | if (m.status & MCI_STATUS_MISCV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 550 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 551 | if (m.status & MCI_STATUS_ADDRV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 552 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 553 | |
| 554 | if (!(flags & MCP_TIMESTAMP)) |
| 555 | m.tsc = 0; |
| 556 | /* |
| 557 | * Don't get the IP here because it's unlikely to |
| 558 | * have anything to do with the actual error location. |
| 559 | */ |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 560 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 561 | mce_log(&m); |
| 562 | add_taint(TAINT_MACHINE_CHECK); |
| 563 | } |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 564 | |
| 565 | /* |
| 566 | * Clear state for this bank. |
| 567 | */ |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 568 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | /* |
| 572 | * Don't clear MCG_STATUS here because it's only defined for |
| 573 | * exceptions. |
| 574 | */ |
Andi Kleen | 88921be | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 575 | |
| 576 | sync_core(); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 577 | } |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 578 | EXPORT_SYMBOL_GPL(machine_check_poll); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 579 | |
| 580 | /* |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 581 | * Do a quick check if any of the events requires a panic. |
| 582 | * This decides if we keep the events around or clear them. |
| 583 | */ |
| 584 | static int mce_no_way_out(struct mce *m, char **msg) |
| 585 | { |
| 586 | int i; |
| 587 | |
| 588 | for (i = 0; i < banks; i++) { |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 589 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 590 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
| 591 | return 1; |
| 592 | } |
| 593 | return 0; |
| 594 | } |
| 595 | |
| 596 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 597 | * Variable to establish order between CPUs while scanning. |
| 598 | * Each CPU spins initially until executing is equal its number. |
| 599 | */ |
| 600 | static atomic_t mce_executing; |
| 601 | |
| 602 | /* |
| 603 | * Defines order of CPUs on entry. First CPU becomes Monarch. |
| 604 | */ |
| 605 | static atomic_t mce_callin; |
| 606 | |
| 607 | /* |
| 608 | * Check if a timeout waiting for other CPUs happened. |
| 609 | */ |
| 610 | static int mce_timed_out(u64 *t) |
| 611 | { |
| 612 | /* |
| 613 | * The others already did panic for some reason. |
| 614 | * Bail out like in a timeout. |
| 615 | * rmb() to tell the compiler that system_state |
| 616 | * might have been modified by someone else. |
| 617 | */ |
| 618 | rmb(); |
| 619 | if (atomic_read(&mce_paniced)) |
| 620 | wait_for_panic(); |
| 621 | if (!monarch_timeout) |
| 622 | goto out; |
| 623 | if ((s64)*t < SPINUNIT) { |
| 624 | /* CHECKME: Make panic default for 1 too? */ |
| 625 | if (tolerant < 1) |
| 626 | mce_panic("Timeout synchronizing machine check over CPUs", |
| 627 | NULL, NULL); |
| 628 | cpu_missing = 1; |
| 629 | return 1; |
| 630 | } |
| 631 | *t -= SPINUNIT; |
| 632 | out: |
| 633 | touch_nmi_watchdog(); |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | /* |
| 638 | * The Monarch's reign. The Monarch is the CPU who entered |
| 639 | * the machine check handler first. It waits for the others to |
| 640 | * raise the exception too and then grades them. When any |
| 641 | * error is fatal panic. Only then let the others continue. |
| 642 | * |
| 643 | * The other CPUs entering the MCE handler will be controlled by the |
| 644 | * Monarch. They are called Subjects. |
| 645 | * |
| 646 | * This way we prevent any potential data corruption in a unrecoverable case |
| 647 | * and also makes sure always all CPU's errors are examined. |
| 648 | * |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 649 | * Also this detects the case of a machine check event coming from outer |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 650 | * space (not detected by any CPUs) In this case some external agent wants |
| 651 | * us to shut down, so panic too. |
| 652 | * |
| 653 | * The other CPUs might still decide to panic if the handler happens |
| 654 | * in a unrecoverable place, but in this case the system is in a semi-stable |
| 655 | * state and won't corrupt anything by itself. It's ok to let the others |
| 656 | * continue for a bit first. |
| 657 | * |
| 658 | * All the spin loops have timeouts; when a timeout happens a CPU |
| 659 | * typically elects itself to be Monarch. |
| 660 | */ |
| 661 | static void mce_reign(void) |
| 662 | { |
| 663 | int cpu; |
| 664 | struct mce *m = NULL; |
| 665 | int global_worst = 0; |
| 666 | char *msg = NULL; |
| 667 | char *nmsg = NULL; |
| 668 | |
| 669 | /* |
| 670 | * This CPU is the Monarch and the other CPUs have run |
| 671 | * through their handlers. |
| 672 | * Grade the severity of the errors of all the CPUs. |
| 673 | */ |
| 674 | for_each_possible_cpu(cpu) { |
| 675 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, |
| 676 | &nmsg); |
| 677 | if (severity > global_worst) { |
| 678 | msg = nmsg; |
| 679 | global_worst = severity; |
| 680 | m = &per_cpu(mces_seen, cpu); |
| 681 | } |
| 682 | } |
| 683 | |
| 684 | /* |
| 685 | * Cannot recover? Panic here then. |
| 686 | * This dumps all the mces in the log buffer and stops the |
| 687 | * other CPUs. |
| 688 | */ |
| 689 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) |
Andi Kleen | ac96037 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 690 | mce_panic("Fatal Machine check", m, msg); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 691 | |
| 692 | /* |
| 693 | * For UC somewhere we let the CPU who detects it handle it. |
| 694 | * Also must let continue the others, otherwise the handling |
| 695 | * CPU could deadlock on a lock. |
| 696 | */ |
| 697 | |
| 698 | /* |
| 699 | * No machine check event found. Must be some external |
| 700 | * source or one CPU is hung. Panic. |
| 701 | */ |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 702 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 703 | mce_panic("Machine check from unknown source", NULL, NULL); |
| 704 | |
| 705 | /* |
| 706 | * Now clear all the mces_seen so that they don't reappear on |
| 707 | * the next mce. |
| 708 | */ |
| 709 | for_each_possible_cpu(cpu) |
| 710 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); |
| 711 | } |
| 712 | |
| 713 | static atomic_t global_nwo; |
| 714 | |
| 715 | /* |
| 716 | * Start of Monarch synchronization. This waits until all CPUs have |
| 717 | * entered the exception handler and then determines if any of them |
| 718 | * saw a fatal event that requires panic. Then it executes them |
| 719 | * in the entry order. |
| 720 | * TBD double check parallel CPU hotunplug |
| 721 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 722 | static int mce_start(int *no_way_out) |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 723 | { |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 724 | int order; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 725 | int cpus = num_online_cpus(); |
| 726 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; |
| 727 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 728 | if (!timeout) |
| 729 | return -1; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 730 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 731 | atomic_add(*no_way_out, &global_nwo); |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 732 | /* |
| 733 | * global_nwo should be updated before mce_callin |
| 734 | */ |
| 735 | smp_wmb(); |
Borislav Petkov | a95436e | 2009-06-20 23:28:22 -0700 | [diff] [blame] | 736 | order = atomic_inc_return(&mce_callin); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 737 | |
| 738 | /* |
| 739 | * Wait for everyone. |
| 740 | */ |
| 741 | while (atomic_read(&mce_callin) != cpus) { |
| 742 | if (mce_timed_out(&timeout)) { |
| 743 | atomic_set(&global_nwo, 0); |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 744 | return -1; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 745 | } |
| 746 | ndelay(SPINUNIT); |
| 747 | } |
| 748 | |
| 749 | /* |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 750 | * mce_callin should be read before global_nwo |
| 751 | */ |
| 752 | smp_rmb(); |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 753 | |
| 754 | if (order == 1) { |
| 755 | /* |
| 756 | * Monarch: Starts executing now, the others wait. |
| 757 | */ |
| 758 | atomic_set(&mce_executing, 1); |
| 759 | } else { |
| 760 | /* |
| 761 | * Subject: Now start the scanning loop one by one in |
| 762 | * the original callin order. |
| 763 | * This way when there are any shared banks it will be |
| 764 | * only seen by one CPU before cleared, avoiding duplicates. |
| 765 | */ |
| 766 | while (atomic_read(&mce_executing) < order) { |
| 767 | if (mce_timed_out(&timeout)) { |
| 768 | atomic_set(&global_nwo, 0); |
| 769 | return -1; |
| 770 | } |
| 771 | ndelay(SPINUNIT); |
| 772 | } |
| 773 | } |
| 774 | |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 775 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 776 | * Cache the global no_way_out state. |
| 777 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 778 | *no_way_out = atomic_read(&global_nwo); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 779 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 780 | return order; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 781 | } |
| 782 | |
| 783 | /* |
| 784 | * Synchronize between CPUs after main scanning loop. |
| 785 | * This invokes the bulk of the Monarch processing. |
| 786 | */ |
| 787 | static int mce_end(int order) |
| 788 | { |
| 789 | int ret = -1; |
| 790 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; |
| 791 | |
| 792 | if (!timeout) |
| 793 | goto reset; |
| 794 | if (order < 0) |
| 795 | goto reset; |
| 796 | |
| 797 | /* |
| 798 | * Allow others to run. |
| 799 | */ |
| 800 | atomic_inc(&mce_executing); |
| 801 | |
| 802 | if (order == 1) { |
| 803 | /* CHECKME: Can this race with a parallel hotplug? */ |
| 804 | int cpus = num_online_cpus(); |
| 805 | |
| 806 | /* |
| 807 | * Monarch: Wait for everyone to go through their scanning |
| 808 | * loops. |
| 809 | */ |
| 810 | while (atomic_read(&mce_executing) <= cpus) { |
| 811 | if (mce_timed_out(&timeout)) |
| 812 | goto reset; |
| 813 | ndelay(SPINUNIT); |
| 814 | } |
| 815 | |
| 816 | mce_reign(); |
| 817 | barrier(); |
| 818 | ret = 0; |
| 819 | } else { |
| 820 | /* |
| 821 | * Subject: Wait for Monarch to finish. |
| 822 | */ |
| 823 | while (atomic_read(&mce_executing) != 0) { |
| 824 | if (mce_timed_out(&timeout)) |
| 825 | goto reset; |
| 826 | ndelay(SPINUNIT); |
| 827 | } |
| 828 | |
| 829 | /* |
| 830 | * Don't reset anything. That's done by the Monarch. |
| 831 | */ |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | /* |
| 836 | * Reset all global state. |
| 837 | */ |
| 838 | reset: |
| 839 | atomic_set(&global_nwo, 0); |
| 840 | atomic_set(&mce_callin, 0); |
| 841 | barrier(); |
| 842 | |
| 843 | /* |
| 844 | * Let others run again. |
| 845 | */ |
| 846 | atomic_set(&mce_executing, 0); |
| 847 | return ret; |
| 848 | } |
| 849 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 850 | /* |
| 851 | * Check if the address reported by the CPU is in a format we can parse. |
| 852 | * It would be possible to add code for most other cases, but all would |
| 853 | * be somewhat complicated (e.g. segment offset would require an instruction |
| 854 | * parser). So only support physical addresses upto page granuality for now. |
| 855 | */ |
| 856 | static int mce_usable_address(struct mce *m) |
| 857 | { |
| 858 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) |
| 859 | return 0; |
| 860 | if ((m->misc & 0x3f) > PAGE_SHIFT) |
| 861 | return 0; |
| 862 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) |
| 863 | return 0; |
| 864 | return 1; |
| 865 | } |
| 866 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 867 | static void mce_clear_state(unsigned long *toclear) |
| 868 | { |
| 869 | int i; |
| 870 | |
| 871 | for (i = 0; i < banks; i++) { |
| 872 | if (test_bit(i, toclear)) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 873 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 874 | } |
| 875 | } |
| 876 | |
| 877 | /* |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 878 | * The actual machine check handler. This only handles real |
| 879 | * exceptions when something got corrupted coming in through int 18. |
| 880 | * |
| 881 | * This is executed in NMI context not subject to normal locking rules. This |
| 882 | * implies that most kernel services cannot be safely used. Don't even |
| 883 | * think about putting a printk in there! |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 884 | * |
| 885 | * On Intel systems this is entered on all CPUs in parallel through |
| 886 | * MCE broadcast. However some CPUs might be broken beyond repair, |
| 887 | * so be always careful when synchronizing with others. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 889 | void do_machine_check(struct pt_regs *regs, long error_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 890 | { |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 891 | struct mce m, *final; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 892 | int i; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 893 | int worst = 0; |
| 894 | int severity; |
| 895 | /* |
| 896 | * Establish sequential order between the CPUs entering the machine |
| 897 | * check handler. |
| 898 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 899 | int order; |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 900 | /* |
| 901 | * If no_way_out gets set, there is no safe way to recover from this |
| 902 | * MCE. If tolerant is cranked up, we'll try anyway. |
| 903 | */ |
| 904 | int no_way_out = 0; |
| 905 | /* |
| 906 | * If kill_it gets set, there might be a way to recover from this |
| 907 | * error. |
| 908 | */ |
| 909 | int kill_it = 0; |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 910 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 911 | char *msg = "Unknown"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 912 | |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 913 | atomic_inc(&mce_entry); |
| 914 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 915 | __get_cpu_var(mce_exception_count)++; |
| 916 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 917 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
Jan Beulich | 22f5991 | 2008-01-30 13:31:23 +0100 | [diff] [blame] | 918 | 18, SIGKILL) == NOTIFY_STOP) |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 919 | goto out; |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 920 | if (!banks) |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 921 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 923 | mce_setup(&m); |
| 924 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 925 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 926 | final = &__get_cpu_var(mces_seen); |
| 927 | *final = m; |
| 928 | |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 929 | no_way_out = mce_no_way_out(&m, &msg); |
| 930 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | barrier(); |
| 932 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 933 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 934 | * When no restart IP must always kill or panic. |
| 935 | */ |
| 936 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
| 937 | kill_it = 1; |
| 938 | |
| 939 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 940 | * Go through all the banks in exclusion of the other CPUs. |
| 941 | * This way we don't report duplicated events on shared banks |
| 942 | * because the first one to see it will clear it. |
| 943 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 944 | order = mce_start(&no_way_out); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 945 | for (i = 0; i < banks; i++) { |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 946 | __clear_bit(i, toclear); |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 947 | if (!mce_banks[i].ctl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | continue; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 949 | |
| 950 | m.misc = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | m.addr = 0; |
| 952 | m.bank = i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 954 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | if ((m.status & MCI_STATUS_VAL) == 0) |
| 956 | continue; |
| 957 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 958 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 959 | * Non uncorrected or non signaled errors are handled by |
| 960 | * machine_check_poll. Leave them alone, unless this panics. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 961 | */ |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 962 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
| 963 | !no_way_out) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 964 | continue; |
| 965 | |
| 966 | /* |
| 967 | * Set taint even when machine check was not enabled. |
| 968 | */ |
| 969 | add_taint(TAINT_MACHINE_CHECK); |
| 970 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 971 | severity = mce_severity(&m, tolerant, NULL); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 972 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 973 | /* |
| 974 | * When machine check was for corrected handler don't touch, |
| 975 | * unless we're panicing. |
| 976 | */ |
| 977 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) |
| 978 | continue; |
| 979 | __set_bit(i, toclear); |
| 980 | if (severity == MCE_NO_SEVERITY) { |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 981 | /* |
| 982 | * Machine check event was not enabled. Clear, but |
| 983 | * ignore. |
| 984 | */ |
| 985 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | } |
| 987 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 988 | /* |
| 989 | * Kill on action required. |
| 990 | */ |
| 991 | if (severity == MCE_AR_SEVERITY) |
| 992 | kill_it = 1; |
| 993 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | if (m.status & MCI_STATUS_MISCV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 995 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | if (m.status & MCI_STATUS_ADDRV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 997 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 999 | /* |
| 1000 | * Action optional error. Queue address for later processing. |
| 1001 | * When the ring overflows we just ignore the AO error. |
| 1002 | * RED-PEN add some logging mechanism when |
| 1003 | * usable_address or mce_add_ring fails. |
| 1004 | * RED-PEN don't ignore overflow for tolerant == 0 |
| 1005 | */ |
| 1006 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) |
| 1007 | mce_ring_add(m.addr >> PAGE_SHIFT); |
| 1008 | |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 1009 | mce_get_rip(&m, regs); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1010 | mce_log(&m); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1011 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1012 | if (severity > worst) { |
| 1013 | *final = m; |
| 1014 | worst = severity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1015 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | } |
| 1017 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1018 | if (!no_way_out) |
| 1019 | mce_clear_state(toclear); |
| 1020 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1021 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1022 | * Do most of the synchronization with other CPUs. |
| 1023 | * When there's any problem use only local no_way_out state. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1024 | */ |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1025 | if (mce_end(order) < 0) |
| 1026 | no_way_out = worst >= MCE_PANIC_SEVERITY; |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1027 | |
| 1028 | /* |
| 1029 | * If we have decided that we just CAN'T continue, and the user |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1030 | * has not set tolerant to an insane level, give up and die. |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1031 | * |
| 1032 | * This is mainly used in the case when the system doesn't |
| 1033 | * support MCE broadcasting or it has been disabled. |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1034 | */ |
| 1035 | if (no_way_out && tolerant < 3) |
Andi Kleen | ac96037 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1036 | mce_panic("Fatal machine check on current CPU", final, msg); |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1037 | |
| 1038 | /* |
| 1039 | * If the error seems to be unrecoverable, something should be |
| 1040 | * done. Try to kill as little as possible. If we can kill just |
| 1041 | * one task, do that. If the user has set the tolerance very |
| 1042 | * high, don't try to do anything at all. |
| 1043 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1045 | if (kill_it && tolerant < 3) |
| 1046 | force_sig(SIGBUS, current); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1048 | /* notify userspace ASAP */ |
| 1049 | set_thread_flag(TIF_MCE_NOTIFY); |
| 1050 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1051 | if (worst > 0) |
| 1052 | mce_report_event(regs); |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 1053 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 1054 | out: |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 1055 | atomic_dec(&mce_entry); |
Andi Kleen | 88921be | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 1056 | sync_core(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | } |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1058 | EXPORT_SYMBOL_GPL(do_machine_check); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 1060 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
| 1061 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) |
| 1062 | { |
| 1063 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); |
| 1064 | } |
| 1065 | |
| 1066 | /* |
| 1067 | * Called after mce notification in process context. This code |
| 1068 | * is allowed to sleep. Call the high level VM handler to process |
| 1069 | * any corrupted pages. |
| 1070 | * Assume that the work queue code only calls this one at a time |
| 1071 | * per CPU. |
| 1072 | * Note we don't disable preemption, so this code might run on the wrong |
| 1073 | * CPU. In this case the event is picked up by the scheduled work queue. |
| 1074 | * This is merely a fast path to expedite processing in some common |
| 1075 | * cases. |
| 1076 | */ |
| 1077 | void mce_notify_process(void) |
| 1078 | { |
| 1079 | unsigned long pfn; |
| 1080 | mce_notify_irq(); |
| 1081 | while (mce_ring_get(&pfn)) |
| 1082 | memory_failure(pfn, MCE_VECTOR); |
| 1083 | } |
| 1084 | |
| 1085 | static void mce_process_work(struct work_struct *dummy) |
| 1086 | { |
| 1087 | mce_notify_process(); |
| 1088 | } |
| 1089 | |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1090 | #ifdef CONFIG_X86_MCE_INTEL |
| 1091 | /*** |
| 1092 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog |
Simon Arlott | 676b185 | 2007-10-20 01:25:36 +0200 | [diff] [blame] | 1093 | * @cpu: The CPU on which the event occurred. |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1094 | * @status: Event status information |
| 1095 | * |
| 1096 | * This function should be called by the thermal interrupt after the |
| 1097 | * event has been processed and the decision was made to log the event |
| 1098 | * further. |
| 1099 | * |
| 1100 | * The status parameter will be saved to the 'status' field of 'struct mce' |
| 1101 | * and historically has been the register value of the |
| 1102 | * MSR_IA32_THERMAL_STATUS (Intel) msr. |
| 1103 | */ |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 1104 | void mce_log_therm_throt_event(__u64 status) |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1105 | { |
| 1106 | struct mce m; |
| 1107 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 1108 | mce_setup(&m); |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1109 | m.bank = MCE_THERMAL_BANK; |
| 1110 | m.status = status; |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1111 | mce_log(&m); |
| 1112 | } |
| 1113 | #endif /* CONFIG_X86_MCE_INTEL */ |
| 1114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | /* |
Tim Hockin | 8a336b0 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 1116 | * Periodic polling timer for "silent" machine check errors. If the |
| 1117 | * poller finds an MCE, poll 2x faster. When the poller finds no more |
| 1118 | * errors, poll 2x slower (up to check_interval seconds). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1120 | static int check_interval = 5 * 60; /* 5 minutes */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1121 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1122 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1123 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1124 | |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1125 | static void mcheck_timer(unsigned long data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | { |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1127 | struct timer_list *t = &per_cpu(mce_timer, data); |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1128 | int *n; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1129 | |
| 1130 | WARN_ON(smp_processor_id() != data); |
| 1131 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1132 | if (mce_available(¤t_cpu_data)) { |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 1133 | machine_check_poll(MCP_TIMESTAMP, |
| 1134 | &__get_cpu_var(mce_poll_banks)); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1135 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1136 | |
| 1137 | /* |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1138 | * Alert userspace if needed. If we logged an MCE, reduce the |
| 1139 | * polling interval, otherwise increase the polling interval. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1140 | */ |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1141 | n = &__get_cpu_var(mce_next_interval); |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1142 | if (mce_notify_irq()) |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1143 | *n = max(*n/2, HZ/100); |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 1144 | else |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1145 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
Tim Hockin | 8a336b0 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 1146 | |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1147 | t->expires = jiffies + *n; |
Hidetoshi Seto | 5be6066 | 2009-06-24 09:21:10 +0900 | [diff] [blame] | 1148 | add_timer_on(t, smp_processor_id()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | } |
| 1150 | |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1151 | static void mce_do_trigger(struct work_struct *work) |
| 1152 | { |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1153 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1154 | } |
| 1155 | |
| 1156 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); |
| 1157 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1158 | /* |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1159 | * Notify the user(s) about new machine check events. |
| 1160 | * Can be called from interrupt context, but not from machine check/NMI |
| 1161 | * context. |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1162 | */ |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1163 | int mce_notify_irq(void) |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1164 | { |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 1165 | /* Not more than two messages every minute */ |
| 1166 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); |
| 1167 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1168 | clear_thread_flag(TIF_MCE_NOTIFY); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1169 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1170 | if (test_and_clear_bit(0, &mce_need_notify)) { |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1171 | wake_up_interruptible(&mce_wait); |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1172 | |
| 1173 | /* |
| 1174 | * There is no risk of missing notifications because |
| 1175 | * work_pending is always cleared before the function is |
| 1176 | * executed. |
| 1177 | */ |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1178 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1179 | schedule_work(&mce_trigger_work); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1180 | |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 1181 | if (__ratelimit(&ratelimit)) |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1182 | printk(KERN_INFO "Machine check events logged\n"); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1183 | |
| 1184 | return 1; |
| 1185 | } |
| 1186 | return 0; |
| 1187 | } |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1188 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1189 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1190 | static int mce_banks_init(void) |
| 1191 | { |
| 1192 | int i; |
| 1193 | |
| 1194 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); |
| 1195 | if (!mce_banks) |
| 1196 | return -ENOMEM; |
| 1197 | for (i = 0; i < banks; i++) { |
| 1198 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1199 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1200 | b->ctl = -1ULL; |
| 1201 | b->init = 1; |
| 1202 | } |
| 1203 | return 0; |
| 1204 | } |
| 1205 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1206 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1207 | * Initialize Machine Checks for a CPU. |
| 1208 | */ |
Bartlomiej Zolnierkiewicz | 419d616 | 2009-07-28 23:56:00 +0200 | [diff] [blame] | 1209 | static int __cpuinit mce_cap_init(void) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1210 | { |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1211 | unsigned b; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1212 | u64 cap; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1213 | |
| 1214 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 1215 | |
| 1216 | b = cap & MCG_BANKCNT_MASK; |
Ingo Molnar | b659294 | 2009-04-08 12:31:27 +0200 | [diff] [blame] | 1217 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
| 1218 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1219 | if (b > MAX_NR_BANKS) { |
| 1220 | printk(KERN_WARNING |
| 1221 | "MCE: Using only %u machine check banks out of %u\n", |
| 1222 | MAX_NR_BANKS, b); |
| 1223 | b = MAX_NR_BANKS; |
| 1224 | } |
| 1225 | |
| 1226 | /* Don't support asymmetric configurations today */ |
| 1227 | WARN_ON(banks != 0 && b != banks); |
| 1228 | banks = b; |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1229 | if (!mce_banks) { |
| 1230 | int err = mce_banks_init(); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1231 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1232 | if (err) |
| 1233 | return err; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1234 | } |
| 1235 | |
| 1236 | /* Use accurate RIP reporting if available. */ |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 1237 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1238 | rip_msr = MSR_IA32_MCG_EIP; |
| 1239 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1240 | if (cap & MCG_SER_P) |
| 1241 | mce_ser = 1; |
| 1242 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1243 | return 0; |
| 1244 | } |
| 1245 | |
Thomas Gleixner | 8be9110 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 1246 | static void mce_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1247 | { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1248 | mce_banks_t all_banks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1249 | u64 cap; |
| 1250 | int i; |
| 1251 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1252 | /* |
| 1253 | * Log the machine checks left over from the previous reset. |
| 1254 | */ |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 1255 | bitmap_fill(all_banks, MAX_NR_BANKS); |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 1256 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | |
| 1258 | set_in_cr4(X86_CR4_MCE); |
| 1259 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1260 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | if (cap & MCG_CTL_P) |
| 1262 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
| 1263 | |
| 1264 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1265 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1266 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1267 | if (!b->init) |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1268 | continue; |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1269 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
| 1270 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1271 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1272 | } |
| 1273 | |
| 1274 | /* Add per CPU specific workarounds here */ |
Linus Torvalds | df58bee | 2009-09-17 21:07:08 -0700 | [diff] [blame] | 1275 | static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1276 | { |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1277 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
| 1278 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); |
| 1279 | return -EOPNOTSUPP; |
| 1280 | } |
| 1281 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | /* This should be disabled by the BIOS, but isn't always */ |
Jan Beulich | 911f6a7 | 2008-04-22 16:22:21 +0100 | [diff] [blame] | 1283 | if (c->x86_vendor == X86_VENDOR_AMD) { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1284 | if (c->x86 == 15 && banks > 4) { |
| 1285 | /* |
| 1286 | * disable GART TBL walk error reporting, which |
| 1287 | * trips off incorrectly with the IOMMU & 3ware |
| 1288 | * & Cerberus: |
| 1289 | */ |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1290 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1291 | } |
| 1292 | if (c->x86 <= 17 && mce_bootlog < 0) { |
| 1293 | /* |
| 1294 | * Lots of broken BIOS around that don't clear them |
| 1295 | * by default and leave crap in there. Don't log: |
| 1296 | */ |
Jan Beulich | 911f6a7 | 2008-04-22 16:22:21 +0100 | [diff] [blame] | 1297 | mce_bootlog = 0; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1298 | } |
Andi Kleen | 2e6f694 | 2009-04-27 18:42:48 +0200 | [diff] [blame] | 1299 | /* |
| 1300 | * Various K7s with broken bank 0 around. Always disable |
| 1301 | * by default. |
| 1302 | */ |
Andi Kleen | 203abd6 | 2009-06-15 14:52:01 +0200 | [diff] [blame] | 1303 | if (c->x86 == 6 && banks > 0) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1304 | mce_banks[0].ctl = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1305 | } |
Andi Kleen | e583538 | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 1306 | |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1307 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
| 1308 | /* |
| 1309 | * SDM documents that on family 6 bank 0 should not be written |
| 1310 | * because it aliases to another special BIOS controlled |
| 1311 | * register. |
| 1312 | * But it's not aliased anymore on model 0x1a+ |
| 1313 | * Don't ignore bank 0 completely because there could be a |
| 1314 | * valid event later, merely don't write CTL0. |
| 1315 | */ |
| 1316 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1317 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
| 1318 | mce_banks[0].init = 0; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1319 | |
| 1320 | /* |
| 1321 | * All newer Intel systems support MCE broadcasting. Enable |
| 1322 | * synchronization with a one second timeout. |
| 1323 | */ |
| 1324 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && |
| 1325 | monarch_timeout < 0) |
| 1326 | monarch_timeout = USEC_PER_SEC; |
Bartlomiej Zolnierkiewicz | c7f6fa4 | 2009-07-28 23:52:54 +0200 | [diff] [blame] | 1327 | |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1328 | /* |
| 1329 | * There are also broken BIOSes on some Pentium M and |
| 1330 | * earlier systems: |
| 1331 | */ |
| 1332 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) |
Bartlomiej Zolnierkiewicz | c7f6fa4 | 2009-07-28 23:52:54 +0200 | [diff] [blame] | 1333 | mce_bootlog = 0; |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1334 | } |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1335 | if (monarch_timeout < 0) |
| 1336 | monarch_timeout = 0; |
Andi Kleen | 29b0f59 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 1337 | if (mce_bootlog != 0) |
| 1338 | mce_panic_timeout = 30; |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1339 | |
| 1340 | return 0; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1341 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1342 | |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1343 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
| 1344 | { |
| 1345 | if (c->x86 != 5) |
| 1346 | return; |
| 1347 | switch (c->x86_vendor) { |
| 1348 | case X86_VENDOR_INTEL: |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 1349 | intel_p5_mcheck_init(c); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1350 | break; |
| 1351 | case X86_VENDOR_CENTAUR: |
| 1352 | winchip_mcheck_init(c); |
| 1353 | break; |
| 1354 | } |
| 1355 | } |
| 1356 | |
H. Peter Anvin | cc3ca22 | 2009-02-20 23:35:51 -0800 | [diff] [blame] | 1357 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1358 | { |
| 1359 | switch (c->x86_vendor) { |
| 1360 | case X86_VENDOR_INTEL: |
| 1361 | mce_intel_feature_init(c); |
| 1362 | break; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1363 | case X86_VENDOR_AMD: |
| 1364 | mce_amd_feature_init(c); |
| 1365 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1366 | default: |
| 1367 | break; |
| 1368 | } |
| 1369 | } |
| 1370 | |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1371 | static void mce_init_timer(void) |
| 1372 | { |
| 1373 | struct timer_list *t = &__get_cpu_var(mce_timer); |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1374 | int *n = &__get_cpu_var(mce_next_interval); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1375 | |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1376 | if (mce_ignore_ce) |
| 1377 | return; |
| 1378 | |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1379 | *n = check_interval * HZ; |
| 1380 | if (!*n) |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1381 | return; |
| 1382 | setup_timer(t, mcheck_timer, smp_processor_id()); |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1383 | t->expires = round_jiffies(jiffies + *n); |
Hidetoshi Seto | 5be6066 | 2009-06-24 09:21:10 +0900 | [diff] [blame] | 1384 | add_timer_on(t, smp_processor_id()); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1385 | } |
| 1386 | |
Andi Kleen | 9eda8cb | 2009-07-09 00:31:42 +0200 | [diff] [blame] | 1387 | /* Handle unconfigured int18 (should never happen) */ |
| 1388 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) |
| 1389 | { |
| 1390 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", |
| 1391 | smp_processor_id()); |
| 1392 | } |
| 1393 | |
| 1394 | /* Call the installed machine check handler for this CPU setup. */ |
| 1395 | void (*machine_check_vector)(struct pt_regs *, long error_code) = |
| 1396 | unexpected_machine_check; |
| 1397 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1398 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1399 | * Called for each booted CPU to set up machine checks. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1400 | * Must be called with preempt off: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | */ |
Ashok Raj | e6982c6 | 2005-06-25 14:54:58 -0700 | [diff] [blame] | 1402 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1403 | { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1404 | if (mce_disabled) |
| 1405 | return; |
| 1406 | |
| 1407 | mce_ancient_init(c); |
| 1408 | |
Andi Kleen | 5b4408f | 2009-02-12 13:39:30 +0100 | [diff] [blame] | 1409 | if (!mce_available(c)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | return; |
| 1411 | |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1412 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 1413 | mce_disabled = 1; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1414 | return; |
| 1415 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1416 | |
Andi Kleen | 5d72792 | 2009-04-27 19:25:48 +0200 | [diff] [blame] | 1417 | machine_check_vector = do_machine_check; |
| 1418 | |
Thomas Gleixner | 8be9110 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 1419 | mce_init(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | mce_cpu_features(c); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1421 | mce_init_timer(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 1422 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1423 | } |
| 1424 | |
| 1425 | /* |
| 1426 | * Character device to read and clear the MCE log. |
| 1427 | */ |
| 1428 | |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1429 | static DEFINE_SPINLOCK(mce_state_lock); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1430 | static int open_count; /* #times opened */ |
| 1431 | static int open_exclu; /* already open exclusive? */ |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1432 | |
| 1433 | static int mce_open(struct inode *inode, struct file *file) |
| 1434 | { |
| 1435 | spin_lock(&mce_state_lock); |
| 1436 | |
| 1437 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { |
| 1438 | spin_unlock(&mce_state_lock); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1439 | |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1440 | return -EBUSY; |
| 1441 | } |
| 1442 | |
| 1443 | if (file->f_flags & O_EXCL) |
| 1444 | open_exclu = 1; |
| 1445 | open_count++; |
| 1446 | |
| 1447 | spin_unlock(&mce_state_lock); |
| 1448 | |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1449 | return nonseekable_open(inode, file); |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1450 | } |
| 1451 | |
| 1452 | static int mce_release(struct inode *inode, struct file *file) |
| 1453 | { |
| 1454 | spin_lock(&mce_state_lock); |
| 1455 | |
| 1456 | open_count--; |
| 1457 | open_exclu = 0; |
| 1458 | |
| 1459 | spin_unlock(&mce_state_lock); |
| 1460 | |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1464 | static void collect_tscs(void *data) |
| 1465 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1466 | unsigned long *cpu_tsc = (unsigned long *)data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1467 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1468 | rdtscll(cpu_tsc[smp_processor_id()]); |
| 1469 | } |
| 1470 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1471 | static DEFINE_MUTEX(mce_read_mutex); |
| 1472 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1473 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
| 1474 | loff_t *off) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1475 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1476 | char __user *buf = ubuf; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1477 | unsigned long *cpu_tsc; |
| 1478 | unsigned prev, next; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1479 | int i, err; |
| 1480 | |
Mike Travis | 6bca67f | 2008-07-18 18:11:27 -0700 | [diff] [blame] | 1481 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
Andi Kleen | f0de53b | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 1482 | if (!cpu_tsc) |
| 1483 | return -ENOMEM; |
| 1484 | |
Daniel Walker | 8c8b885 | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 1485 | mutex_lock(&mce_read_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1486 | next = rcu_dereference(mcelog.next); |
| 1487 | |
| 1488 | /* Only supports full reads right now */ |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1489 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
Daniel Walker | 8c8b885 | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 1490 | mutex_unlock(&mce_read_mutex); |
Andi Kleen | f0de53b | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 1491 | kfree(cpu_tsc); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1492 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1493 | return -EINVAL; |
| 1494 | } |
| 1495 | |
| 1496 | err = 0; |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1497 | prev = 0; |
| 1498 | do { |
| 1499 | for (i = prev; i < next; i++) { |
| 1500 | unsigned long start = jiffies; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1501 | |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1502 | while (!mcelog.entry[i].finished) { |
| 1503 | if (time_after_eq(jiffies, start + 2)) { |
| 1504 | memset(mcelog.entry + i, 0, |
| 1505 | sizeof(struct mce)); |
| 1506 | goto timeout; |
| 1507 | } |
| 1508 | cpu_relax(); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1509 | } |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1510 | smp_rmb(); |
| 1511 | err |= copy_to_user(buf, mcelog.entry + i, |
| 1512 | sizeof(struct mce)); |
| 1513 | buf += sizeof(struct mce); |
| 1514 | timeout: |
| 1515 | ; |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1516 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1517 | |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1518 | memset(mcelog.entry + prev, 0, |
| 1519 | (next - prev) * sizeof(struct mce)); |
| 1520 | prev = next; |
| 1521 | next = cmpxchg(&mcelog.next, prev, 0); |
| 1522 | } while (next != prev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1523 | |
Paul E. McKenney | b2b1866 | 2005-06-25 14:55:38 -0700 | [diff] [blame] | 1524 | synchronize_sched(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1525 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1526 | /* |
| 1527 | * Collect entries that were still getting written before the |
| 1528 | * synchronize. |
| 1529 | */ |
Jens Axboe | 15c8b6c | 2008-05-09 09:39:44 +0200 | [diff] [blame] | 1530 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1531 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1532 | for (i = next; i < MCE_LOG_LEN; i++) { |
| 1533 | if (mcelog.entry[i].finished && |
| 1534 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { |
| 1535 | err |= copy_to_user(buf, mcelog.entry+i, |
| 1536 | sizeof(struct mce)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1537 | smp_rmb(); |
| 1538 | buf += sizeof(struct mce); |
| 1539 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); |
| 1540 | } |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1541 | } |
Daniel Walker | 8c8b885 | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 1542 | mutex_unlock(&mce_read_mutex); |
Andi Kleen | f0de53b | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 1543 | kfree(cpu_tsc); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1544 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1545 | return err ? -EFAULT : buf - ubuf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1546 | } |
| 1547 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1548 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
| 1549 | { |
| 1550 | poll_wait(file, &mce_wait, wait); |
| 1551 | if (rcu_dereference(mcelog.next)) |
| 1552 | return POLLIN | POLLRDNORM; |
| 1553 | return 0; |
| 1554 | } |
| 1555 | |
Nikanth Karthikesan | c68461b | 2008-01-30 13:32:59 +0100 | [diff] [blame] | 1556 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1557 | { |
| 1558 | int __user *p = (int __user *)arg; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1559 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1560 | if (!capable(CAP_SYS_ADMIN)) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1561 | return -EPERM; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1562 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | switch (cmd) { |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1564 | case MCE_GET_RECORD_LEN: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1565 | return put_user(sizeof(struct mce), p); |
| 1566 | case MCE_GET_LOG_LEN: |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1567 | return put_user(MCE_LOG_LEN, p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | case MCE_GETCLEAR_FLAGS: { |
| 1569 | unsigned flags; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1570 | |
| 1571 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | flags = mcelog.flags; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1573 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1574 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1575 | return put_user(flags, p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | } |
| 1577 | default: |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1578 | return -ENOTTY; |
| 1579 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1580 | } |
| 1581 | |
H. Peter Anvin | a1ff41b | 2009-05-25 22:16:14 -0700 | [diff] [blame] | 1582 | /* Modified in mce-inject.c, so not static or const */ |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1583 | struct file_operations mce_chrdev_ops = { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1584 | .open = mce_open, |
| 1585 | .release = mce_release, |
| 1586 | .read = mce_read, |
| 1587 | .poll = mce_poll, |
| 1588 | .unlocked_ioctl = mce_ioctl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | }; |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1590 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1591 | |
| 1592 | static struct miscdevice mce_log_device = { |
| 1593 | MISC_MCELOG_MINOR, |
| 1594 | "mcelog", |
| 1595 | &mce_chrdev_ops, |
| 1596 | }; |
| 1597 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1598 | /* |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1599 | * mce=off Disables machine check |
| 1600 | * mce=no_cmci Disables CMCI |
| 1601 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
| 1602 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1603 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
| 1604 | * monarchtimeout is how long to wait for other CPUs on machine |
| 1605 | * check, or 0 to not wait |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1606 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
| 1607 | * mce=nobootlog Don't log MCEs from before booting. |
| 1608 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1609 | static int __init mcheck_enable(char *str) |
| 1610 | { |
Bartlomiej Zolnierkiewicz | e3346fc | 2009-07-28 23:55:09 +0200 | [diff] [blame] | 1611 | if (*str == 0) { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1612 | enable_p5_mce(); |
Bartlomiej Zolnierkiewicz | e3346fc | 2009-07-28 23:55:09 +0200 | [diff] [blame] | 1613 | return 1; |
| 1614 | } |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1615 | if (*str == '=') |
| 1616 | str++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1617 | if (!strcmp(str, "off")) |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 1618 | mce_disabled = 1; |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1619 | else if (!strcmp(str, "no_cmci")) |
| 1620 | mce_cmci_disabled = 1; |
| 1621 | else if (!strcmp(str, "dont_log_ce")) |
| 1622 | mce_dont_log_ce = 1; |
| 1623 | else if (!strcmp(str, "ignore_ce")) |
| 1624 | mce_ignore_ce = 1; |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1625 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
| 1626 | mce_bootlog = (str[0] == 'b'); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1627 | else if (isdigit(str[0])) { |
Andi Kleen | 8c566ef | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1628 | get_option(&str, &tolerant); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1629 | if (*str == ',') { |
| 1630 | ++str; |
| 1631 | get_option(&str, &monarch_timeout); |
| 1632 | } |
| 1633 | } else { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1634 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1635 | str); |
| 1636 | return 0; |
| 1637 | } |
OGAWA Hirofumi | 9b41046 | 2006-03-31 02:30:33 -0800 | [diff] [blame] | 1638 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1639 | } |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1640 | __setup("mce", mcheck_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1642 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | * Sysfs support |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1644 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1645 | |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1646 | /* |
| 1647 | * Disable machine checks on suspend and shutdown. We can't really handle |
| 1648 | * them later. |
| 1649 | */ |
| 1650 | static int mce_disable(void) |
| 1651 | { |
| 1652 | int i; |
| 1653 | |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1654 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1655 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1656 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1657 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1658 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1659 | } |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1660 | return 0; |
| 1661 | } |
| 1662 | |
| 1663 | static int mce_suspend(struct sys_device *dev, pm_message_t state) |
| 1664 | { |
| 1665 | return mce_disable(); |
| 1666 | } |
| 1667 | |
| 1668 | static int mce_shutdown(struct sys_device *dev) |
| 1669 | { |
| 1670 | return mce_disable(); |
| 1671 | } |
| 1672 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1673 | /* |
| 1674 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. |
| 1675 | * Only one CPU is active at this time, the others get re-added later using |
| 1676 | * CPU hotplug: |
| 1677 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1678 | static int mce_resume(struct sys_device *dev) |
| 1679 | { |
Thomas Gleixner | 8be9110 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 1680 | mce_init(); |
Andi Kleen | 6ec68bf | 2009-02-12 13:39:26 +0100 | [diff] [blame] | 1681 | mce_cpu_features(¤t_cpu_data); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1682 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1683 | return 0; |
| 1684 | } |
| 1685 | |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1686 | static void mce_cpu_restart(void *data) |
| 1687 | { |
| 1688 | del_timer_sync(&__get_cpu_var(mce_timer)); |
Hidetoshi Seto | 33edbf0 | 2009-06-15 17:18:45 +0900 | [diff] [blame] | 1689 | if (!mce_available(¤t_cpu_data)) |
| 1690 | return; |
| 1691 | mce_init(); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1692 | mce_init_timer(); |
| 1693 | } |
| 1694 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | /* Reinit MCEs after user configuration changes */ |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1696 | static void mce_restart(void) |
| 1697 | { |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1698 | on_each_cpu(mce_cpu_restart, NULL, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | } |
| 1700 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1701 | /* Toggle features for corrected errors */ |
| 1702 | static void mce_disable_ce(void *all) |
| 1703 | { |
| 1704 | if (!mce_available(¤t_cpu_data)) |
| 1705 | return; |
| 1706 | if (all) |
| 1707 | del_timer_sync(&__get_cpu_var(mce_timer)); |
| 1708 | cmci_clear(); |
| 1709 | } |
| 1710 | |
| 1711 | static void mce_enable_ce(void *all) |
| 1712 | { |
| 1713 | if (!mce_available(¤t_cpu_data)) |
| 1714 | return; |
| 1715 | cmci_reenable(); |
| 1716 | cmci_recheck(); |
| 1717 | if (all) |
| 1718 | mce_init_timer(); |
| 1719 | } |
| 1720 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | static struct sysdev_class mce_sysclass = { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1722 | .suspend = mce_suspend, |
| 1723 | .shutdown = mce_shutdown, |
| 1724 | .resume = mce_resume, |
| 1725 | .name = "machinecheck", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1726 | }; |
| 1727 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1728 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1729 | |
| 1730 | __cpuinitdata |
| 1731 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1732 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1733 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
| 1734 | { |
| 1735 | return container_of(attr, struct mce_bank, attr); |
| 1736 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1737 | |
| 1738 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, |
| 1739 | char *buf) |
| 1740 | { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1741 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1742 | } |
| 1743 | |
| 1744 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1745 | const char *buf, size_t size) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1746 | { |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1747 | u64 new; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1748 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1749 | if (strict_strtoull(buf, 0, &new) < 0) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1750 | return -EINVAL; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1751 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1752 | attr_to_bank(attr)->ctl = new; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1753 | mce_restart(); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1754 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1755 | return size; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1756 | } |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1757 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1758 | static ssize_t |
| 1759 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1760 | { |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1761 | strcpy(buf, mce_helper); |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1762 | strcat(buf, "\n"); |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1763 | return strlen(mce_helper) + 1; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1764 | } |
| 1765 | |
Andi Kleen | 4a0b2b4 | 2008-07-01 18:48:41 +0200 | [diff] [blame] | 1766 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1767 | const char *buf, size_t siz) |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1768 | { |
| 1769 | char *p; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1770 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1771 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
| 1772 | mce_helper[sizeof(mce_helper)-1] = 0; |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1773 | p = strchr(mce_helper, '\n'); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1774 | |
Jan Beulich | e9084ec | 2009-07-16 09:45:11 +0100 | [diff] [blame] | 1775 | if (p) |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1776 | *p = 0; |
| 1777 | |
Jan Beulich | e9084ec | 2009-07-16 09:45:11 +0100 | [diff] [blame] | 1778 | return strlen(mce_helper) + !!p; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1779 | } |
| 1780 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1781 | static ssize_t set_ignore_ce(struct sys_device *s, |
| 1782 | struct sysdev_attribute *attr, |
| 1783 | const char *buf, size_t size) |
| 1784 | { |
| 1785 | u64 new; |
| 1786 | |
| 1787 | if (strict_strtoull(buf, 0, &new) < 0) |
| 1788 | return -EINVAL; |
| 1789 | |
| 1790 | if (mce_ignore_ce ^ !!new) { |
| 1791 | if (new) { |
| 1792 | /* disable ce features */ |
| 1793 | on_each_cpu(mce_disable_ce, (void *)1, 1); |
| 1794 | mce_ignore_ce = 1; |
| 1795 | } else { |
| 1796 | /* enable ce features */ |
| 1797 | mce_ignore_ce = 0; |
| 1798 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
| 1799 | } |
| 1800 | } |
| 1801 | return size; |
| 1802 | } |
| 1803 | |
| 1804 | static ssize_t set_cmci_disabled(struct sys_device *s, |
| 1805 | struct sysdev_attribute *attr, |
| 1806 | const char *buf, size_t size) |
| 1807 | { |
| 1808 | u64 new; |
| 1809 | |
| 1810 | if (strict_strtoull(buf, 0, &new) < 0) |
| 1811 | return -EINVAL; |
| 1812 | |
| 1813 | if (mce_cmci_disabled ^ !!new) { |
| 1814 | if (new) { |
| 1815 | /* disable cmci */ |
| 1816 | on_each_cpu(mce_disable_ce, NULL, 1); |
| 1817 | mce_cmci_disabled = 1; |
| 1818 | } else { |
| 1819 | /* enable cmci */ |
| 1820 | mce_cmci_disabled = 0; |
| 1821 | on_each_cpu(mce_enable_ce, NULL, 1); |
| 1822 | } |
| 1823 | } |
| 1824 | return size; |
| 1825 | } |
| 1826 | |
Andi Kleen | b56f642 | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 1827 | static ssize_t store_int_with_restart(struct sys_device *s, |
| 1828 | struct sysdev_attribute *attr, |
| 1829 | const char *buf, size_t size) |
| 1830 | { |
| 1831 | ssize_t ret = sysdev_store_int(s, attr, buf, size); |
| 1832 | mce_restart(); |
| 1833 | return ret; |
| 1834 | } |
| 1835 | |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1836 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
Andi Kleen | d95d62c | 2008-07-01 18:48:43 +0200 | [diff] [blame] | 1837 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1838 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1839 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1840 | |
Andi Kleen | b56f642 | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 1841 | static struct sysdev_ext_attribute attr_check_interval = { |
| 1842 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, |
| 1843 | store_int_with_restart), |
| 1844 | &check_interval |
| 1845 | }; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1846 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1847 | static struct sysdev_ext_attribute attr_ignore_ce = { |
| 1848 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), |
| 1849 | &mce_ignore_ce |
| 1850 | }; |
| 1851 | |
| 1852 | static struct sysdev_ext_attribute attr_cmci_disabled = { |
Yinghai Lu | 74b602c | 2009-06-17 14:43:32 -0700 | [diff] [blame] | 1853 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1854 | &mce_cmci_disabled |
| 1855 | }; |
| 1856 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1857 | static struct sysdev_attribute *mce_attrs[] = { |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1858 | &attr_tolerant.attr, |
| 1859 | &attr_check_interval.attr, |
| 1860 | &attr_trigger, |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1861 | &attr_monarch_timeout.attr, |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1862 | &attr_dont_log_ce.attr, |
| 1863 | &attr_ignore_ce.attr, |
| 1864 | &attr_cmci_disabled.attr, |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1865 | NULL |
| 1866 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1867 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1868 | static cpumask_var_t mce_dev_initialized; |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 1869 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1870 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1871 | static __cpuinit int mce_create_device(unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1872 | { |
| 1873 | int err; |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1874 | int i, j; |
Mike Travis | 92cb761 | 2007-10-19 20:35:04 +0200 | [diff] [blame] | 1875 | |
Andreas Herrmann | 9036755 | 2007-11-07 02:12:58 +0100 | [diff] [blame] | 1876 | if (!mce_available(&boot_cpu_data)) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1877 | return -EIO; |
| 1878 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1879 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
| 1880 | per_cpu(mce_dev, cpu).id = cpu; |
| 1881 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1882 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1883 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1884 | if (err) |
| 1885 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1886 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1887 | for (i = 0; mce_attrs[i]; i++) { |
| 1888 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1889 | if (err) |
| 1890 | goto error; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1891 | } |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1892 | for (j = 0; j < banks; j++) { |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1893 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1894 | &mce_banks[j].attr); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1895 | if (err) |
| 1896 | goto error2; |
| 1897 | } |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1898 | cpumask_set_cpu(cpu, mce_dev_initialized); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1899 | |
| 1900 | return 0; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1901 | error2: |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1902 | while (--j >= 0) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1903 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1904 | error: |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1905 | while (--i >= 0) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1906 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1907 | |
| 1908 | sysdev_unregister(&per_cpu(mce_dev, cpu)); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1909 | |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1910 | return err; |
| 1911 | } |
| 1912 | |
Jan Beulich | 2d9cd6c | 2008-08-29 13:15:04 +0100 | [diff] [blame] | 1913 | static __cpuinit void mce_remove_device(unsigned int cpu) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1914 | { |
Shaohua Li | 73ca535 | 2006-01-11 22:43:06 +0100 | [diff] [blame] | 1915 | int i; |
| 1916 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1917 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 1918 | return; |
| 1919 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1920 | for (i = 0; mce_attrs[i]; i++) |
| 1921 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
| 1922 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1923 | for (i = 0; i < banks; i++) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1924 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1925 | |
| 1926 | sysdev_unregister(&per_cpu(mce_dev, cpu)); |
| 1927 | cpumask_clear_cpu(cpu, mce_dev_initialized); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1928 | } |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1929 | |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1930 | /* Make sure there are no machine checks on offlined CPUs. */ |
H. Peter Anvin | ec5b3d3 | 2009-02-23 14:01:04 -0800 | [diff] [blame] | 1931 | static void mce_disable_cpu(void *h) |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1932 | { |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1933 | unsigned long action = *(unsigned long *)h; |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1934 | int i; |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1935 | |
| 1936 | if (!mce_available(¤t_cpu_data)) |
| 1937 | return; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1938 | if (!(action & CPU_TASKS_FROZEN)) |
| 1939 | cmci_clear(); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1940 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1941 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1942 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1943 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1944 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1945 | } |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1946 | } |
| 1947 | |
H. Peter Anvin | ec5b3d3 | 2009-02-23 14:01:04 -0800 | [diff] [blame] | 1948 | static void mce_reenable_cpu(void *h) |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1949 | { |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1950 | unsigned long action = *(unsigned long *)h; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1951 | int i; |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1952 | |
| 1953 | if (!mce_available(¤t_cpu_data)) |
| 1954 | return; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1955 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1956 | if (!(action & CPU_TASKS_FROZEN)) |
| 1957 | cmci_reenable(); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1958 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1959 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1960 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1961 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1962 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1963 | } |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 1964 | } |
| 1965 | |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1966 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1967 | static int __cpuinit |
| 1968 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1969 | { |
| 1970 | unsigned int cpu = (unsigned long)hcpu; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1971 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1972 | |
| 1973 | switch (action) { |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 1974 | case CPU_ONLINE: |
| 1975 | case CPU_ONLINE_FROZEN: |
| 1976 | mce_create_device(cpu); |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 1977 | if (threshold_cpu_callback) |
| 1978 | threshold_cpu_callback(action, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1979 | break; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1980 | case CPU_DEAD: |
Rafael J. Wysocki | 8bb7844 | 2007-05-09 02:35:10 -0700 | [diff] [blame] | 1981 | case CPU_DEAD_FROZEN: |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 1982 | if (threshold_cpu_callback) |
| 1983 | threshold_cpu_callback(action, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1984 | mce_remove_device(cpu); |
| 1985 | break; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1986 | case CPU_DOWN_PREPARE: |
| 1987 | case CPU_DOWN_PREPARE_FROZEN: |
| 1988 | del_timer_sync(t); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1989 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1990 | break; |
| 1991 | case CPU_DOWN_FAILED: |
| 1992 | case CPU_DOWN_FAILED_FROZEN: |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1993 | t->expires = round_jiffies(jiffies + |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1994 | __get_cpu_var(mce_next_interval)); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1995 | add_timer_on(t, cpu); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 1996 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
| 1997 | break; |
| 1998 | case CPU_POST_DEAD: |
| 1999 | /* intentionally ignoring frozen here */ |
| 2000 | cmci_rediscover(cpu); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 2001 | break; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2002 | } |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 2003 | return NOTIFY_OK; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2004 | } |
| 2005 | |
Sam Ravnborg | 1e35669 | 2008-01-30 13:33:36 +0100 | [diff] [blame] | 2006 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2007 | .notifier_call = mce_cpu_callback, |
| 2008 | }; |
| 2009 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2010 | static __init void mce_init_banks(void) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2011 | { |
| 2012 | int i; |
| 2013 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2014 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2015 | struct mce_bank *b = &mce_banks[i]; |
| 2016 | struct sysdev_attribute *a = &b->attr; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2017 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2018 | a->attr.name = b->attrname; |
| 2019 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2020 | |
| 2021 | a->attr.mode = 0644; |
| 2022 | a->show = show_bank; |
| 2023 | a->store = set_bank; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2024 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2025 | } |
| 2026 | |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2027 | static __init int mce_init_device(void) |
| 2028 | { |
| 2029 | int err; |
| 2030 | int i = 0; |
| 2031 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2032 | if (!mce_available(&boot_cpu_data)) |
| 2033 | return -EIO; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2034 | |
Yinghai Lu | e92fae0 | 2009-06-17 16:21:33 -0700 | [diff] [blame] | 2035 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
Rusty Russell | 996867d | 2009-03-13 14:49:51 +1030 | [diff] [blame] | 2036 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2037 | mce_init_banks(); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2038 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2039 | err = sysdev_class_register(&mce_sysclass); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 2040 | if (err) |
| 2041 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2042 | |
| 2043 | for_each_online_cpu(i) { |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 2044 | err = mce_create_device(i); |
| 2045 | if (err) |
| 2046 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2047 | } |
| 2048 | |
Chandra Seetharaman | be6b5a3 | 2006-07-30 03:03:37 -0700 | [diff] [blame] | 2049 | register_hotcpu_notifier(&mce_cpu_notifier); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2050 | misc_register(&mce_log_device); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2051 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2052 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2053 | } |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2054 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2055 | device_initcall(mce_init_device); |
Ingo Molnar | a988d33 | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 2056 | |
Andi Kleen | d7c3c9a | 2009-04-28 23:07:25 +0200 | [diff] [blame] | 2057 | /* |
| 2058 | * Old style boot options parsing. Only for compatibility. |
| 2059 | */ |
| 2060 | static int __init mcheck_disable(char *str) |
| 2061 | { |
| 2062 | mce_disabled = 1; |
| 2063 | return 1; |
| 2064 | } |
| 2065 | __setup("nomce", mcheck_disable); |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 2066 | |
| 2067 | #ifdef CONFIG_DEBUG_FS |
| 2068 | struct dentry *mce_get_debugfs_dir(void) |
| 2069 | { |
| 2070 | static struct dentry *dmce; |
| 2071 | |
| 2072 | if (!dmce) |
| 2073 | dmce = debugfs_create_dir("mce", NULL); |
| 2074 | |
| 2075 | return dmce; |
| 2076 | } |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 2077 | |
| 2078 | static void mce_reset(void) |
| 2079 | { |
| 2080 | cpu_missing = 0; |
| 2081 | atomic_set(&mce_fake_paniced, 0); |
| 2082 | atomic_set(&mce_executing, 0); |
| 2083 | atomic_set(&mce_callin, 0); |
| 2084 | atomic_set(&global_nwo, 0); |
| 2085 | } |
| 2086 | |
| 2087 | static int fake_panic_get(void *data, u64 *val) |
| 2088 | { |
| 2089 | *val = fake_panic; |
| 2090 | return 0; |
| 2091 | } |
| 2092 | |
| 2093 | static int fake_panic_set(void *data, u64 val) |
| 2094 | { |
| 2095 | mce_reset(); |
| 2096 | fake_panic = val; |
| 2097 | return 0; |
| 2098 | } |
| 2099 | |
| 2100 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
| 2101 | fake_panic_set, "%llu\n"); |
| 2102 | |
| 2103 | static int __init mce_debugfs_init(void) |
| 2104 | { |
| 2105 | struct dentry *dmce, *ffake_panic; |
| 2106 | |
| 2107 | dmce = mce_get_debugfs_dir(); |
| 2108 | if (!dmce) |
| 2109 | return -ENOMEM; |
| 2110 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, |
| 2111 | &fake_panic_fops); |
| 2112 | if (!ffake_panic) |
| 2113 | return -ENOMEM; |
| 2114 | |
| 2115 | return 0; |
| 2116 | } |
| 2117 | late_initcall(mce_debugfs_init); |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 2118 | #endif |