Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Dave Jones | f4432c5 | 2008-10-20 13:31:45 -0400 | [diff] [blame^] | 2 | * Athlon specific Machine Check Exception Reporting |
| 3 | * (C) Copyright 2002 Dave Jones <davej@redhat.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/types.h> |
| 8 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/smp.h> |
| 11 | |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 12 | #include <asm/processor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/system.h> |
| 14 | #include <asm/msr.h> |
| 15 | |
| 16 | #include "mce.h" |
| 17 | |
| 18 | /* Machine Check Handler For AMD Athlon/Duron */ |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 19 | static void k7_machine_check(struct pt_regs *regs, long error_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | { |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 21 | int recover = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | u32 alow, ahigh, high, low; |
| 23 | u32 mcgstl, mcgsth; |
| 24 | int i; |
| 25 | |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 26 | rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | if (mcgstl & (1<<0)) /* Recoverable ? */ |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 28 | recover = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 30 | printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | smp_processor_id(), mcgsth, mcgstl); |
| 32 | |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 33 | for (i = 1; i < nr_mce_banks; i++) { |
Andrew Morton | 7271339 | 2008-01-30 13:32:13 +0100 | [diff] [blame] | 34 | rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | if (high&(1<<31)) { |
Min Zhang | 9e8b6d9 | 2008-01-30 13:32:11 +0100 | [diff] [blame] | 36 | char misc[20]; |
| 37 | char addr[24]; |
| 38 | misc[0] = addr[0] = '\0'; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | if (high & (1<<29)) |
| 40 | recover |= 1; |
| 41 | if (high & (1<<25)) |
| 42 | recover |= 2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | high &= ~(1<<31); |
| 44 | if (high & (1<<27)) { |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 45 | rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); |
| 46 | snprintf(misc, 20, "[%08x%08x]", ahigh, alow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | } |
| 48 | if (high & (1<<26)) { |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 49 | rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh); |
| 50 | snprintf(addr, 24, " at %08x%08x", ahigh, alow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | } |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 52 | printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", |
Min Zhang | 9e8b6d9 | 2008-01-30 13:32:11 +0100 | [diff] [blame] | 53 | smp_processor_id(), i, high, low, misc, addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | /* Clear it */ |
Andrew Morton | b912a1c | 2008-01-30 13:32:12 +0100 | [diff] [blame] | 55 | wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | /* Serialize */ |
| 57 | wmb(); |
| 58 | add_taint(TAINT_MACHINE_CHECK); |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | if (recover&2) |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 63 | panic("CPU context corrupt"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | if (recover&1) |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 65 | panic("Unable to continue"); |
| 66 | printk(KERN_EMERG "Attempting to continue.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | mcgstl &= ~(1<<2); |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 68 | wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | |
| 72 | /* AMD K7 machine check is Intel like */ |
Shaohua Li | 31ab269 | 2005-11-07 00:58:42 -0800 | [diff] [blame] | 73 | void amd_mcheck_init(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | { |
| 75 | u32 l, h; |
| 76 | int i; |
| 77 | |
Joachim Deguara | 2f3c30e | 2007-05-02 19:27:18 +0200 | [diff] [blame] | 78 | if (!cpu_has(c, X86_FEATURE_MCE)) |
| 79 | return; |
| 80 | |
Andi Kleen | c12ceb7 | 2007-05-21 14:31:47 +0200 | [diff] [blame] | 81 | machine_check_vector = k7_machine_check; |
| 82 | wmb(); |
| 83 | |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 84 | printk(KERN_INFO "Intel machine check architecture supported.\n"); |
| 85 | rdmsr(MSR_IA32_MCG_CAP, l, h); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | if (l & (1<<8)) /* Control register present ? */ |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 87 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | nr_mce_banks = l & 0xff; |
| 89 | |
| 90 | /* Clear status for MC index 0 separately, we don't touch CTL, |
Andi Kleen | de90c5c | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 91 | * as some K7 Athlons cause spurious MCEs when its enabled. */ |
| 92 | if (boot_cpu_data.x86 == 6) { |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 93 | wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0); |
Andi Kleen | de90c5c | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 94 | i = 1; |
| 95 | } else |
| 96 | i = 0; |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 97 | for (; i < nr_mce_banks; i++) { |
| 98 | wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); |
| 99 | wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | } |
| 101 | |
Paolo Ciarrocchi | 5175676 | 2008-06-14 14:37:14 +0200 | [diff] [blame] | 102 | set_in_cr4(X86_CR4_MCE); |
| 103 | printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | smp_processor_id()); |
| 105 | } |