Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Intel pinctrl/GPIO core driver. |
| 3 | * |
| 4 | * Copyright (C) 2015, Intel Corporation |
| 5 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> |
| 6 | * Mika Westerberg <mika.westerberg@linux.intel.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/acpi.h> |
| 16 | #include <linux/gpio.h> |
| 17 | #include <linux/gpio/driver.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/pm.h> |
| 20 | #include <linux/pinctrl/pinctrl.h> |
| 21 | #include <linux/pinctrl/pinmux.h> |
| 22 | #include <linux/pinctrl/pinconf.h> |
| 23 | #include <linux/pinctrl/pinconf-generic.h> |
| 24 | |
| 25 | #include "pinctrl-intel.h" |
| 26 | |
| 27 | /* Maximum number of pads in each group */ |
| 28 | #define NPADS_IN_GPP 24 |
| 29 | |
| 30 | /* Offset from regs */ |
| 31 | #define PADBAR 0x00c |
| 32 | #define GPI_IS 0x100 |
| 33 | #define GPI_GPE_STS 0x140 |
| 34 | #define GPI_GPE_EN 0x160 |
| 35 | |
| 36 | #define PADOWN_BITS 4 |
| 37 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) |
| 38 | #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) |
| 39 | |
| 40 | /* Offset from pad_regs */ |
| 41 | #define PADCFG0 0x000 |
| 42 | #define PADCFG0_RXEVCFG_SHIFT 25 |
| 43 | #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) |
| 44 | #define PADCFG0_RXEVCFG_LEVEL 0 |
| 45 | #define PADCFG0_RXEVCFG_EDGE 1 |
| 46 | #define PADCFG0_RXEVCFG_DISABLED 2 |
| 47 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 |
| 48 | #define PADCFG0_RXINV BIT(23) |
| 49 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) |
| 50 | #define PADCFG0_GPIROUTSCI BIT(19) |
| 51 | #define PADCFG0_GPIROUTSMI BIT(18) |
| 52 | #define PADCFG0_GPIROUTNMI BIT(17) |
| 53 | #define PADCFG0_PMODE_SHIFT 10 |
| 54 | #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) |
| 55 | #define PADCFG0_GPIORXDIS BIT(9) |
| 56 | #define PADCFG0_GPIOTXDIS BIT(8) |
| 57 | #define PADCFG0_GPIORXSTATE BIT(1) |
| 58 | #define PADCFG0_GPIOTXSTATE BIT(0) |
| 59 | |
| 60 | #define PADCFG1 0x004 |
| 61 | #define PADCFG1_TERM_UP BIT(13) |
| 62 | #define PADCFG1_TERM_SHIFT 10 |
| 63 | #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) |
| 64 | #define PADCFG1_TERM_20K 4 |
| 65 | #define PADCFG1_TERM_2K 3 |
| 66 | #define PADCFG1_TERM_5K 2 |
| 67 | #define PADCFG1_TERM_1K 1 |
| 68 | |
| 69 | struct intel_pad_context { |
| 70 | u32 padcfg0; |
| 71 | u32 padcfg1; |
| 72 | }; |
| 73 | |
| 74 | struct intel_community_context { |
| 75 | u32 *intmask; |
| 76 | }; |
| 77 | |
| 78 | struct intel_pinctrl_context { |
| 79 | struct intel_pad_context *pads; |
| 80 | struct intel_community_context *communities; |
| 81 | }; |
| 82 | |
| 83 | /** |
| 84 | * struct intel_pinctrl - Intel pinctrl private structure |
| 85 | * @dev: Pointer to the device structure |
| 86 | * @lock: Lock to serialize register access |
| 87 | * @pctldesc: Pin controller description |
| 88 | * @pctldev: Pointer to the pin controller device |
| 89 | * @chip: GPIO chip in this pin controller |
| 90 | * @soc: SoC/PCH specific pin configuration data |
| 91 | * @communities: All communities in this pin controller |
| 92 | * @ncommunities: Number of communities in this pin controller |
| 93 | * @context: Configuration saved over system sleep |
| 94 | */ |
| 95 | struct intel_pinctrl { |
| 96 | struct device *dev; |
| 97 | spinlock_t lock; |
| 98 | struct pinctrl_desc pctldesc; |
| 99 | struct pinctrl_dev *pctldev; |
| 100 | struct gpio_chip chip; |
| 101 | const struct intel_pinctrl_soc_data *soc; |
| 102 | struct intel_community *communities; |
| 103 | size_t ncommunities; |
| 104 | struct intel_pinctrl_context context; |
| 105 | }; |
| 106 | |
| 107 | #define gpiochip_to_pinctrl(c) container_of(c, struct intel_pinctrl, chip) |
| 108 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
| 109 | |
| 110 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, |
| 111 | unsigned pin) |
| 112 | { |
| 113 | struct intel_community *community; |
| 114 | int i; |
| 115 | |
| 116 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 117 | community = &pctrl->communities[i]; |
| 118 | if (pin >= community->pin_base && |
| 119 | pin < community->pin_base + community->npins) |
| 120 | return community; |
| 121 | } |
| 122 | |
| 123 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); |
| 124 | return NULL; |
| 125 | } |
| 126 | |
| 127 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, |
| 128 | unsigned reg) |
| 129 | { |
| 130 | const struct intel_community *community; |
| 131 | unsigned padno; |
| 132 | |
| 133 | community = intel_get_community(pctrl, pin); |
| 134 | if (!community) |
| 135 | return NULL; |
| 136 | |
| 137 | padno = pin_to_padno(community, pin); |
| 138 | return community->pad_regs + reg + padno * 8; |
| 139 | } |
| 140 | |
| 141 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) |
| 142 | { |
| 143 | const struct intel_community *community; |
| 144 | unsigned padno, gpp, gpp_offset, offset; |
| 145 | void __iomem *padown; |
| 146 | |
| 147 | community = intel_get_community(pctrl, pin); |
| 148 | if (!community) |
| 149 | return false; |
| 150 | if (!community->padown_offset) |
| 151 | return true; |
| 152 | |
| 153 | padno = pin_to_padno(community, pin); |
| 154 | gpp = padno / NPADS_IN_GPP; |
| 155 | gpp_offset = padno % NPADS_IN_GPP; |
| 156 | offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4; |
| 157 | padown = community->regs + offset; |
| 158 | |
| 159 | return !(readl(padown) & PADOWN_MASK(padno)); |
| 160 | } |
| 161 | |
| 162 | static bool intel_pad_reserved_for_acpi(struct intel_pinctrl *pctrl, |
| 163 | unsigned pin) |
| 164 | { |
| 165 | const struct intel_community *community; |
| 166 | unsigned padno, gpp, offset; |
| 167 | void __iomem *hostown; |
| 168 | |
| 169 | community = intel_get_community(pctrl, pin); |
| 170 | if (!community) |
| 171 | return true; |
| 172 | if (!community->hostown_offset) |
| 173 | return false; |
| 174 | |
| 175 | padno = pin_to_padno(community, pin); |
| 176 | gpp = padno / NPADS_IN_GPP; |
| 177 | offset = community->hostown_offset + gpp * 4; |
| 178 | hostown = community->regs + offset; |
| 179 | |
| 180 | return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); |
| 181 | } |
| 182 | |
| 183 | static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) |
| 184 | { |
| 185 | struct intel_community *community; |
| 186 | unsigned padno, gpp, offset; |
| 187 | u32 value; |
| 188 | |
| 189 | community = intel_get_community(pctrl, pin); |
| 190 | if (!community) |
| 191 | return true; |
| 192 | if (!community->padcfglock_offset) |
| 193 | return false; |
| 194 | |
| 195 | padno = pin_to_padno(community, pin); |
| 196 | gpp = padno / NPADS_IN_GPP; |
| 197 | |
| 198 | /* |
| 199 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, |
| 200 | * the pad is considered unlocked. Any other case means that it is |
| 201 | * either fully or partially locked and we don't touch it. |
| 202 | */ |
| 203 | offset = community->padcfglock_offset + gpp * 8; |
| 204 | value = readl(community->regs + offset); |
| 205 | if (value & BIT(pin % NPADS_IN_GPP)) |
| 206 | return true; |
| 207 | |
| 208 | offset = community->padcfglock_offset + 4 + gpp * 8; |
| 209 | value = readl(community->regs + offset); |
| 210 | if (value & BIT(pin % NPADS_IN_GPP)) |
| 211 | return true; |
| 212 | |
| 213 | return false; |
| 214 | } |
| 215 | |
| 216 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) |
| 217 | { |
| 218 | return intel_pad_owned_by_host(pctrl, pin) && |
| 219 | !intel_pad_reserved_for_acpi(pctrl, pin) && |
| 220 | !intel_pad_locked(pctrl, pin); |
| 221 | } |
| 222 | |
| 223 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) |
| 224 | { |
| 225 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 226 | |
| 227 | return pctrl->soc->ngroups; |
| 228 | } |
| 229 | |
| 230 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, |
| 231 | unsigned group) |
| 232 | { |
| 233 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 234 | |
| 235 | return pctrl->soc->groups[group].name; |
| 236 | } |
| 237 | |
| 238 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, |
| 239 | const unsigned **pins, unsigned *npins) |
| 240 | { |
| 241 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 242 | |
| 243 | *pins = pctrl->soc->groups[group].pins; |
| 244 | *npins = pctrl->soc->groups[group].npins; |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
| 249 | unsigned pin) |
| 250 | { |
| 251 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 252 | u32 cfg0, cfg1, mode; |
| 253 | bool locked, acpi; |
| 254 | |
| 255 | if (!intel_pad_owned_by_host(pctrl, pin)) { |
| 256 | seq_puts(s, "not available"); |
| 257 | return; |
| 258 | } |
| 259 | |
| 260 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); |
| 261 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
| 262 | |
| 263 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; |
| 264 | if (!mode) |
| 265 | seq_puts(s, "GPIO "); |
| 266 | else |
| 267 | seq_printf(s, "mode %d ", mode); |
| 268 | |
| 269 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); |
| 270 | |
| 271 | locked = intel_pad_locked(pctrl, pin); |
| 272 | acpi = intel_pad_reserved_for_acpi(pctrl, pin); |
| 273 | |
| 274 | if (locked || acpi) { |
| 275 | seq_puts(s, " ["); |
| 276 | if (locked) { |
| 277 | seq_puts(s, "LOCKED"); |
| 278 | if (acpi) |
| 279 | seq_puts(s, ", "); |
| 280 | } |
| 281 | if (acpi) |
| 282 | seq_puts(s, "ACPI"); |
| 283 | seq_puts(s, "]"); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | static const struct pinctrl_ops intel_pinctrl_ops = { |
| 288 | .get_groups_count = intel_get_groups_count, |
| 289 | .get_group_name = intel_get_group_name, |
| 290 | .get_group_pins = intel_get_group_pins, |
| 291 | .pin_dbg_show = intel_pin_dbg_show, |
| 292 | }; |
| 293 | |
| 294 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) |
| 295 | { |
| 296 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 297 | |
| 298 | return pctrl->soc->nfunctions; |
| 299 | } |
| 300 | |
| 301 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, |
| 302 | unsigned function) |
| 303 | { |
| 304 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 305 | |
| 306 | return pctrl->soc->functions[function].name; |
| 307 | } |
| 308 | |
| 309 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, |
| 310 | unsigned function, |
| 311 | const char * const **groups, |
| 312 | unsigned * const ngroups) |
| 313 | { |
| 314 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 315 | |
| 316 | *groups = pctrl->soc->functions[function].groups; |
| 317 | *ngroups = pctrl->soc->functions[function].ngroups; |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, |
| 322 | unsigned group) |
| 323 | { |
| 324 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 325 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; |
| 326 | unsigned long flags; |
| 327 | int i; |
| 328 | |
| 329 | spin_lock_irqsave(&pctrl->lock, flags); |
| 330 | |
| 331 | /* |
| 332 | * All pins in the groups needs to be accessible and writable |
| 333 | * before we can enable the mux for this group. |
| 334 | */ |
| 335 | for (i = 0; i < grp->npins; i++) { |
| 336 | if (!intel_pad_usable(pctrl, grp->pins[i])) { |
| 337 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 338 | return -EBUSY; |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | /* Now enable the mux setting for each pin in the group */ |
| 343 | for (i = 0; i < grp->npins; i++) { |
| 344 | void __iomem *padcfg0; |
| 345 | u32 value; |
| 346 | |
| 347 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); |
| 348 | value = readl(padcfg0); |
| 349 | |
| 350 | value &= ~PADCFG0_PMODE_MASK; |
| 351 | value |= grp->mode << PADCFG0_PMODE_SHIFT; |
| 352 | |
| 353 | writel(value, padcfg0); |
| 354 | } |
| 355 | |
| 356 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
| 362 | struct pinctrl_gpio_range *range, |
| 363 | unsigned pin) |
| 364 | { |
| 365 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 366 | void __iomem *padcfg0; |
| 367 | unsigned long flags; |
| 368 | u32 value; |
| 369 | |
| 370 | spin_lock_irqsave(&pctrl->lock, flags); |
| 371 | |
| 372 | if (!intel_pad_usable(pctrl, pin)) { |
| 373 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 374 | return -EBUSY; |
| 375 | } |
| 376 | |
| 377 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 378 | /* Put the pad into GPIO mode */ |
| 379 | value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; |
| 380 | /* Disable SCI/SMI/NMI generation */ |
| 381 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); |
| 382 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); |
| 383 | /* Disable TX buffer and enable RX (this will be input) */ |
| 384 | value &= ~PADCFG0_GPIORXDIS; |
| 385 | value |= PADCFG0_GPIOTXDIS; |
| 386 | writel(value, padcfg0); |
| 387 | |
| 388 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 394 | struct pinctrl_gpio_range *range, |
| 395 | unsigned pin, bool input) |
| 396 | { |
| 397 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 398 | void __iomem *padcfg0; |
| 399 | unsigned long flags; |
| 400 | u32 value; |
| 401 | |
| 402 | spin_lock_irqsave(&pctrl->lock, flags); |
| 403 | |
| 404 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 405 | |
| 406 | value = readl(padcfg0); |
| 407 | if (input) |
| 408 | value |= PADCFG0_GPIOTXDIS; |
| 409 | else |
| 410 | value &= ~PADCFG0_GPIOTXDIS; |
| 411 | writel(value, padcfg0); |
| 412 | |
| 413 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | static const struct pinmux_ops intel_pinmux_ops = { |
| 419 | .get_functions_count = intel_get_functions_count, |
| 420 | .get_function_name = intel_get_function_name, |
| 421 | .get_function_groups = intel_get_function_groups, |
| 422 | .set_mux = intel_pinmux_set_mux, |
| 423 | .gpio_request_enable = intel_gpio_request_enable, |
| 424 | .gpio_set_direction = intel_gpio_set_direction, |
| 425 | }; |
| 426 | |
| 427 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
| 428 | unsigned long *config) |
| 429 | { |
| 430 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 431 | enum pin_config_param param = pinconf_to_config_param(*config); |
| 432 | u32 value, term; |
| 433 | u16 arg = 0; |
| 434 | |
| 435 | if (!intel_pad_owned_by_host(pctrl, pin)) |
| 436 | return -ENOTSUPP; |
| 437 | |
| 438 | value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
| 439 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; |
| 440 | |
| 441 | switch (param) { |
| 442 | case PIN_CONFIG_BIAS_DISABLE: |
| 443 | if (term) |
| 444 | return -EINVAL; |
| 445 | break; |
| 446 | |
| 447 | case PIN_CONFIG_BIAS_PULL_UP: |
| 448 | if (!term || !(value & PADCFG1_TERM_UP)) |
| 449 | return -EINVAL; |
| 450 | |
| 451 | switch (term) { |
| 452 | case PADCFG1_TERM_1K: |
| 453 | arg = 1000; |
| 454 | break; |
| 455 | case PADCFG1_TERM_2K: |
| 456 | arg = 2000; |
| 457 | break; |
| 458 | case PADCFG1_TERM_5K: |
| 459 | arg = 5000; |
| 460 | break; |
| 461 | case PADCFG1_TERM_20K: |
| 462 | arg = 20000; |
| 463 | break; |
| 464 | } |
| 465 | |
| 466 | break; |
| 467 | |
| 468 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 469 | if (!term || value & PADCFG1_TERM_UP) |
| 470 | return -EINVAL; |
| 471 | |
| 472 | switch (term) { |
| 473 | case PADCFG1_TERM_5K: |
| 474 | arg = 5000; |
| 475 | break; |
| 476 | case PADCFG1_TERM_20K: |
| 477 | arg = 20000; |
| 478 | break; |
| 479 | } |
| 480 | |
| 481 | break; |
| 482 | |
| 483 | default: |
| 484 | return -ENOTSUPP; |
| 485 | } |
| 486 | |
| 487 | *config = pinconf_to_config_packed(param, arg); |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, |
| 492 | unsigned long config) |
| 493 | { |
| 494 | unsigned param = pinconf_to_config_param(config); |
| 495 | unsigned arg = pinconf_to_config_argument(config); |
| 496 | void __iomem *padcfg1; |
| 497 | unsigned long flags; |
| 498 | int ret = 0; |
| 499 | u32 value; |
| 500 | |
| 501 | spin_lock_irqsave(&pctrl->lock, flags); |
| 502 | |
| 503 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
| 504 | value = readl(padcfg1); |
| 505 | |
| 506 | switch (param) { |
| 507 | case PIN_CONFIG_BIAS_DISABLE: |
| 508 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); |
| 509 | break; |
| 510 | |
| 511 | case PIN_CONFIG_BIAS_PULL_UP: |
| 512 | value &= ~PADCFG1_TERM_MASK; |
| 513 | |
| 514 | value |= PADCFG1_TERM_UP; |
| 515 | |
| 516 | switch (arg) { |
| 517 | case 20000: |
| 518 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; |
| 519 | break; |
| 520 | case 5000: |
| 521 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; |
| 522 | break; |
| 523 | case 2000: |
| 524 | value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; |
| 525 | break; |
| 526 | case 1000: |
| 527 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; |
| 528 | break; |
| 529 | default: |
| 530 | ret = -EINVAL; |
| 531 | } |
| 532 | |
| 533 | break; |
| 534 | |
| 535 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 536 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); |
| 537 | |
| 538 | switch (arg) { |
| 539 | case 20000: |
| 540 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; |
| 541 | break; |
| 542 | case 5000: |
| 543 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; |
| 544 | break; |
| 545 | default: |
| 546 | ret = -EINVAL; |
| 547 | } |
| 548 | |
| 549 | break; |
| 550 | } |
| 551 | |
| 552 | if (!ret) |
| 553 | writel(value, padcfg1); |
| 554 | |
| 555 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 556 | |
| 557 | return ret; |
| 558 | } |
| 559 | |
| 560 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
| 561 | unsigned long *configs, unsigned nconfigs) |
| 562 | { |
| 563 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 564 | int i, ret; |
| 565 | |
| 566 | if (!intel_pad_usable(pctrl, pin)) |
| 567 | return -ENOTSUPP; |
| 568 | |
| 569 | for (i = 0; i < nconfigs; i++) { |
| 570 | switch (pinconf_to_config_param(configs[i])) { |
| 571 | case PIN_CONFIG_BIAS_DISABLE: |
| 572 | case PIN_CONFIG_BIAS_PULL_UP: |
| 573 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 574 | ret = intel_config_set_pull(pctrl, pin, configs[i]); |
| 575 | if (ret) |
| 576 | return ret; |
| 577 | break; |
| 578 | |
| 579 | default: |
| 580 | return -ENOTSUPP; |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | static const struct pinconf_ops intel_pinconf_ops = { |
| 588 | .is_generic = true, |
| 589 | .pin_config_get = intel_config_get, |
| 590 | .pin_config_set = intel_config_set, |
| 591 | }; |
| 592 | |
| 593 | static const struct pinctrl_desc intel_pinctrl_desc = { |
| 594 | .pctlops = &intel_pinctrl_ops, |
| 595 | .pmxops = &intel_pinmux_ops, |
| 596 | .confops = &intel_pinconf_ops, |
| 597 | .owner = THIS_MODULE, |
| 598 | }; |
| 599 | |
| 600 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 601 | { |
| 602 | return pinctrl_request_gpio(chip->base + offset); |
| 603 | } |
| 604 | |
| 605 | static void intel_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 606 | { |
| 607 | pinctrl_free_gpio(chip->base + offset); |
| 608 | } |
| 609 | |
| 610 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 611 | { |
| 612 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); |
| 613 | void __iomem *reg; |
| 614 | |
| 615 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); |
| 616 | if (!reg) |
| 617 | return -EINVAL; |
| 618 | |
| 619 | return !!(readl(reg) & PADCFG0_GPIORXSTATE); |
| 620 | } |
| 621 | |
| 622 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 623 | { |
| 624 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); |
| 625 | void __iomem *reg; |
| 626 | |
| 627 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); |
| 628 | if (reg) { |
| 629 | unsigned long flags; |
| 630 | u32 padcfg0; |
| 631 | |
| 632 | spin_lock_irqsave(&pctrl->lock, flags); |
| 633 | padcfg0 = readl(reg); |
| 634 | if (value) |
| 635 | padcfg0 |= PADCFG0_GPIOTXSTATE; |
| 636 | else |
| 637 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; |
| 638 | writel(padcfg0, reg); |
| 639 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 644 | { |
| 645 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 646 | } |
| 647 | |
| 648 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 649 | int value) |
| 650 | { |
| 651 | intel_gpio_set(chip, offset, value); |
| 652 | return pinctrl_gpio_direction_output(chip->base + offset); |
| 653 | } |
| 654 | |
| 655 | static const struct gpio_chip intel_gpio_chip = { |
| 656 | .owner = THIS_MODULE, |
| 657 | .request = intel_gpio_request, |
| 658 | .free = intel_gpio_free, |
| 659 | .direction_input = intel_gpio_direction_input, |
| 660 | .direction_output = intel_gpio_direction_output, |
| 661 | .get = intel_gpio_get, |
| 662 | .set = intel_gpio_set, |
| 663 | }; |
| 664 | |
| 665 | static void intel_gpio_irq_ack(struct irq_data *d) |
| 666 | { |
| 667 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 668 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 669 | const struct intel_community *community; |
| 670 | unsigned pin = irqd_to_hwirq(d); |
| 671 | |
| 672 | spin_lock(&pctrl->lock); |
| 673 | |
| 674 | community = intel_get_community(pctrl, pin); |
| 675 | if (community) { |
| 676 | unsigned padno = pin_to_padno(community, pin); |
| 677 | unsigned gpp_offset = padno % NPADS_IN_GPP; |
| 678 | unsigned gpp = padno / NPADS_IN_GPP; |
| 679 | |
| 680 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); |
| 681 | } |
| 682 | |
| 683 | spin_unlock(&pctrl->lock); |
| 684 | } |
| 685 | |
| 686 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) |
| 687 | { |
| 688 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 689 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 690 | const struct intel_community *community; |
| 691 | unsigned pin = irqd_to_hwirq(d); |
| 692 | unsigned long flags; |
| 693 | |
| 694 | spin_lock_irqsave(&pctrl->lock, flags); |
| 695 | |
| 696 | community = intel_get_community(pctrl, pin); |
| 697 | if (community) { |
| 698 | unsigned padno = pin_to_padno(community, pin); |
| 699 | unsigned gpp_offset = padno % NPADS_IN_GPP; |
| 700 | unsigned gpp = padno / NPADS_IN_GPP; |
| 701 | void __iomem *reg; |
| 702 | u32 value; |
| 703 | |
| 704 | reg = community->regs + community->ie_offset + gpp * 4; |
| 705 | value = readl(reg); |
| 706 | if (mask) |
| 707 | value &= ~BIT(gpp_offset); |
| 708 | else |
| 709 | value |= BIT(gpp_offset); |
| 710 | writel(value, reg); |
| 711 | } |
| 712 | |
| 713 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 714 | } |
| 715 | |
| 716 | static void intel_gpio_irq_mask(struct irq_data *d) |
| 717 | { |
| 718 | intel_gpio_irq_mask_unmask(d, true); |
| 719 | } |
| 720 | |
| 721 | static void intel_gpio_irq_unmask(struct irq_data *d) |
| 722 | { |
| 723 | intel_gpio_irq_mask_unmask(d, false); |
| 724 | } |
| 725 | |
| 726 | static int intel_gpio_irq_type(struct irq_data *d, unsigned type) |
| 727 | { |
| 728 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 729 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 730 | unsigned pin = irqd_to_hwirq(d); |
| 731 | unsigned long flags; |
| 732 | void __iomem *reg; |
| 733 | u32 value; |
| 734 | |
| 735 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 736 | if (!reg) |
| 737 | return -EINVAL; |
| 738 | |
| 739 | spin_lock_irqsave(&pctrl->lock, flags); |
| 740 | |
| 741 | value = readl(reg); |
| 742 | |
| 743 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); |
| 744 | |
| 745 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
| 746 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; |
| 747 | } else if (type & IRQ_TYPE_EDGE_FALLING) { |
| 748 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; |
| 749 | value |= PADCFG0_RXINV; |
| 750 | } else if (type & IRQ_TYPE_EDGE_RISING) { |
| 751 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; |
| 752 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
| 753 | value |= PADCFG0_RXINV; |
| 754 | } else { |
| 755 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; |
| 756 | } |
| 757 | |
| 758 | writel(value, reg); |
| 759 | |
| 760 | if (type & IRQ_TYPE_EDGE_BOTH) |
Thomas Gleixner | fc756bc | 2015-06-23 15:52:45 +0200 | [diff] [blame] | 761 | irq_set_handler_locked(d, handle_edge_irq); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 762 | else if (type & IRQ_TYPE_LEVEL_MASK) |
Thomas Gleixner | fc756bc | 2015-06-23 15:52:45 +0200 | [diff] [blame] | 763 | irq_set_handler_locked(d, handle_level_irq); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 764 | |
| 765 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) |
| 771 | { |
| 772 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 773 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 774 | const struct intel_community *community; |
| 775 | unsigned pin = irqd_to_hwirq(d); |
| 776 | unsigned padno, gpp, gpp_offset; |
| 777 | u32 gpe_en; |
| 778 | |
| 779 | community = intel_get_community(pctrl, pin); |
| 780 | if (!community) |
| 781 | return -EINVAL; |
| 782 | |
| 783 | padno = pin_to_padno(community, pin); |
| 784 | gpp = padno / NPADS_IN_GPP; |
| 785 | gpp_offset = padno % NPADS_IN_GPP; |
| 786 | |
| 787 | /* Clear the existing wake status */ |
| 788 | writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); |
| 789 | |
| 790 | /* |
| 791 | * The controller will generate wake when GPE of the corresponding |
| 792 | * pad is enabled and it is not routed to SCI (GPIROUTSCI is not |
| 793 | * set). |
| 794 | */ |
| 795 | gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); |
| 796 | if (on) |
| 797 | gpe_en |= BIT(gpp_offset); |
| 798 | else |
| 799 | gpe_en &= ~BIT(gpp_offset); |
| 800 | writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); |
| 801 | |
| 802 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
| 803 | return 0; |
| 804 | } |
| 805 | |
| 806 | static void intel_gpio_community_irq_handler(struct gpio_chip *gc, |
| 807 | const struct intel_community *community) |
| 808 | { |
| 809 | int gpp; |
| 810 | |
| 811 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 812 | unsigned long pending, enabled, gpp_offset; |
| 813 | |
| 814 | pending = readl(community->regs + GPI_IS + gpp * 4); |
| 815 | enabled = readl(community->regs + community->ie_offset + |
| 816 | gpp * 4); |
| 817 | |
| 818 | /* Only interrupts that are enabled */ |
| 819 | pending &= enabled; |
| 820 | |
| 821 | for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { |
| 822 | unsigned padno, irq; |
| 823 | |
| 824 | /* |
| 825 | * The last group in community can have less pins |
| 826 | * than NPADS_IN_GPP. |
| 827 | */ |
| 828 | padno = gpp_offset + gpp * NPADS_IN_GPP; |
| 829 | if (padno >= community->npins) |
| 830 | break; |
| 831 | |
| 832 | irq = irq_find_mapping(gc->irqdomain, |
| 833 | community->pin_base + padno); |
| 834 | generic_handle_irq(irq); |
| 835 | } |
| 836 | } |
| 837 | } |
| 838 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 839 | static void intel_gpio_irq_handler(struct irq_desc *desc) |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 840 | { |
| 841 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
| 842 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
Jiang Liu | 5663bb2 | 2015-06-04 12:13:16 +0800 | [diff] [blame] | 843 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 844 | int i; |
| 845 | |
| 846 | chained_irq_enter(chip, desc); |
| 847 | |
| 848 | /* Need to check all communities for pending interrupts */ |
| 849 | for (i = 0; i < pctrl->ncommunities; i++) |
| 850 | intel_gpio_community_irq_handler(gc, &pctrl->communities[i]); |
| 851 | |
| 852 | chained_irq_exit(chip, desc); |
| 853 | } |
| 854 | |
| 855 | static struct irq_chip intel_gpio_irqchip = { |
| 856 | .name = "intel-gpio", |
| 857 | .irq_ack = intel_gpio_irq_ack, |
| 858 | .irq_mask = intel_gpio_irq_mask, |
| 859 | .irq_unmask = intel_gpio_irq_unmask, |
| 860 | .irq_set_type = intel_gpio_irq_type, |
| 861 | .irq_set_wake = intel_gpio_irq_wake, |
| 862 | }; |
| 863 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 864 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
| 865 | { |
| 866 | int ret; |
| 867 | |
| 868 | pctrl->chip = intel_gpio_chip; |
| 869 | |
| 870 | pctrl->chip.ngpio = pctrl->soc->npins; |
| 871 | pctrl->chip.label = dev_name(pctrl->dev); |
| 872 | pctrl->chip.dev = pctrl->dev; |
| 873 | pctrl->chip.base = -1; |
| 874 | |
| 875 | ret = gpiochip_add(&pctrl->chip); |
| 876 | if (ret) { |
| 877 | dev_err(pctrl->dev, "failed to register gpiochip\n"); |
| 878 | return ret; |
| 879 | } |
| 880 | |
| 881 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), |
| 882 | 0, 0, pctrl->soc->npins); |
| 883 | if (ret) { |
| 884 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); |
| 885 | gpiochip_remove(&pctrl->chip); |
| 886 | return ret; |
| 887 | } |
| 888 | |
| 889 | ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, |
| 890 | handle_simple_irq, IRQ_TYPE_NONE); |
| 891 | if (ret) { |
| 892 | dev_err(pctrl->dev, "failed to add irqchip\n"); |
| 893 | gpiochip_remove(&pctrl->chip); |
| 894 | return ret; |
| 895 | } |
| 896 | |
| 897 | gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, |
| 898 | intel_gpio_irq_handler); |
| 899 | return 0; |
| 900 | } |
| 901 | |
| 902 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) |
| 903 | { |
| 904 | #ifdef CONFIG_PM_SLEEP |
| 905 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; |
| 906 | struct intel_community_context *communities; |
| 907 | struct intel_pad_context *pads; |
| 908 | int i; |
| 909 | |
| 910 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); |
| 911 | if (!pads) |
| 912 | return -ENOMEM; |
| 913 | |
| 914 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, |
| 915 | sizeof(*communities), GFP_KERNEL); |
| 916 | if (!communities) |
| 917 | return -ENOMEM; |
| 918 | |
| 919 | |
| 920 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 921 | struct intel_community *community = &pctrl->communities[i]; |
| 922 | u32 *intmask; |
| 923 | |
| 924 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, |
| 925 | sizeof(*intmask), GFP_KERNEL); |
| 926 | if (!intmask) |
| 927 | return -ENOMEM; |
| 928 | |
| 929 | communities[i].intmask = intmask; |
| 930 | } |
| 931 | |
| 932 | pctrl->context.pads = pads; |
| 933 | pctrl->context.communities = communities; |
| 934 | #endif |
| 935 | |
| 936 | return 0; |
| 937 | } |
| 938 | |
| 939 | int intel_pinctrl_probe(struct platform_device *pdev, |
| 940 | const struct intel_pinctrl_soc_data *soc_data) |
| 941 | { |
| 942 | struct intel_pinctrl *pctrl; |
| 943 | int i, ret, irq; |
| 944 | |
| 945 | if (!soc_data) |
| 946 | return -EINVAL; |
| 947 | |
| 948 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); |
| 949 | if (!pctrl) |
| 950 | return -ENOMEM; |
| 951 | |
| 952 | pctrl->dev = &pdev->dev; |
| 953 | pctrl->soc = soc_data; |
| 954 | spin_lock_init(&pctrl->lock); |
| 955 | |
| 956 | /* |
| 957 | * Make a copy of the communities which we can use to hold pointers |
| 958 | * to the registers. |
| 959 | */ |
| 960 | pctrl->ncommunities = pctrl->soc->ncommunities; |
| 961 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, |
| 962 | sizeof(*pctrl->communities), GFP_KERNEL); |
| 963 | if (!pctrl->communities) |
| 964 | return -ENOMEM; |
| 965 | |
| 966 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 967 | struct intel_community *community = &pctrl->communities[i]; |
| 968 | struct resource *res; |
| 969 | void __iomem *regs; |
| 970 | u32 padbar; |
| 971 | |
| 972 | *community = pctrl->soc->communities[i]; |
| 973 | |
| 974 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
| 975 | community->barno); |
| 976 | regs = devm_ioremap_resource(&pdev->dev, res); |
| 977 | if (IS_ERR(regs)) |
| 978 | return PTR_ERR(regs); |
| 979 | |
| 980 | /* Read offset of the pad configuration registers */ |
| 981 | padbar = readl(regs + PADBAR); |
| 982 | |
| 983 | community->regs = regs; |
| 984 | community->pad_regs = regs + padbar; |
| 985 | community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); |
| 986 | } |
| 987 | |
| 988 | irq = platform_get_irq(pdev, 0); |
| 989 | if (irq < 0) { |
| 990 | dev_err(&pdev->dev, "failed to get interrupt number\n"); |
| 991 | return irq; |
| 992 | } |
| 993 | |
| 994 | ret = intel_pinctrl_pm_init(pctrl); |
| 995 | if (ret) |
| 996 | return ret; |
| 997 | |
| 998 | pctrl->pctldesc = intel_pinctrl_desc; |
| 999 | pctrl->pctldesc.name = dev_name(&pdev->dev); |
| 1000 | pctrl->pctldesc.pins = pctrl->soc->pins; |
| 1001 | pctrl->pctldesc.npins = pctrl->soc->npins; |
| 1002 | |
| 1003 | pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1004 | if (IS_ERR(pctrl->pctldev)) { |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1005 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1006 | return PTR_ERR(pctrl->pctldev); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1007 | } |
| 1008 | |
| 1009 | ret = intel_gpio_probe(pctrl, irq); |
| 1010 | if (ret) { |
| 1011 | pinctrl_unregister(pctrl->pctldev); |
| 1012 | return ret; |
| 1013 | } |
| 1014 | |
| 1015 | platform_set_drvdata(pdev, pctrl); |
| 1016 | |
| 1017 | return 0; |
| 1018 | } |
| 1019 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe); |
| 1020 | |
| 1021 | int intel_pinctrl_remove(struct platform_device *pdev) |
| 1022 | { |
| 1023 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1024 | |
| 1025 | gpiochip_remove(&pctrl->chip); |
| 1026 | pinctrl_unregister(pctrl->pctldev); |
| 1027 | |
| 1028 | return 0; |
| 1029 | } |
| 1030 | EXPORT_SYMBOL_GPL(intel_pinctrl_remove); |
| 1031 | |
| 1032 | #ifdef CONFIG_PM_SLEEP |
| 1033 | int intel_pinctrl_suspend(struct device *dev) |
| 1034 | { |
| 1035 | struct platform_device *pdev = to_platform_device(dev); |
| 1036 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1037 | struct intel_community_context *communities; |
| 1038 | struct intel_pad_context *pads; |
| 1039 | int i; |
| 1040 | |
| 1041 | pads = pctrl->context.pads; |
| 1042 | for (i = 0; i < pctrl->soc->npins; i++) { |
| 1043 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; |
| 1044 | u32 val; |
| 1045 | |
| 1046 | if (!intel_pad_usable(pctrl, desc->number)) |
| 1047 | continue; |
| 1048 | |
| 1049 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); |
| 1050 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; |
| 1051 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); |
| 1052 | pads[i].padcfg1 = val; |
| 1053 | } |
| 1054 | |
| 1055 | communities = pctrl->context.communities; |
| 1056 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1057 | struct intel_community *community = &pctrl->communities[i]; |
| 1058 | void __iomem *base; |
| 1059 | unsigned gpp; |
| 1060 | |
| 1061 | base = community->regs + community->ie_offset; |
| 1062 | for (gpp = 0; gpp < community->ngpps; gpp++) |
| 1063 | communities[i].intmask[gpp] = readl(base + gpp * 4); |
| 1064 | } |
| 1065 | |
| 1066 | return 0; |
| 1067 | } |
| 1068 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); |
| 1069 | |
Mika Westerberg | f487bbf | 2015-10-13 17:51:25 +0300 | [diff] [blame^] | 1070 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
| 1071 | { |
| 1072 | size_t i; |
| 1073 | |
| 1074 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1075 | const struct intel_community *community; |
| 1076 | void __iomem *base; |
| 1077 | unsigned gpp; |
| 1078 | |
| 1079 | community = &pctrl->communities[i]; |
| 1080 | base = community->regs; |
| 1081 | |
| 1082 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 1083 | /* Mask and clear all interrupts */ |
| 1084 | writel(0, base + community->ie_offset + gpp * 4); |
| 1085 | writel(0xffff, base + GPI_IS + gpp * 4); |
| 1086 | } |
| 1087 | } |
| 1088 | } |
| 1089 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1090 | int intel_pinctrl_resume(struct device *dev) |
| 1091 | { |
| 1092 | struct platform_device *pdev = to_platform_device(dev); |
| 1093 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1094 | const struct intel_community_context *communities; |
| 1095 | const struct intel_pad_context *pads; |
| 1096 | int i; |
| 1097 | |
| 1098 | /* Mask all interrupts */ |
| 1099 | intel_gpio_irq_init(pctrl); |
| 1100 | |
| 1101 | pads = pctrl->context.pads; |
| 1102 | for (i = 0; i < pctrl->soc->npins; i++) { |
| 1103 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; |
| 1104 | void __iomem *padcfg; |
| 1105 | u32 val; |
| 1106 | |
| 1107 | if (!intel_pad_usable(pctrl, desc->number)) |
| 1108 | continue; |
| 1109 | |
| 1110 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); |
| 1111 | val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; |
| 1112 | if (val != pads[i].padcfg0) { |
| 1113 | writel(pads[i].padcfg0, padcfg); |
| 1114 | dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", |
| 1115 | desc->number, readl(padcfg)); |
| 1116 | } |
| 1117 | |
| 1118 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); |
| 1119 | val = readl(padcfg); |
| 1120 | if (val != pads[i].padcfg1) { |
| 1121 | writel(pads[i].padcfg1, padcfg); |
| 1122 | dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", |
| 1123 | desc->number, readl(padcfg)); |
| 1124 | } |
| 1125 | } |
| 1126 | |
| 1127 | communities = pctrl->context.communities; |
| 1128 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1129 | struct intel_community *community = &pctrl->communities[i]; |
| 1130 | void __iomem *base; |
| 1131 | unsigned gpp; |
| 1132 | |
| 1133 | base = community->regs + community->ie_offset; |
| 1134 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 1135 | writel(communities[i].intmask[gpp], base + gpp * 4); |
| 1136 | dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, |
| 1137 | readl(base + gpp * 4)); |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | return 0; |
| 1142 | } |
| 1143 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume); |
| 1144 | #endif |
| 1145 | |
| 1146 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); |
| 1147 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 1148 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); |
| 1149 | MODULE_LICENSE("GPL v2"); |