Shawn Guo | 53f9443 | 2012-08-22 21:36:30 +0800 | [diff] [blame] | 1 | * Clock bindings for Freescale i.MX23 |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Should be "fsl,imx23-clkctrl" |
| 5 | - reg: Address and length of the register set |
| 6 | - #clock-cells: Should be <1> |
| 7 | |
| 8 | The clock consumer should specify the desired clock by having the clock |
| 9 | ID in its "clocks" phandle cell. The following is a full list of i.MX23 |
| 10 | clocks and IDs. |
| 11 | |
| 12 | Clock ID |
| 13 | ------------------ |
| 14 | ref_xtal 0 |
| 15 | pll 1 |
| 16 | ref_cpu 2 |
| 17 | ref_emi 3 |
| 18 | ref_pix 4 |
| 19 | ref_io 5 |
| 20 | saif_sel 6 |
| 21 | lcdif_sel 7 |
| 22 | gpmi_sel 8 |
| 23 | ssp_sel 9 |
| 24 | emi_sel 10 |
| 25 | cpu 11 |
| 26 | etm_sel 12 |
| 27 | cpu_pll 13 |
| 28 | cpu_xtal 14 |
| 29 | hbus 15 |
| 30 | xbus 16 |
| 31 | lcdif_div 17 |
| 32 | ssp_div 18 |
| 33 | gpmi_div 19 |
| 34 | emi_pll 20 |
| 35 | emi_xtal 21 |
| 36 | etm_div 22 |
| 37 | saif_div 23 |
| 38 | clk32k_div 24 |
| 39 | rtc 25 |
| 40 | adc 26 |
| 41 | spdif_div 27 |
| 42 | clk32k 28 |
| 43 | dri 29 |
| 44 | pwm 30 |
| 45 | filt 31 |
| 46 | uart 32 |
| 47 | ssp 33 |
| 48 | gpmi 34 |
| 49 | spdif 35 |
| 50 | emi 36 |
| 51 | saif 37 |
| 52 | lcdif 38 |
| 53 | etm 39 |
| 54 | usb 40 |
Fabio Estevam | f589453 | 2012-09-22 13:54:55 -0300 | [diff] [blame] | 55 | usb_phy 41 |
Shawn Guo | 53f9443 | 2012-08-22 21:36:30 +0800 | [diff] [blame] | 56 | |
| 57 | Examples: |
| 58 | |
| 59 | clks: clkctrl@80040000 { |
| 60 | compatible = "fsl,imx23-clkctrl"; |
| 61 | reg = <0x80040000 0x2000>; |
| 62 | #clock-cells = <1>; |
Shawn Guo | 53f9443 | 2012-08-22 21:36:30 +0800 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | auart0: serial@8006c000 { |
| 66 | compatible = "fsl,imx23-auart"; |
| 67 | reg = <0x8006c000 0x2000>; |
| 68 | interrupts = <24 25 23>; |
| 69 | clocks = <&clks 32>; |
| 70 | status = "disabled"; |
| 71 | }; |