Paul Burton | fe4ef45 | 2015-05-24 16:11:34 +0100 | [diff] [blame] | 1 | Ingenic SoC CGU binding |
| 2 | |
| 3 | The CGU in an Ingenic SoC provides all the clocks generated on-chip. It |
| 4 | typically includes a variety of PLLs, multiplexers, dividers & gates in order |
| 5 | to provide many different clock signals derived from only 2 external source |
| 6 | clocks. |
| 7 | |
| 8 | Required properties: |
| 9 | - compatible : Should be "ingenic,<soctype>-cgu". |
| 10 | For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". |
| 11 | - reg : The address & length of the CGU registers. |
| 12 | - clocks : List of phandle & clock specifiers for clocks external to the CGU. |
| 13 | Two such external clocks should be specified - first the external crystal |
| 14 | "ext" and second the RTC clock source "rtc". |
| 15 | - clock-names : List of name strings for the external clocks. |
| 16 | - #clock-cells: Should be 1. |
| 17 | Clock consumers specify this argument to identify a clock. The valid values |
| 18 | may be found in <dt-bindings/clock/<soctype>-cgu.h>. |
| 19 | |
| 20 | Example SoC include file: |
| 21 | |
| 22 | / { |
| 23 | cgu: jz4740-cgu { |
| 24 | compatible = "ingenic,jz4740-cgu"; |
| 25 | reg = <0x10000000 0x100>; |
| 26 | #clock-cells = <1>; |
| 27 | }; |
| 28 | |
| 29 | uart0: serial@10030000 { |
| 30 | clocks = <&cgu JZ4740_CLK_UART0>; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | Example board file: |
| 35 | |
| 36 | / { |
| 37 | ext: clock@0 { |
| 38 | compatible = "fixed-clock"; |
| 39 | #clock-cells = <0>; |
| 40 | clock-frequency = <12000000>; |
| 41 | }; |
| 42 | |
| 43 | rtc: clock@1 { |
| 44 | compatible = "fixed-clock"; |
| 45 | #clock-cells = <0>; |
| 46 | clock-frequency = <32768>; |
| 47 | }; |
| 48 | |
| 49 | &cgu { |
| 50 | clocks = <&ext> <&rtc>; |
| 51 | clock-names: "ext", "rtc"; |
| 52 | }; |
| 53 | }; |