Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 1 | UniPhier clock controller |
| 2 | |
| 3 | |
| 4 | System clock |
| 5 | ------------ |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible: should be one of the following: |
| 9 | "socionext,uniphier-sld3-clock" - for sLD3 SoC. |
| 10 | "socionext,uniphier-ld4-clock" - for LD4 SoC. |
| 11 | "socionext,uniphier-pro4-clock" - for Pro4 SoC. |
| 12 | "socionext,uniphier-sld8-clock" - for sLD8 SoC. |
| 13 | "socionext,uniphier-pro5-clock" - for Pro5 SoC. |
| 14 | "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. |
| 15 | "socionext,uniphier-ld11-clock" - for LD11 SoC. |
| 16 | "socionext,uniphier-ld20-clock" - for LD20 SoC. |
| 17 | - #clock-cells: should be 1. |
| 18 | |
| 19 | Example: |
| 20 | |
| 21 | sysctrl@61840000 { |
| 22 | compatible = "socionext,uniphier-sysctrl", |
| 23 | "simple-mfd", "syscon"; |
| 24 | reg = <0x61840000 0x4000>; |
| 25 | |
| 26 | clock { |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 27 | compatible = "socionext,uniphier-ld11-clock"; |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 28 | #clock-cells = <1>; |
| 29 | }; |
| 30 | |
| 31 | other nodes ... |
| 32 | }; |
| 33 | |
| 34 | Provided clocks: |
| 35 | |
| 36 | 8: ST DMAC |
| 37 | 12: GIO (Giga bit stream I/O) |
| 38 | 14: USB3 ch0 host |
| 39 | 15: USB3 ch1 host |
| 40 | 16: USB3 ch0 PHY0 |
| 41 | 17: USB3 ch0 PHY1 |
| 42 | 20: USB3 ch1 PHY0 |
| 43 | 21: USB3 ch1 PHY1 |
| 44 | |
| 45 | |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 46 | Media I/O (MIO) clock, SD clock |
| 47 | ------------------------------- |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 48 | |
| 49 | Required properties: |
| 50 | - compatible: should be one of the following: |
| 51 | "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC. |
| 52 | "socionext,uniphier-ld4-mio-clock" - for LD4 SoC. |
| 53 | "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC. |
| 54 | "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC. |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 55 | "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC. |
| 56 | "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 57 | "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 58 | "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 59 | - #clock-cells: should be 1. |
| 60 | |
| 61 | Example: |
| 62 | |
| 63 | mioctrl@59810000 { |
| 64 | compatible = "socionext,uniphier-mioctrl", |
| 65 | "simple-mfd", "syscon"; |
| 66 | reg = <0x59810000 0x800>; |
| 67 | |
| 68 | clock { |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 69 | compatible = "socionext,uniphier-ld11-mio-clock"; |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 70 | #clock-cells = <1>; |
| 71 | }; |
| 72 | |
| 73 | other nodes ... |
| 74 | }; |
| 75 | |
| 76 | Provided clocks: |
| 77 | |
| 78 | 0: SD ch0 host |
| 79 | 1: eMMC host |
| 80 | 2: SD ch1 host |
| 81 | 7: MIO DMAC |
| 82 | 8: USB2 ch0 host |
| 83 | 9: USB2 ch1 host |
| 84 | 10: USB2 ch2 host |
| 85 | 11: USB2 ch3 host |
| 86 | 12: USB2 ch0 PHY |
| 87 | 13: USB2 ch1 PHY |
| 88 | 14: USB2 ch2 PHY |
| 89 | 15: USB2 ch3 PHY |
| 90 | |
| 91 | |
| 92 | Peripheral clock |
| 93 | ---------------- |
| 94 | |
| 95 | Required properties: |
| 96 | - compatible: should be one of the following: |
| 97 | "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC. |
| 98 | "socionext,uniphier-ld4-peri-clock" - for LD4 SoC. |
| 99 | "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC. |
| 100 | "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC. |
| 101 | "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC. |
| 102 | "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. |
| 103 | "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. |
| 104 | "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. |
| 105 | - #clock-cells: should be 1. |
| 106 | |
| 107 | Example: |
| 108 | |
| 109 | perictrl@59820000 { |
| 110 | compatible = "socionext,uniphier-perictrl", |
| 111 | "simple-mfd", "syscon"; |
| 112 | reg = <0x59820000 0x200>; |
| 113 | |
| 114 | clock { |
Masahiro Yamada | 5c6201e | 2016-10-19 17:22:07 +0900 | [diff] [blame] | 115 | compatible = "socionext,uniphier-ld11-peri-clock"; |
Masahiro Yamada | 7f4d3b5 | 2016-09-16 16:40:04 +0900 | [diff] [blame] | 116 | #clock-cells = <1>; |
| 117 | }; |
| 118 | |
| 119 | other nodes ... |
| 120 | }; |
| 121 | |
| 122 | Provided clocks: |
| 123 | |
| 124 | 0: UART ch0 |
| 125 | 1: UART ch1 |
| 126 | 2: UART ch2 |
| 127 | 3: UART ch3 |
| 128 | 4: I2C ch0 |
| 129 | 5: I2C ch1 |
| 130 | 6: I2C ch2 |
| 131 | 7: I2C ch3 |
| 132 | 8: I2C ch4 |
| 133 | 9: I2C ch5 |
| 134 | 10: I2C ch6 |