Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1 | * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX |
| 2 | |
| 3 | Required properties: |
Markus Pargmann | 63edea1 | 2014-02-16 20:10:55 +0100 | [diff] [blame] | 4 | - compatible : Should be one of |
| 5 | "fsl,imx25-sdma" |
| 6 | "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" |
| 7 | "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" |
| 8 | "fsl,imx51-sdma" |
| 9 | "fsl,imx53-sdma" |
| 10 | "fsl,imx6q-sdma" |
Fabio Estevam | b7d2648 | 2016-08-10 13:05:05 -0300 | [diff] [blame] | 11 | "fsl,imx7d-sdma" |
Geert Uytterhoeven | c1e0cff | 2014-03-11 11:23:48 +0100 | [diff] [blame] | 12 | The -to variants should be preferred since they allow to determine the |
Markus Pargmann | 63edea1 | 2014-02-16 20:10:55 +0100 | [diff] [blame] | 13 | correct ROM script addresses needed for the driver to work without additional |
| 14 | firmware. |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 15 | - reg : Should contain SDMA registers location and length |
| 16 | - interrupts : Should contain SDMA interrupt |
Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 17 | - #dma-cells : Must be <3>. |
| 18 | The first cell specifies the DMA request/event ID. See details below |
| 19 | about the second and third cell. |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 20 | - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM |
| 21 | scripts firmware |
| 22 | |
Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 23 | The second cell of dma phandle specifies the peripheral type of DMA transfer. |
| 24 | The full ID of peripheral types can be found below. |
| 25 | |
| 26 | ID transfer type |
| 27 | --------------------- |
| 28 | 0 MCU domain SSI |
| 29 | 1 Shared SSI |
| 30 | 2 MMC |
| 31 | 3 SDHC |
| 32 | 4 MCU domain UART |
| 33 | 5 Shared UART |
| 34 | 6 FIRI |
| 35 | 7 MCU domain CSPI |
| 36 | 8 Shared CSPI |
| 37 | 9 SIM |
| 38 | 10 ATA |
| 39 | 11 CCM |
| 40 | 12 External peripheral |
| 41 | 13 Memory Stick Host Controller |
| 42 | 14 Shared Memory Stick Host Controller |
| 43 | 15 DSP |
| 44 | 16 Memory |
| 45 | 17 FIFO type Memory |
| 46 | 18 SPDIF |
| 47 | 19 IPU Memory |
| 48 | 20 ASRC |
| 49 | 21 ESAI |
Nicolin Chen | 1a89557 | 2013-11-13 22:55:25 +0800 | [diff] [blame] | 50 | 22 SSI Dual FIFO (needs firmware ver >= 2) |
Nicolin Chen | f892afb | 2014-06-16 11:31:05 +0800 | [diff] [blame] | 51 | 23 Shared ASRC |
Nicolin Chen | 29aebfd | 2014-10-24 12:37:41 -0700 | [diff] [blame] | 52 | 24 SAI |
Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 53 | |
| 54 | The third cell specifies the transfer priority as below. |
| 55 | |
| 56 | ID transfer priority |
| 57 | ------------------------- |
| 58 | 0 High |
| 59 | 1 Medium |
| 60 | 2 Low |
| 61 | |
Fabio Estevam | 3883dd7 | 2016-04-01 20:52:16 -0300 | [diff] [blame] | 62 | Optional properties: |
| 63 | |
| 64 | - gpr : The phandle to the General Purpose Register (GPR) node. |
| 65 | - fsl,sdma-event-remap : Register bits of sdma event remap, the format is |
| 66 | <reg shift val>. |
| 67 | reg is the GPR register offset. |
| 68 | shift is the bit position inside the GPR register. |
| 69 | val is the value of the bit (0 or 1). |
| 70 | |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 71 | Examples: |
| 72 | |
| 73 | sdma@83fb0000 { |
| 74 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 75 | reg = <0x83fb0000 0x4000>; |
| 76 | interrupts = <6>; |
Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 77 | #dma-cells = <3>; |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 78 | fsl,sdma-ram-script-name = "sdma-imx51.bin"; |
| 79 | }; |
Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 80 | |
| 81 | DMA clients connected to the i.MX SDMA controller must use the format |
| 82 | described in the dma.txt file. |
| 83 | |
| 84 | Examples: |
| 85 | |
| 86 | ssi2: ssi@70014000 { |
| 87 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 88 | reg = <0x70014000 0x4000>; |
| 89 | interrupts = <30>; |
| 90 | clocks = <&clks 49>; |
| 91 | dmas = <&sdma 24 1 0>, |
| 92 | <&sdma 25 1 0>; |
| 93 | dma-names = "rx", "tx"; |
| 94 | fsl,fifo-depth = <15>; |
| 95 | }; |
Fabio Estevam | 3883dd7 | 2016-04-01 20:52:16 -0300 | [diff] [blame] | 96 | |
| 97 | Using the fsl,sdma-event-remap property: |
| 98 | |
| 99 | If we want to use SDMA on the SAI1 port on a MX6SX: |
| 100 | |
| 101 | &sdma { |
| 102 | gpr = <&gpr>; |
| 103 | /* SDMA events remap for SAI1_RX and SAI1_TX */ |
| 104 | fsl,sdma-event-remap = <0 15 1>, <0 16 1>; |
| 105 | }; |
| 106 | |
| 107 | The fsl,sdma-event-remap property in this case has two values: |
| 108 | - <0 15 1> means that the offset is 0, so GPR0 is the register of the |
| 109 | SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. |
| 110 | Setting bit 15 to 1 selects SAI1_RX. |
| 111 | - <0 16 1> means that the offset is 0, so GPR0 is the register of the |
| 112 | SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. |
| 113 | Setting bit 16 to 1 selects SAI1_TX. |