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Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001* Marvell XOR engines
2
3Required properties:
Marcin Wojtasac5f0f32016-04-29 09:49:07 +02004- compatible: Should be one of the following:
5 - "marvell,orion-xor"
6 - "marvell,armada-380-xor"
7 - "marvell,armada-3700-xor".
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01008- reg: Should contain registers location and length (two sets)
9 the first set is the low registers, the second set the high
10 registers for the XOR engine.
11- clocks: pointer to the reference clock
12
13The DT node must also contains sub-nodes for each XOR channel that the
14XOR engine has. Those sub-nodes have the following required
15properties:
16- interrupts: interrupt of the XOR channel
17
Thomas Petazzoni6d8f7ab2015-07-08 16:28:16 +020018The sub-nodes used to contain one or several of the following
19properties, but they are now deprecated:
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +010020- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
21- dmacap,memset to indicate that the XOR channel is capable of memset operations
22- dmacap,xor to indicate that the XOR channel is capable of xor operations
Thomas Petazzoni6d8f7ab2015-07-08 16:28:16 +020023- dmacap,interrupt to indicate that the XOR channel is capable of
24 generating interrupts
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +010025
26Example:
27
28xor@d0060900 {
29 compatible = "marvell,orion-xor";
30 reg = <0xd0060900 0x100
31 0xd0060b00 0x100>;
32 clocks = <&coreclk 0>;
33 status = "okay";
34
35 xor00 {
36 interrupts = <51>;
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +010037 };
38 xor01 {
39 interrupts = <52>;
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +010040 };
41};