Barry Song | 2e041c9 | 2014-03-27 15:49:31 +0800 | [diff] [blame] | 1 | * CSR SiRFSoC DMA controller |
| 2 | |
| 3 | See dma.txt first |
| 4 | |
| 5 | Required properties: |
Hao Liu | 0a45dca | 2015-05-26 07:32:28 +0000 | [diff] [blame] | 6 | - compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or |
| 7 | "sirf,atlas7-dmac-v2" |
Barry Song | 2e041c9 | 2014-03-27 15:49:31 +0800 | [diff] [blame] | 8 | - reg: Should contain DMA registers location and length. |
| 9 | - interrupts: Should contain one interrupt shared by all channel |
| 10 | - #dma-cells: must be <1>. used to represent the number of integer |
| 11 | cells in the dmas property of client device. |
| 12 | - clocks: clock required |
| 13 | |
| 14 | Example: |
| 15 | |
| 16 | Controller: |
| 17 | dmac0: dma-controller@b00b0000 { |
| 18 | compatible = "sirf,prima2-dmac"; |
| 19 | reg = <0xb00b0000 0x10000>; |
| 20 | interrupts = <12>; |
| 21 | clocks = <&clks 24>; |
| 22 | #dma-cells = <1>; |
| 23 | }; |
| 24 | |
| 25 | |
| 26 | Client: |
| 27 | Fill the specific dma request line in dmas. In the below example, spi0 read |
| 28 | channel request line is 9 of the 2nd dma controller, while write channel uses |
| 29 | 4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st |
| 30 | dma controller, while write channel uses 13 of the 1st dma controller: |
| 31 | |
| 32 | spi0: spi@b00d0000 { |
| 33 | compatible = "sirf,prima2-spi"; |
| 34 | dmas = <&dmac1 9>, |
| 35 | <&dmac1 4>; |
| 36 | dma-names = "rx", "tx"; |
| 37 | }; |
| 38 | |
| 39 | spi1: spi@b0170000 { |
| 40 | compatible = "sirf,prima2-spi"; |
| 41 | dmas = <&dmac0 12>, |
| 42 | <&dmac0 13>; |
| 43 | dma-names = "rx", "tx"; |
| 44 | }; |