Sebastian Andrzej Siewior | df2634f | 2011-02-22 21:07:38 +0100 | [diff] [blame] | 1 | Interrupt chips |
| 2 | --------------- |
| 3 | |
| 4 | * Intel I/O Advanced Programmable Interrupt Controller (IO APIC) |
| 5 | |
| 6 | Required properties: |
| 7 | -------------------- |
| 8 | compatible = "intel,ce4100-ioapic"; |
| 9 | #interrupt-cells = <2>; |
| 10 | |
| 11 | Device's interrupt property: |
| 12 | |
| 13 | interrupts = <P S>; |
| 14 | |
| 15 | The first number (P) represents the interrupt pin which is wired to the |
| 16 | IO APIC. The second number (S) represents the sense of interrupt which |
| 17 | should be configured and can be one of: |
| 18 | 0 - Edge Rising |
| 19 | 1 - Level Low |
| 20 | 2 - Level High |
| 21 | 3 - Edge Falling |
| 22 | |
| 23 | * Local APIC |
| 24 | Required property: |
| 25 | |
| 26 | compatible = "intel,ce4100-lapic"; |