Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 1 | Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) |
| 2 | |
| 3 | Samsung's Exynos architecture contains System MMUs that enables scattered |
| 4 | physical memory chunks visible as a contiguous region to DMA-capable peripheral |
| 5 | devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. |
| 6 | |
| 7 | System MMU is an IOMMU and supports identical translation table format to |
| 8 | ARMv7 translation tables with minimum set of page properties including access |
| 9 | permissions, shareability and security protection. In addition, System MMU has |
| 10 | another capabilities like L2 TLB or block-fetch buffers to minimize translation |
| 11 | latency. |
| 12 | |
| 13 | System MMUs are in many to one relation with peripheral devices, i.e. single |
| 14 | peripheral device might have multiple System MMUs (usually one for each bus |
| 15 | master), but one System MMU can handle transactions from only one peripheral |
| 16 | device. The relation between a System MMU and the peripheral device needs to be |
| 17 | defined in device node of the peripheral device. |
| 18 | |
| 19 | MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System |
| 20 | MMUs. |
| 21 | * MFC has one System MMU on its left and right bus. |
| 22 | * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU |
| 23 | for window 1, 2 and 3. |
| 24 | * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and |
| 25 | the other System MMU on the write channel. |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 26 | |
Marek Szyprowski | e680270 | 2016-02-18 15:12:57 +0100 | [diff] [blame] | 27 | For information on assigning System MMU controller to its peripheral devices, |
| 28 | see generic IOMMU bindings. |
Shaik Ameer Basha | df15e1d | 2014-05-14 11:23:33 +0530 | [diff] [blame] | 29 | |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 30 | Required properties: |
| 31 | - compatible: Should be "samsung,exynos-sysmmu" |
| 32 | - reg: A tuple of base address and size of System MMU registers. |
Marek Szyprowski | e680270 | 2016-02-18 15:12:57 +0100 | [diff] [blame] | 33 | - #iommu-cells: Should be <0>. |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 34 | - interrupt-parent: The phandle of the interrupt controller of System MMU |
| 35 | - interrupts: An interrupt specifier for interrupt signal of System MMU, |
| 36 | according to the format defined by a particular interrupt |
| 37 | controller. |
Marek Szyprowski | 740a01e | 2016-02-18 15:12:58 +0100 | [diff] [blame] | 38 | - clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate |
| 39 | SYSMMU core clocks. |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 40 | Optional "master" if the clock to the System MMU is gated by |
Marek Szyprowski | 740a01e | 2016-02-18 15:12:58 +0100 | [diff] [blame] | 41 | another gate clock other core (usually main gate clock |
Marek Szyprowski | e680270 | 2016-02-18 15:12:57 +0100 | [diff] [blame] | 42 | of peripheral device this SYSMMU belongs to). |
| 43 | - clocks: Phandles for respective clocks described by clock-names. |
Marek Szyprowski | 0da6587 | 2015-01-24 13:16:15 +0900 | [diff] [blame] | 44 | - power-domains: Required if the System MMU is needed to gate its power. |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 45 | Please refer to the following document: |
Krzysztof Kozlowski | 068812e | 2015-10-24 05:07:02 +0900 | [diff] [blame] | 46 | Documentation/devicetree/bindings/power/pd-samsung.txt |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 47 | |
| 48 | Examples: |
| 49 | gsc_0: gsc@13e00000 { |
| 50 | compatible = "samsung,exynos5-gsc"; |
| 51 | reg = <0x13e00000 0x1000>; |
| 52 | interrupts = <0 85 0>; |
Marek Szyprowski | 0da6587 | 2015-01-24 13:16:15 +0900 | [diff] [blame] | 53 | power-domains = <&pd_gsc>; |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 54 | clocks = <&clock CLK_GSCL0>; |
| 55 | clock-names = "gscl"; |
Marek Szyprowski | e680270 | 2016-02-18 15:12:57 +0100 | [diff] [blame] | 56 | iommus = <&sysmmu_gsc0>; |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | sysmmu_gsc0: sysmmu@13E80000 { |
| 60 | compatible = "samsung,exynos-sysmmu"; |
| 61 | reg = <0x13E80000 0x1000>; |
| 62 | interrupt-parent = <&combiner>; |
| 63 | interrupts = <2 0>; |
| 64 | clock-names = "sysmmu", "master"; |
| 65 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; |
Marek Szyprowski | 0da6587 | 2015-01-24 13:16:15 +0900 | [diff] [blame] | 66 | power-domains = <&pd_gsc>; |
Marek Szyprowski | e680270 | 2016-02-18 15:12:57 +0100 | [diff] [blame] | 67 | #iommu-cells = <0>; |
Cho KyongHo | 93e268d | 2014-05-12 11:45:01 +0530 | [diff] [blame] | 68 | }; |