| Mugunthan V N | 5892cd1 | 2013-09-21 00:50:39 +0530 | [diff] [blame] | 1 | TI CPSW Phy mode Selection Device Tree Bindings |
| 2 | ----------------------------------------------- |
| 3 | |
| 4 | Required properties: |
| Mugunthan V N | d415fa1 | 2014-05-09 19:07:34 +0530 | [diff] [blame] | 5 | - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and |
| 6 | "ti,dra7xx-cpsw-phy-sel" for dra7xx platform |
| Mugunthan V N | b80b930 | 2014-05-09 19:07:35 +0530 | [diff] [blame] | 7 | "ti,am43xx-cpsw-phy-sel" for am43xx platform |
| Mugunthan V N | 5892cd1 | 2013-09-21 00:50:39 +0530 | [diff] [blame] | 8 | - reg : physical base address and size of the cpsw |
| 9 | registers map |
| 10 | - reg-names : names of the register map given in "reg" node |
| 11 | |
| 12 | Optional properties: |
| 13 | -rmii-clock-ext : If present, the driver will configure the RMII |
| 14 | interface to external clock usage |
| 15 | |
| 16 | Examples: |
| 17 | |
| 18 | phy_sel: cpsw-phy-sel@44e10650 { |
| 19 | compatible = "ti,am3352-cpsw-phy-sel"; |
| 20 | reg= <0x44e10650 0x4>; |
| 21 | reg-names = "gmii-sel"; |
| 22 | }; |
| 23 | |
| 24 | (or) |
| 25 | phy_sel: cpsw-phy-sel@44e10650 { |
| 26 | compatible = "ti,am3352-cpsw-phy-sel"; |
| 27 | reg= <0x44e10650 0x4>; |
| 28 | reg-names = "gmii-sel"; |
| 29 | rmii-clock-ext; |
| 30 | }; |