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Kumar Galad0fc2ea2008-07-07 11:28:33 -05001* MDIO IO device
2
3The MDIO is a bus to which the PHY devices are connected. For each
4device that exists on this bus, a child node should be created. See
Andy Flemingb31a1d82008-12-16 15:29:15 -08005the definition of the PHY node in booting-without-of.txt for an example
6of how to define a PHY.
Kumar Galad0fc2ea2008-07-07 11:28:33 -05007
8Required properties:
9 - reg : Offset and length of the register set for the device
10 - compatible : Should define the compatible device type for the
Shruti Kanetkar132d7bc2015-02-01 15:58:31 -060011 mdio. Currently supported strings/devices are:
12 - "fsl,gianfar-tbi"
13 - "fsl,gianfar-mdio"
14 - "fsl,etsec2-tbi"
15 - "fsl,etsec2-mdio"
16 - "fsl,ucc-mdio"
17 - "fsl,fman-mdio"
18 When device_type is "mdio", the following strings are also considered:
19 - "gianfar"
20 - "ucc_geth_phy"
Kumar Galad0fc2ea2008-07-07 11:28:33 -050021
22Example:
23
24 mdio@24520 {
25 reg = <24520 20>;
26 compatible = "fsl,gianfar-mdio";
27
28 ethernet-phy@0 {
29 ......
30 };
31 };
32
Andy Flemingb31a1d82008-12-16 15:29:15 -080033* TBI Internal MDIO bus
34
35As of this writing, every tsec is associated with an internal TBI PHY.
36This PHY is accessed through the local MDIO bus. These buses are defined
37similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
38The TBI PHYs underneath them are similar to normal PHYs, but the reg property
39is considered instructive, rather than descriptive. The reg property should
40be chosen so it doesn't interfere with other PHYs on the bus.
Kumar Galad0fc2ea2008-07-07 11:28:33 -050041
42* Gianfar-compatible ethernet nodes
43
Scott Wood00262982008-07-11 18:04:43 -050044Properties:
Kumar Galad0fc2ea2008-07-07 11:28:33 -050045
46 - device_type : Should be "network"
47 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
48 - compatible : Should be "gianfar"
49 - reg : Offset and length of the register set for the device
Scott Wood00262982008-07-11 18:04:43 -050050 - interrupts : For FEC devices, the first interrupt is the device's
51 interrupt. For TSEC and eTSEC devices, the first interrupt is
52 transmit, the second is receive, and the third is error.
Sergei Shtylyove8f08ee2014-02-18 02:41:59 +030053 - phy-handle : See ethernet.txt file in the same directory.
Florian Fainelliae218882014-05-22 09:47:44 -070054 - fixed-link : See fixed-link.txt in the same directory.
Sergei Shtylyove8f08ee2014-02-18 02:41:59 +030055 - phy-connection-type : See ethernet.txt file in the same directory.
56 This property is only really needed if the connection is of type
57 "rgmii-id", as all other connection types are detected by hardware.
Scott Wood00262982008-07-11 18:04:43 -050058 - fsl,magic-packet : If present, indicates that the hardware supports
59 waking up via magic packet.
Claudiu Manoil66cebb82015-10-05 17:19:57 +030060 - fsl,wake-on-filer : If present, indicates that the hardware supports
61 waking up by Filer General Purpose Interrupt (FGPI) asserted on the
62 Rx int line. This is an advanced power management capability allowing
63 certain packet types (user) defined by filer rules to wake up the system.
Andy Fleming4d7902f2009-02-04 16:43:44 -080064 - bd-stash : If present, indicates that the hardware supports stashing
65 buffer descriptors in the L2.
66 - rx-stash-len : Denotes the number of bytes of a received buffer to stash
67 in the L2.
68 - rx-stash-idx : Denotes the index of the first byte from the received
69 buffer to stash in the L2.
Kumar Galad0fc2ea2008-07-07 11:28:33 -050070
71Example:
72 ethernet@24000 {
Kumar Galad0fc2ea2008-07-07 11:28:33 -050073 device_type = "network";
74 model = "TSEC";
75 compatible = "gianfar";
Scott Wood00262982008-07-11 18:04:43 -050076 reg = <0x24000 0x1000>;
77 local-mac-address = [ 00 E0 0C 00 73 00 ];
78 interrupts = <29 2 30 2 34 2>;
79 interrupt-parent = <&mpic>;
80 phy-handle = <&phy0>
Kumar Galad0fc2ea2008-07-07 11:28:33 -050081 };
Richard Cochranc78275f2011-04-22 12:03:54 +020082
83* Gianfar PTP clock nodes
84
85General Properties:
86
87 - compatible Should be "fsl,etsec-ptp"
88 - reg Offset and length of the register set for the device
89 - interrupts There should be at least two interrupts. Some devices
90 have as many as four PTP related interrupts.
91
92Clock Properties:
93
Aida Mynzhasovae58f6f42013-09-27 17:40:27 +040094 - fsl,cksel Timer reference clock source.
Richard Cochranc78275f2011-04-22 12:03:54 +020095 - fsl,tclk-period Timer reference clock period in nanoseconds.
96 - fsl,tmr-prsc Prescaler, divides the output clock.
97 - fsl,tmr-add Frequency compensation value.
98 - fsl,tmr-fiper1 Fixed interval period pulse generator.
99 - fsl,tmr-fiper2 Fixed interval period pulse generator.
100 - fsl,max-adj Maximum frequency adjustment in parts per billion.
101
102 These properties set the operational parameters for the PTP
103 clock. You must choose these carefully for the clock to work right.
104 Here is how to figure good values:
105
Aida Mynzhasovae58f6f42013-09-27 17:40:27 +0400106 TimerOsc = selected reference clock MHz
Richard Cochranc78275f2011-04-22 12:03:54 +0200107 tclk_period = desired clock period nanoseconds
108 NominalFreq = 1000 / tclk_period MHz
109 FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
110 tmr_add = ceil(2^32 / FreqDivRatio)
111 OutputClock = NominalFreq / tmr_prsc MHz
112 PulseWidth = 1 / OutputClock microseconds
113 FiperFreq1 = desired frequency in Hz
114 FiperDiv1 = 1000000 * OutputClock / FiperFreq1
115 tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
116 max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
117
118 The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
119 driver expects that tmr_fiper1 will be correctly set to produce a 1
120 Pulse Per Second (PPS) signal, since this will be offered to the PPS
121 subsystem to synchronize the Linux clock.
122
Aida Mynzhasovae58f6f42013-09-27 17:40:27 +0400123 Reference clock source is determined by the value, which is holded
124 in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
125 value, which will be directly written in those bits, that is why,
126 according to reference manual, the next clock sources can be used:
127
128 <0> - external high precision timer reference clock (TSEC_TMR_CLK
129 input is used for this purpose);
130 <1> - eTSEC system clock;
131 <2> - eTSEC1 transmit clock;
132 <3> - RTC clock input.
133
134 When this attribute is not used, eTSEC system clock will serve as
135 IEEE 1588 timer reference clock.
136
Richard Cochranc78275f2011-04-22 12:03:54 +0200137Example:
138
139 ptp_clock@24E00 {
140 compatible = "fsl,etsec-ptp";
141 reg = <0x24E00 0xB0>;
142 interrupts = <12 0x8 13 0x8>;
143 interrupt-parent = < &ipic >;
Aida Mynzhasovae58f6f42013-09-27 17:40:27 +0400144 fsl,cksel = <1>;
Richard Cochranc78275f2011-04-22 12:03:54 +0200145 fsl,tclk-period = <10>;
146 fsl,tmr-prsc = <100>;
147 fsl,tmr-add = <0x999999A4>;
148 fsl,tmr-fiper1 = <0x3B9AC9F6>;
149 fsl,tmr-fiper2 = <0x00018696>;
150 fsl,max-adj = <659999998>;
151 };