Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 1 | * Marvell MDIO Ethernet Controller interface |
| 2 | |
| 3 | The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x, |
| 4 | MV78xx0, Armada 370 and Armada XP have an identical unit that provides |
| 5 | an interface with the MDIO bus. This driver handles this MDIO |
| 6 | interface. |
| 7 | |
| 8 | Required properties: |
| 9 | - compatible: "marvell,orion-mdio" |
| 10 | - reg: address and length of the SMI register |
| 11 | |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 12 | Optional properties: |
| 13 | - interrupts: interrupt line number for the SMI error/done interrupt |
Sebastian Hesselbarth | b8075da | 2013-04-10 23:24:48 +0000 | [diff] [blame] | 14 | - clocks: Phandle to the clock control device and gate bit |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 15 | |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 16 | The child nodes of the MDIO driver are the individual PHY devices |
| 17 | connected to this MDIO bus. They must have a "reg" property given the |
| 18 | PHY address on the MDIO bus. |
| 19 | |
| 20 | Example at the SoC level: |
| 21 | |
| 22 | mdio { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | compatible = "marvell,orion-mdio"; |
| 26 | reg = <0xd0072004 0x4>; |
| 27 | }; |
| 28 | |
| 29 | And at the board level: |
| 30 | |
| 31 | mdio { |
| 32 | phy0: ethernet-phy@0 { |
| 33 | reg = <0>; |
| 34 | }; |
| 35 | |
| 36 | phy1: ethernet-phy@1 { |
| 37 | reg = <1>; |
| 38 | }; |
| 39 | } |