| Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 1 | Tegra SoC PWFM controller |
| 2 | |
| 3 | Required properties: |
| Laxman Dewangan | 57dfd17 | 2016-06-22 17:17:22 +0530 | [diff] [blame] | 4 | - compatible: Must be: |
| 5 | - "nvidia,tegra20-pwm": for Tegra20 |
| 6 | - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30 |
| 7 | - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114 |
| 8 | - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124 |
| 9 | - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 |
| 10 | - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 |
| 11 | - "nvidia,tegra186-pwm": for Tegra186 |
| Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 12 | - reg: physical base address and length of the controller's registers |
| Laurent Pinchart | ebeec0a | 2013-07-18 00:54:23 +0200 | [diff] [blame] | 13 | - #pwm-cells: should be 2. See pwm.txt in this directory for a description of |
| 14 | the cells format. |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 15 | - clocks: Must contain one entry, for the module clock. |
| 16 | See ../clocks/clock-bindings.txt for details. |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame] | 17 | - resets: Must contain an entry for each entry in reset-names. |
| 18 | See ../reset/reset.txt for details. |
| 19 | - reset-names: Must include the following entries: |
| 20 | - pwm |
| Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 21 | |
| 22 | Example: |
| 23 | |
| 24 | pwm: pwm@7000a000 { |
| 25 | compatible = "nvidia,tegra20-pwm"; |
| 26 | reg = <0x7000a000 0x100>; |
| 27 | #pwm-cells = <2>; |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 28 | clocks = <&tegra_car 17>; |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame] | 29 | resets = <&tegra_car 17>; |
| 30 | reset-names = "pwm"; |
| Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 31 | }; |