| Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 1 | NVIDIA Tegra20 real-time clock |
| 2 | |
| 3 | The Tegra RTC maintains seconds and milliseconds counters, and five alarm |
| 4 | registers. The alarms and other interrupts may wake the system from low-power |
| 5 | state. |
| 6 | |
| 7 | Required properties: |
| 8 | |
| Paul Walmsley | 193c9d2 | 2015-01-30 15:11:04 -0700 | [diff] [blame] | 9 | - compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, |
| 10 | must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip> |
| 11 | can be tegra30, tegra114, tegra124, or tegra132. |
| Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 12 | - reg : Specifies base physical address and size of the registers. |
| 13 | - interrupts : A single interrupt specifier. |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 14 | - clocks : Must contain one entry, for the module clock. |
| 15 | See ../clocks/clock-bindings.txt for details. |
| Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 16 | |
| 17 | Example: |
| 18 | |
| 19 | timer { |
| 20 | compatible = "nvidia,tegra20-rtc"; |
| 21 | reg = <0x7000e000 0x100>; |
| 22 | interrupts = <0 2 0x04>; |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 23 | clocks = <&tegra_car 4>; |
| Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 24 | }; |