Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/pm.c |
| 2 | * |
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * EXYNOS4210 - Power Management support |
| 7 | * |
| 8 | * Based on arch/arm/mach-s3c2410/pm.c |
| 9 | * Copyright (c) 2006 Simtec Electronics |
| 10 | * Ben Dooks <ben@simtec.co.uk> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/suspend.h> |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 19 | #include <linux/syscore_ops.h> |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 20 | #include <linux/io.h> |
| 21 | |
| 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/hardware/cache-l2x0.h> |
| 24 | |
| 25 | #include <plat/cpu.h> |
| 26 | #include <plat/pm.h> |
| 27 | |
| 28 | #include <mach/regs-irq.h> |
| 29 | #include <mach/regs-gpio.h> |
| 30 | #include <mach/regs-clock.h> |
| 31 | #include <mach/regs-pmu.h> |
| 32 | #include <mach/pm-core.h> |
Jaecheol Lee | e4cf2d1 | 2011-07-18 19:21:27 +0900 | [diff] [blame] | 33 | #include <mach/pmu.h> |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 34 | |
| 35 | static struct sleep_save exynos4_set_clksrc[] = { |
| 36 | { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, |
| 37 | { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, |
| 38 | { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, |
| 39 | { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, |
| 40 | { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, |
| 41 | { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, |
| 42 | { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, |
| 43 | { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, |
| 44 | { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, |
| 45 | { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, |
| 46 | }; |
| 47 | |
| 48 | static struct sleep_save exynos4_core_save[] = { |
| 49 | /* CMU side */ |
| 50 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), |
| 51 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), |
| 52 | SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), |
| 53 | SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), |
| 54 | SAVE_ITEM(S5P_EPLL_CON0), |
| 55 | SAVE_ITEM(S5P_EPLL_CON1), |
| 56 | SAVE_ITEM(S5P_VPLL_CON0), |
| 57 | SAVE_ITEM(S5P_VPLL_CON1), |
| 58 | SAVE_ITEM(S5P_CLKSRC_TOP0), |
| 59 | SAVE_ITEM(S5P_CLKSRC_TOP1), |
| 60 | SAVE_ITEM(S5P_CLKSRC_CAM), |
| 61 | SAVE_ITEM(S5P_CLKSRC_MFC), |
| 62 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
| 63 | SAVE_ITEM(S5P_CLKSRC_LCD0), |
| 64 | SAVE_ITEM(S5P_CLKSRC_LCD1), |
| 65 | SAVE_ITEM(S5P_CLKSRC_MAUDIO), |
| 66 | SAVE_ITEM(S5P_CLKSRC_FSYS), |
| 67 | SAVE_ITEM(S5P_CLKSRC_PERIL0), |
| 68 | SAVE_ITEM(S5P_CLKSRC_PERIL1), |
| 69 | SAVE_ITEM(S5P_CLKDIV_CAM), |
| 70 | SAVE_ITEM(S5P_CLKDIV_TV), |
| 71 | SAVE_ITEM(S5P_CLKDIV_MFC), |
| 72 | SAVE_ITEM(S5P_CLKDIV_G3D), |
| 73 | SAVE_ITEM(S5P_CLKDIV_IMAGE), |
| 74 | SAVE_ITEM(S5P_CLKDIV_LCD0), |
| 75 | SAVE_ITEM(S5P_CLKDIV_LCD1), |
| 76 | SAVE_ITEM(S5P_CLKDIV_MAUDIO), |
| 77 | SAVE_ITEM(S5P_CLKDIV_FSYS0), |
| 78 | SAVE_ITEM(S5P_CLKDIV_FSYS1), |
| 79 | SAVE_ITEM(S5P_CLKDIV_FSYS2), |
| 80 | SAVE_ITEM(S5P_CLKDIV_FSYS3), |
| 81 | SAVE_ITEM(S5P_CLKDIV_PERIL0), |
| 82 | SAVE_ITEM(S5P_CLKDIV_PERIL1), |
| 83 | SAVE_ITEM(S5P_CLKDIV_PERIL2), |
| 84 | SAVE_ITEM(S5P_CLKDIV_PERIL3), |
| 85 | SAVE_ITEM(S5P_CLKDIV_PERIL4), |
| 86 | SAVE_ITEM(S5P_CLKDIV_PERIL5), |
| 87 | SAVE_ITEM(S5P_CLKDIV_TOP), |
| 88 | SAVE_ITEM(S5P_CLKSRC_MASK_CAM), |
| 89 | SAVE_ITEM(S5P_CLKSRC_MASK_TV), |
| 90 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), |
| 91 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), |
| 92 | SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), |
| 93 | SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), |
| 94 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), |
| 95 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), |
| 96 | SAVE_ITEM(S5P_CLKGATE_SCLKCAM), |
| 97 | SAVE_ITEM(S5P_CLKGATE_IP_CAM), |
| 98 | SAVE_ITEM(S5P_CLKGATE_IP_TV), |
| 99 | SAVE_ITEM(S5P_CLKGATE_IP_MFC), |
| 100 | SAVE_ITEM(S5P_CLKGATE_IP_G3D), |
| 101 | SAVE_ITEM(S5P_CLKGATE_IP_IMAGE), |
| 102 | SAVE_ITEM(S5P_CLKGATE_IP_LCD0), |
| 103 | SAVE_ITEM(S5P_CLKGATE_IP_LCD1), |
| 104 | SAVE_ITEM(S5P_CLKGATE_IP_FSYS), |
| 105 | SAVE_ITEM(S5P_CLKGATE_IP_GPS), |
| 106 | SAVE_ITEM(S5P_CLKGATE_IP_PERIL), |
| 107 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR), |
| 108 | SAVE_ITEM(S5P_CLKGATE_BLOCK), |
| 109 | SAVE_ITEM(S5P_CLKSRC_MASK_DMC), |
| 110 | SAVE_ITEM(S5P_CLKSRC_DMC), |
| 111 | SAVE_ITEM(S5P_CLKDIV_DMC0), |
| 112 | SAVE_ITEM(S5P_CLKDIV_DMC1), |
| 113 | SAVE_ITEM(S5P_CLKGATE_IP_DMC), |
| 114 | SAVE_ITEM(S5P_CLKSRC_CPU), |
| 115 | SAVE_ITEM(S5P_CLKDIV_CPU), |
| 116 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), |
| 117 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), |
| 118 | /* GIC side */ |
| 119 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), |
| 120 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), |
| 121 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x008), |
| 122 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C), |
| 123 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x014), |
| 124 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x018), |
| 125 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x000), |
| 126 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x004), |
| 127 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x100), |
| 128 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x104), |
| 129 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x108), |
| 130 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x300), |
| 131 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x304), |
| 132 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x308), |
| 133 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x400), |
| 134 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x404), |
| 135 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x408), |
| 136 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C), |
| 137 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x410), |
| 138 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x414), |
| 139 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x418), |
| 140 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C), |
| 141 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x420), |
| 142 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x424), |
| 143 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x428), |
| 144 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C), |
| 145 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x430), |
| 146 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x434), |
| 147 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x438), |
| 148 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C), |
| 149 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x440), |
| 150 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x444), |
| 151 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x448), |
| 152 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C), |
| 153 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x450), |
| 154 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x454), |
| 155 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x458), |
| 156 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C), |
| 157 | |
| 158 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x800), |
| 159 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x804), |
| 160 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x808), |
| 161 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C), |
| 162 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x810), |
| 163 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x814), |
| 164 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x818), |
| 165 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C), |
| 166 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x820), |
| 167 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x824), |
| 168 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x828), |
| 169 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C), |
| 170 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x830), |
| 171 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x834), |
| 172 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x838), |
| 173 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C), |
| 174 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x840), |
| 175 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x844), |
| 176 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x848), |
| 177 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C), |
| 178 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x850), |
| 179 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x854), |
| 180 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x858), |
| 181 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C), |
| 182 | |
| 183 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00), |
| 184 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04), |
| 185 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08), |
| 186 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C), |
| 187 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10), |
| 188 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14), |
| 189 | |
| 190 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), |
| 191 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), |
| 192 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), |
| 193 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), |
| 194 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), |
| 195 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), |
| 196 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), |
| 197 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), |
| 198 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), |
| 199 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), |
| 200 | }; |
| 201 | |
| 202 | static struct sleep_save exynos4_l2cc_save[] = { |
| 203 | SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), |
| 204 | SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), |
| 205 | SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), |
| 206 | SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), |
| 207 | SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), |
| 208 | }; |
| 209 | |
Jaecheol Lee | f4ba4b0 | 2011-07-18 19:25:03 +0900 | [diff] [blame^] | 210 | /* For Cortex-A9 Diagnostic and Power control register */ |
| 211 | static unsigned int save_arm_register[2]; |
| 212 | |
| 213 | void exynos4_cpu_suspend(unsigned long arg) |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 214 | { |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 215 | outer_flush_all(); |
| 216 | |
| 217 | /* issue the standby signal into the pm unit. */ |
| 218 | cpu_do_idle(); |
| 219 | |
| 220 | /* we should never get past here */ |
| 221 | panic("sleep resumed to originator?"); |
| 222 | } |
| 223 | |
| 224 | static void exynos4_pm_prepare(void) |
| 225 | { |
| 226 | u32 tmp; |
| 227 | |
| 228 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); |
| 229 | s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); |
| 230 | |
| 231 | tmp = __raw_readl(S5P_INFORM1); |
| 232 | |
| 233 | /* Set value of power down register for sleep mode */ |
| 234 | |
Jaecheol Lee | e4cf2d1 | 2011-07-18 19:21:27 +0900 | [diff] [blame] | 235 | exynos4_sys_powerdown_conf(SYS_SLEEP); |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 236 | __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); |
| 237 | |
| 238 | /* ensure at least INFORM0 has the resume address */ |
| 239 | |
| 240 | __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); |
| 241 | |
| 242 | /* Before enter central sequence mode, clock src register have to set */ |
| 243 | |
| 244 | s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); |
| 245 | |
| 246 | } |
| 247 | |
| 248 | static int exynos4_pm_add(struct sys_device *sysdev) |
| 249 | { |
| 250 | pm_cpu_prep = exynos4_pm_prepare; |
| 251 | pm_cpu_sleep = exynos4_cpu_suspend; |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | /* This function copy from linux/arch/arm/kernel/smp_scu.c */ |
| 257 | |
| 258 | void exynos4_scu_enable(void __iomem *scu_base) |
| 259 | { |
| 260 | u32 scu_ctrl; |
| 261 | |
| 262 | scu_ctrl = __raw_readl(scu_base); |
| 263 | /* already enabled? */ |
| 264 | if (scu_ctrl & 1) |
| 265 | return; |
| 266 | |
| 267 | scu_ctrl |= 1; |
| 268 | __raw_writel(scu_ctrl, scu_base); |
| 269 | |
| 270 | /* |
| 271 | * Ensure that the data accessed by CPU0 before the SCU was |
| 272 | * initialised is visible to the other CPUs. |
| 273 | */ |
| 274 | flush_cache_all(); |
| 275 | } |
| 276 | |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 277 | static struct sysdev_driver exynos4_pm_driver = { |
| 278 | .add = exynos4_pm_add, |
| 279 | }; |
| 280 | |
| 281 | static __init int exynos4_pm_drvinit(void) |
| 282 | { |
| 283 | unsigned int tmp; |
| 284 | |
| 285 | s3c_pm_init(); |
| 286 | |
| 287 | /* All wakeup disable */ |
| 288 | |
| 289 | tmp = __raw_readl(S5P_WAKEUP_MASK); |
| 290 | tmp |= ((0xFF << 8) | (0x1F << 1)); |
| 291 | __raw_writel(tmp, S5P_WAKEUP_MASK); |
| 292 | |
| 293 | return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); |
| 294 | } |
| 295 | arch_initcall(exynos4_pm_drvinit); |
| 296 | |
Jaecheol Lee | 12974e9 | 2011-07-18 19:21:41 +0900 | [diff] [blame] | 297 | static int exynos4_pm_suspend(void) |
| 298 | { |
| 299 | unsigned long tmp; |
| 300 | |
| 301 | /* Setting Central Sequence Register for power down mode */ |
| 302 | |
| 303 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); |
| 304 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; |
| 305 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); |
| 306 | |
Jaecheol Lee | f4ba4b0 | 2011-07-18 19:25:03 +0900 | [diff] [blame^] | 307 | /* Save Power control register */ |
| 308 | asm ("mrc p15, 0, %0, c15, c0, 0" |
| 309 | : "=r" (tmp) : : "cc"); |
| 310 | save_arm_register[0] = tmp; |
| 311 | |
| 312 | /* Save Diagnostic register */ |
| 313 | asm ("mrc p15, 0, %0, c15, c0, 1" |
| 314 | : "=r" (tmp) : : "cc"); |
| 315 | save_arm_register[1] = tmp; |
| 316 | |
Jaecheol Lee | 12974e9 | 2011-07-18 19:21:41 +0900 | [diff] [blame] | 317 | return 0; |
| 318 | } |
| 319 | |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 320 | static void exynos4_pm_resume(void) |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 321 | { |
Jaecheol Lee | e240ab1 | 2011-07-18 19:21:34 +0900 | [diff] [blame] | 322 | unsigned long tmp; |
| 323 | |
| 324 | /* |
| 325 | * If PMU failed while entering sleep mode, WFI will be |
| 326 | * ignored by PMU and then exiting cpu_do_idle(). |
| 327 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically |
| 328 | * in this situation. |
| 329 | */ |
| 330 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); |
| 331 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { |
| 332 | tmp |= S5P_CENTRAL_LOWPWR_CFG; |
| 333 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); |
| 334 | /* No need to perform below restore code */ |
| 335 | goto early_wakeup; |
| 336 | } |
Jaecheol Lee | f4ba4b0 | 2011-07-18 19:25:03 +0900 | [diff] [blame^] | 337 | /* Restore Power control register */ |
| 338 | tmp = save_arm_register[0]; |
| 339 | asm volatile ("mcr p15, 0, %0, c15, c0, 0" |
| 340 | : : "r" (tmp) |
| 341 | : "cc"); |
| 342 | |
| 343 | /* Restore Diagnostic register */ |
| 344 | tmp = save_arm_register[1]; |
| 345 | asm volatile ("mcr p15, 0, %0, c15, c0, 1" |
| 346 | : : "r" (tmp) |
| 347 | : "cc"); |
Jaecheol Lee | e240ab1 | 2011-07-18 19:21:34 +0900 | [diff] [blame] | 348 | |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 349 | /* For release retention */ |
| 350 | |
| 351 | __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); |
| 352 | __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); |
| 353 | __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); |
| 354 | __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); |
| 355 | __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); |
| 356 | __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); |
| 357 | __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); |
| 358 | |
| 359 | s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); |
| 360 | |
| 361 | exynos4_scu_enable(S5P_VA_SCU); |
| 362 | |
| 363 | #ifdef CONFIG_CACHE_L2X0 |
| 364 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); |
| 365 | outer_inv_all(); |
| 366 | /* enable L2X0*/ |
| 367 | writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); |
| 368 | #endif |
Jaecheol Lee | e240ab1 | 2011-07-18 19:21:34 +0900 | [diff] [blame] | 369 | |
| 370 | early_wakeup: |
| 371 | return; |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 372 | } |
| 373 | |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 374 | static struct syscore_ops exynos4_pm_syscore_ops = { |
Jaecheol Lee | 12974e9 | 2011-07-18 19:21:41 +0900 | [diff] [blame] | 375 | .suspend = exynos4_pm_suspend, |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 376 | .resume = exynos4_pm_resume, |
| 377 | }; |
| 378 | |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 379 | static __init int exynos4_pm_syscore_init(void) |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 380 | { |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 381 | register_syscore_ops(&exynos4_pm_syscore_ops); |
| 382 | return 0; |
Jaecheol Lee | 1663895 | 2011-03-10 13:33:59 +0900 | [diff] [blame] | 383 | } |
Rafael J. Wysocki | bb072c3 | 2011-04-22 22:03:21 +0200 | [diff] [blame] | 384 | arch_initcall(exynos4_pm_syscore_init); |