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Rafał Miłecki1d738e62011-07-07 15:25:27 +02001/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n LCN-PHY support
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include <linux/slab.h>
24
25#include "b43.h"
26#include "phy_lcn.h"
27#include "tables_phy_lcn.h"
28#include "main.h"
29
30/**************************************************
Rafał Miłeckidc713fb2011-08-15 18:50:56 +020031 * Radio 2064.
32 **************************************************/
33
34static void b43_radio_2064_init(struct b43_wldev *dev)
35{
36 b43_radio_write(dev, 0x09c, 0x0020);
37 b43_radio_write(dev, 0x105, 0x0008);
38 b43_radio_write(dev, 0x032, 0x0062);
39 b43_radio_write(dev, 0x033, 0x0019);
40 b43_radio_write(dev, 0x090, 0x0010);
41 b43_radio_write(dev, 0x010, 0x0000);
42 b43_radio_write(dev, 0x060, 0x007f);
43 b43_radio_write(dev, 0x061, 0x0072);
44 b43_radio_write(dev, 0x062, 0x007f);
45 b43_radio_write(dev, 0x01d, 0x0002);
46 b43_radio_write(dev, 0x01e, 0x0006);
47
48 b43_phy_write(dev, 0x4ea, 0x4688);
49 b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
50 b43_phy_mask(dev, 0x4eb, ~0x01c0);
51 b43_phy_maskset(dev, 0x4eb, 0xff00, 0x19);
52
53 b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
54
55 b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
56 b43_radio_set(dev, 0x004, 0x40);
57 b43_radio_set(dev, 0x120, 0x10);
58 b43_radio_set(dev, 0x078, 0x80);
59 b43_radio_set(dev, 0x129, 0x2);
60 b43_radio_set(dev, 0x057, 0x1);
61 b43_radio_set(dev, 0x05b, 0x2);
62
63 /* TODO: wait for some bit to be set */
64 b43_radio_read(dev, 0x05c);
65
66 b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
67 b43_radio_mask(dev, 0x057, (u16) ~0xff01);
68
69 b43_phy_write(dev, 0x933, 0x2d6b);
70 b43_phy_write(dev, 0x934, 0x2d6b);
71 b43_phy_write(dev, 0x935, 0x2d6b);
72 b43_phy_write(dev, 0x936, 0x2d6b);
73 b43_phy_write(dev, 0x937, 0x016b);
74
75 b43_radio_mask(dev, 0x057, (u16) ~0xff02);
76 b43_radio_write(dev, 0x0c2, 0x006f);
77}
78
79/**************************************************
Rafał Miłecki78bc2462011-08-15 18:50:55 +020080 * Various PHY ops
81 **************************************************/
82
83static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
84{
85 u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
86 u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
87
88 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
89 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);
90
91 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
92 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
93
94 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
95 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
96}
97
98static void b43_phy_lcn_clean_0x18_table(struct b43_wldev *dev)
99{
100 u8 i;
101
102 for (i = 0; i < 0x80; i++)
103 b43_lcntab_write(dev, B43_LCNTAB32(0x18, i), 0x80000);
104}
105
106static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev)
107{
108 u8 i;
109
110 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
111 for (i = 0; i < 30; i++) {
112 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
113 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
114 }
115
116 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
117 for (i = 0; i < 64; i++) {
118 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
119 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
120 }
121}
122
123/**************************************************
Rafał Miłeckif9286682011-08-14 23:27:28 +0200124 * Basic PHY ops.
125 **************************************************/
126
127static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
128{
129 struct b43_phy_lcn *phy_lcn;
130
131 phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
132 if (!phy_lcn)
133 return -ENOMEM;
134 dev->phy.lcn = phy_lcn;
135
136 return 0;
137}
138
139static void b43_phy_lcn_op_free(struct b43_wldev *dev)
140{
141 struct b43_phy *phy = &dev->phy;
142 struct b43_phy_lcn *phy_lcn = phy->lcn;
143
144 kfree(phy_lcn);
145 phy->lcn = NULL;
146}
147
148static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
149{
150 struct b43_phy *phy = &dev->phy;
151 struct b43_phy_lcn *phy_lcn = phy->lcn;
152
153 memset(phy_lcn, 0, sizeof(*phy_lcn));
154}
155
Rafał Miłecki78bc2462011-08-15 18:50:55 +0200156static int b43_phy_lcn_op_init(struct b43_wldev *dev)
157{
158 b43_phy_set(dev, 0x44a, 0x80);
159 b43_phy_mask(dev, 0x44a, 0x7f);
160 b43_phy_set(dev, 0x6d1, 0x80);
161 b43_phy_write(dev, 0x6d0, 0x7);
162
163 b43_phy_lcn_afe_set_unset(dev);
164
165 b43_phy_write(dev, 0x60a, 0xa0);
166 b43_phy_write(dev, 0x46a, 0x19);
167 b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
168
169 b43_phy_lcn_tables_init(dev);
170 /* TODO: various tables ops here */
171 b43_phy_lcn_clean_0x18_table(dev);
172
173 /* TODO: some ops here */
174
175 b43_phy_lcn_clear_0x07_table(dev);
176
Rafał Miłeckidc713fb2011-08-15 18:50:56 +0200177 if (dev->phy.radio_ver == 0x2064)
178 b43_radio_2064_init(dev);
179 else
180 B43_WARN_ON(1);
181
Rafał Miłecki78bc2462011-08-15 18:50:55 +0200182 return 0;
183}
184
Rafał Miłeckiba356b52011-08-14 23:27:29 +0200185static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
186 bool blocked)
187{
188 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
189 b43err(dev->wl, "MAC not suspended\n");
190
191 if (blocked) {
192 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
193 b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
194
195 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
196 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
197 b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
198
199 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
200 b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
201 } else {
Rafał Miłecki78bc2462011-08-15 18:50:55 +0200202 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
203 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
204 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
Rafał Miłeckiba356b52011-08-14 23:27:29 +0200205 }
206}
207
Rafał Miłecki7ed88522011-08-14 23:27:30 +0200208static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
209{
210 if (on) {
211 b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
212 } else {
213 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
214 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
215 }
216}
217
Rafał Miłeckif9286682011-08-14 23:27:28 +0200218static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
219{
220 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
221 return 1;
222 return 36;
223}
224
225static enum b43_txpwr_result
226b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
227{
228 return B43_TXPWR_RES_DONE;
229}
230
231static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
232{
233}
234
235/**************************************************
Rafał Miłeckif533d0f2011-08-28 14:28:43 +0200236 * R/W ops.
237 **************************************************/
238
239static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
240{
241 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
242 return b43_read16(dev, B43_MMIO_PHY_DATA);
243}
244
245static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
246{
247 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
248 b43_write16(dev, B43_MMIO_PHY_DATA, value);
249}
250
251static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
252 u16 set)
253{
254 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
255 b43_write16(dev, B43_MMIO_PHY_DATA,
256 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
257}
258
259static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
260{
261 /* LCN-PHY needs 0x200 for read access */
262 reg |= 0x200;
263
264 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
265 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
266}
267
268static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
269 u16 value)
270{
271 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
272 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
273}
274
275/**************************************************
Rafał Miłecki1d738e62011-07-07 15:25:27 +0200276 * PHY ops struct.
277 **************************************************/
278
279const struct b43_phy_operations b43_phyops_lcn = {
Rafał Miłecki1d738e62011-07-07 15:25:27 +0200280 .allocate = b43_phy_lcn_op_allocate,
281 .free = b43_phy_lcn_op_free,
282 .prepare_structs = b43_phy_lcn_op_prepare_structs,
283 .init = b43_phy_lcn_op_init,
284 .phy_read = b43_phy_lcn_op_read,
285 .phy_write = b43_phy_lcn_op_write,
286 .phy_maskset = b43_phy_lcn_op_maskset,
287 .radio_read = b43_phy_lcn_op_radio_read,
288 .radio_write = b43_phy_lcn_op_radio_write,
289 .software_rfkill = b43_phy_lcn_op_software_rfkill,
290 .switch_analog = b43_phy_lcn_op_switch_analog,
Rafał Miłecki7ed88522011-08-14 23:27:30 +0200291 /*
Rafał Miłecki1d738e62011-07-07 15:25:27 +0200292 .switch_channel = b43_phy_lcn_op_switch_channel,
Rafał Miłeckif9286682011-08-14 23:27:28 +0200293 */
Rafał Miłecki1d738e62011-07-07 15:25:27 +0200294 .get_default_chan = b43_phy_lcn_op_get_default_chan,
295 .recalc_txpower = b43_phy_lcn_op_recalc_txpower,
296 .adjust_txpower = b43_phy_lcn_op_adjust_txpower,
Rafał Miłecki1d738e62011-07-07 15:25:27 +0200297};