Lars Persson | f56454f | 2016-02-11 17:06:17 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Device Tree Source for the Axis ARTPEC-6 SoC |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public License |
| 5 | * version 2. This program is licensed "as is" without any warranty of any |
| 6 | * kind, whether express or implied. |
| 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include "skeleton.dtsi" |
| 11 | |
| 12 | / { |
| 13 | compatible = "axis,artpec6"; |
| 14 | interrupt-parent = <&intc>; |
| 15 | |
| 16 | cpus { |
| 17 | #address-cells = <1>; |
| 18 | #size-cells = <0>; |
| 19 | |
| 20 | cpu0: cpu@0 { |
| 21 | device_type = "cpu"; |
| 22 | compatible = "arm,cortex-a9"; |
| 23 | reg = <0>; |
| 24 | next-level-cache = <&pl310>; |
| 25 | }; |
| 26 | |
| 27 | cpu1: cpu@1 { |
| 28 | device_type = "cpu"; |
| 29 | compatible = "arm,cortex-a9"; |
| 30 | reg = <1>; |
| 31 | next-level-cache = <&pl310>; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | syscon { |
| 36 | compatible = "axis,artpec6-syscon", "syscon"; |
| 37 | reg = <0xf8000000 0x48>; |
| 38 | }; |
| 39 | |
| 40 | psci { |
| 41 | compatible = "arm,psci-0.2", "arm,psci"; |
| 42 | method = "smc"; |
| 43 | psci_version = <0x84000000>; |
| 44 | cpu_on = <0x84000003>; |
| 45 | system_reset = <0x84000009>; |
| 46 | }; |
| 47 | |
| 48 | scu@faf00000 { |
| 49 | compatible = "arm,cortex-a9-scu"; |
| 50 | reg = <0xfaf00000 0x58>; |
| 51 | }; |
| 52 | |
| 53 | /* Main external clock driving CPU and peripherals */ |
| 54 | ext_clk: ext_clk { |
| 55 | #clock-cells = <0>; |
| 56 | compatible = "fixed-clock"; |
| 57 | clock-frequency = <50000000>; |
| 58 | }; |
| 59 | |
| 60 | /* PLL1 is used by CPU and some peripherals */ |
| 61 | pll1_clk: pll1_clk@f8000000 { |
| 62 | #clock-cells = <0>; |
| 63 | compatible = "axis,artpec6-pll1-clock"; |
| 64 | reg = <0xf8000000 4>; |
| 65 | clocks = <&ext_clk>; |
| 66 | }; |
| 67 | |
| 68 | cpu_clk: cpu_clk { |
| 69 | #clock-cells = <0>; |
| 70 | compatible = "fixed-factor-clock"; |
| 71 | clock-div = <1>; |
| 72 | clock-mult = <1>; |
| 73 | clocks = <&pll1_clk>; |
| 74 | clock-output-names = "cpu_clk"; |
| 75 | }; |
| 76 | |
| 77 | cpu_clkdiv2: cpu_clkdiv2 { |
| 78 | #clock-cells = <0>; |
| 79 | compatible = "fixed-factor-clock"; |
| 80 | clock-div = <2>; |
| 81 | clock-mult = <1>; |
| 82 | clocks = <&cpu_clk>; |
| 83 | }; |
| 84 | |
| 85 | cpu_clkdiv4: cpu_clkdiv4 { |
| 86 | #clock-cells = <0>; |
| 87 | compatible = "fixed-factor-clock"; |
| 88 | clock-div = <4>; |
| 89 | clock-mult = <1>; |
| 90 | clocks = <&cpu_clk>; |
| 91 | }; |
| 92 | |
| 93 | apb_pclk: apb_pclk { |
| 94 | #clock-cells = <0>; |
| 95 | compatible = "fixed-factor-clock"; |
| 96 | clock-div = <8>; |
| 97 | clock-mult = <1>; |
| 98 | clocks = <&cpu_clk>; |
| 99 | clock-output-names = "apb_pclk"; |
| 100 | }; |
| 101 | |
| 102 | /* PLL2 is used by a number of peripherals, including UDL */ |
| 103 | pll2: pll2 { |
| 104 | #clock-cells = <0>; |
| 105 | compatible = "fixed-factor-clock"; |
| 106 | clock-div = <1>; |
| 107 | clock-mult = <24>; |
| 108 | clocks = <&ext_clk>; |
| 109 | }; |
| 110 | |
| 111 | /* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */ |
| 112 | pll2div2: pll2div2 { |
| 113 | #clock-cells = <0>; |
| 114 | compatible = "fixed-factor-clock"; |
| 115 | clock-div = <2>; |
| 116 | clock-mult = <1>; |
| 117 | clocks = <&pll2>; |
| 118 | }; |
| 119 | |
| 120 | pll2div12: pll2div12 { |
| 121 | #clock-cells = <0>; |
| 122 | compatible = "fixed-factor-clock"; |
| 123 | clock-div = <12>; |
| 124 | clock-mult = <1>; |
| 125 | clocks = <&pll2>; |
| 126 | }; |
| 127 | |
| 128 | pll2div24: pll2div24 { |
| 129 | #clock-cells = <0>; |
| 130 | compatible = "fixed-factor-clock"; |
| 131 | clock-div = <24>; |
| 132 | clock-mult = <1>; |
| 133 | clocks = <&pll2>; |
| 134 | clock-output-names = "uart_clk"; |
| 135 | }; |
| 136 | |
| 137 | |
| 138 | gtimer@faf00200 { |
| 139 | compatible = "arm,cortex-a9-global-timer"; |
| 140 | reg = <0xfaf00200 0x20>; |
| 141 | interrupts = <GIC_PPI 11 0xf01>; |
| 142 | clocks = <&cpu_clkdiv2>; |
| 143 | }; |
| 144 | |
| 145 | timer@faf00600 { |
| 146 | compatible = "arm,cortex-a9-twd-timer"; |
| 147 | reg = <0xfaf00600 0x20>; |
| 148 | interrupts = <GIC_PPI 13 0xf04>; |
| 149 | clocks = <&cpu_clkdiv2>; |
| 150 | status = "disabled"; |
| 151 | }; |
| 152 | |
| 153 | intc: interrupt-controller@faf01000 { |
| 154 | interrupt-controller; |
| 155 | compatible = "arm,cortex-a9-gic"; |
| 156 | #interrupt-cells = <3>; |
| 157 | reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; |
| 158 | }; |
| 159 | |
| 160 | pl310: cache-controller@faf10000 { |
| 161 | compatible = "arm,pl310-cache"; |
| 162 | cache-unified; |
| 163 | cache-level = <2>; |
| 164 | reg = <0xfaf10000 0x1000>; |
| 165 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| 166 | arm,data-latency = <1 1 1>; |
| 167 | arm,tag-latency = <1 1 1>; |
| 168 | arm,filter-ranges = <0x0 0x80000000>; |
| 169 | }; |
| 170 | |
| 171 | pmu { |
| 172 | compatible = "arm,cortex-a9-pmu"; |
| 173 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 174 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 175 | interrupt-parent = <&intc>; |
| 176 | }; |
| 177 | |
| 178 | amba@0 { |
| 179 | compatible = "simple-bus"; |
| 180 | #address-cells = <0x1>; |
| 181 | #size-cells = <0x1>; |
| 182 | interrupt-parent = <&intc>; |
| 183 | ranges; |
| 184 | dma-ranges = <0x80000000 0x00000000 0x40000000>; |
| 185 | dma-coherent; |
| 186 | |
| 187 | ethernet: ethernet@f8010000 { |
| 188 | clock-names = "phy_ref_clk", "apb_pclk"; |
| 189 | clocks = <&ext_clk>, <&apb_pclk>; |
| 190 | compatible = "snps,dwc-qos-ethernet-4.10"; |
| 191 | interrupt-parent = <&intc>; |
| 192 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 193 | reg = <0xf8010000 0x4000>; |
| 194 | |
| 195 | snps,write-requests = <2>; |
| 196 | snps,read-requests = <16>; |
| 197 | snps,txpbl = <8>; |
| 198 | snps,rxpbl = <2>; |
| 199 | |
| 200 | status = "disabled"; |
| 201 | }; |
| 202 | |
| 203 | uart0: serial@f8036000 { |
| 204 | compatible = "arm,pl011", "arm,primecell"; |
| 205 | reg = <0xf8036000 0x1000>; |
| 206 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 207 | clocks = <&pll2div24>, <&apb_pclk>; |
| 208 | clock-names = "uart_clk", "apb_pclk"; |
| 209 | status = "disabled"; |
| 210 | }; |
| 211 | uart1: serial@f8037000 { |
| 212 | compatible = "arm,pl011", "arm,primecell"; |
| 213 | reg = <0xf8037000 0x1000>; |
| 214 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | clocks = <&pll2div24>, <&apb_pclk>; |
| 216 | clock-names = "uart_clk", "apb_pclk"; |
| 217 | status = "disabled"; |
| 218 | }; |
| 219 | uart2: serial@f8038000 { |
| 220 | compatible = "arm,pl011", "arm,primecell"; |
| 221 | reg = <0xf8038000 0x1000>; |
| 222 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 223 | clocks = <&pll2div24>, <&apb_pclk>; |
| 224 | clock-names = "uart_clk", "apb_pclk"; |
| 225 | status = "disabled"; |
| 226 | }; |
| 227 | uart3: serial@f8039000 { |
| 228 | compatible = "arm,pl011", "arm,primecell"; |
| 229 | reg = <0xf8039000 0x1000>; |
| 230 | interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| 231 | clocks = <&pll2div24>, <&apb_pclk>; |
| 232 | clock-names = "uart_clk", "apb_pclk"; |
| 233 | status = "disabled"; |
| 234 | }; |
| 235 | }; |
| 236 | }; |