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Catalin Marinasdcfdae02011-11-22 17:30:29 +00001/*
2 * arch/arm/include/asm/pgtable-3level.h
3 *
4 * Copyright (C) 2011 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef _ASM_PGTABLE_3LEVEL_H
21#define _ASM_PGTABLE_3LEVEL_H
22
23/*
24 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
25 * 8 bytes each, occupying a 4K page. The first level table covers a range of
26 * 512GB, each entry representing 1GB. Since we are limited to 4GB input
27 * address range, only 4 entries in the PGD are used.
28 *
29 * There are enough spare bits in a page table entry for the kernel specific
30 * state.
31 */
32#define PTRS_PER_PTE 512
33#define PTRS_PER_PMD 512
34#define PTRS_PER_PGD 4
35
Will Deacone38a5172013-05-02 13:52:01 +010036#define PTE_HWTABLE_PTRS (0)
Catalin Marinasdcfdae02011-11-22 17:30:29 +000037#define PTE_HWTABLE_OFF (0)
38#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
39
40/*
41 * PGDIR_SHIFT determines the size a top-level page table entry can map.
42 */
43#define PGDIR_SHIFT 30
44
45/*
46 * PMD_SHIFT determines the size a middle-level page table entry can map.
47 */
48#define PMD_SHIFT 21
49
50#define PMD_SIZE (1UL << PMD_SHIFT)
Cyril Chemparathy926edcc2012-07-22 13:40:38 -040051#define PMD_MASK (~((1 << PMD_SHIFT) - 1))
Catalin Marinasdcfdae02011-11-22 17:30:29 +000052#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
Cyril Chemparathy926edcc2012-07-22 13:40:38 -040053#define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1))
Catalin Marinasdcfdae02011-11-22 17:30:29 +000054
55/*
56 * section address mask and size definitions.
57 */
58#define SECTION_SHIFT 21
59#define SECTION_SIZE (1UL << SECTION_SHIFT)
Cyril Chemparathy926edcc2012-07-22 13:40:38 -040060#define SECTION_MASK (~((1 << SECTION_SHIFT) - 1))
Catalin Marinasdcfdae02011-11-22 17:30:29 +000061
62#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
63
64/*
Catalin Marinas1355e2a2012-07-25 14:32:38 +010065 * Hugetlb definitions.
66 */
67#define HPAGE_SHIFT PMD_SHIFT
68#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
69#define HPAGE_MASK (~(HPAGE_SIZE - 1))
70#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
71
72/*
Catalin Marinasdcfdae02011-11-22 17:30:29 +000073 * "Linux" PTE definitions for LPAE.
74 *
75 * These bits overlap with the hardware bits but the naming is preserved for
76 * consistency with the classic page table format.
77 */
Will Deacondbf62d52012-07-19 11:51:05 +010078#define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
79#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
Catalin Marinasdcfdae02011-11-22 17:30:29 +000080#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
Catalin Marinasdcfdae02011-11-22 17:30:29 +000081#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
82#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
83#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
84#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
85#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
86#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */
87#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
Will Deacon26ffd0d2012-09-01 05:22:12 +010088#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
Catalin Marinasdcfdae02011-11-22 17:30:29 +000089
Catalin Marinas8d962502012-07-25 14:39:26 +010090#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
91#define PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
92#define PMD_SECT_SPLITTING (_AT(pmdval_t, 1) << 56)
93#define PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
94
Catalin Marinasdcfdae02011-11-22 17:30:29 +000095/*
96 * To be used in assembly code with the upper page attributes.
97 */
98#define L_PTE_XN_HIGH (1 << (54 - 32))
99#define L_PTE_DIRTY_HIGH (1 << (55 - 32))
100
101/*
102 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
103 */
104#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
105#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
106#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
107#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
108#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
109#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
110#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
111#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
112#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
113#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
114
Catalin Marinasda028772011-11-22 17:30:29 +0000115/*
116 * Software PGD flags.
117 */
118#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
119
Christoffer Dallcc577c22013-01-20 18:28:04 -0500120/*
121 * 2nd stage PTE definitions for LPAE.
122 */
123#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
124#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
125#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
126#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
Marc Zyngier865499e2013-04-12 14:00:16 +0100127#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
Christoffer Dallcc577c22013-01-20 18:28:04 -0500128
129/*
130 * Hyp-mode PL2 PTE definitions for LPAE.
131 */
132#define L_PTE_HYP L_PTE_USER
133
Catalin Marinasda028772011-11-22 17:30:29 +0000134#ifndef __ASSEMBLY__
135
136#define pud_none(pud) (!pud_val(pud))
137#define pud_bad(pud) (!(pud_val(pud) & 2))
138#define pud_present(pud) (pud_val(pud))
Christoffer Dallcc577c22013-01-20 18:28:04 -0500139#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
140 PMD_TYPE_TABLE)
141#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
142 PMD_TYPE_SECT)
Catalin Marinasda028772011-11-22 17:30:29 +0000143
144#define pud_clear(pudp) \
145 do { \
146 *pudp = __pud(0); \
147 clean_pmd_entry(pudp); \
148 } while (0)
149
150#define set_pud(pudp, pud) \
151 do { \
152 *pudp = pud; \
153 flush_pmd_entry(pudp); \
154 } while (0)
155
156static inline pmd_t *pud_page_vaddr(pud_t pud)
157{
158 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
159}
160
161/* Find an entry in the second-level page table.. */
162#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
163static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
164{
165 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
166}
167
168#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
169
170#define copy_pmd(pmdpd,pmdps) \
171 do { \
172 *pmdpd = *pmdps; \
173 flush_pmd_entry(pmdpd); \
174 } while (0)
175
176#define pmd_clear(pmdp) \
177 do { \
178 *pmdp = __pmd(0); \
179 clean_pmd_entry(pmdp); \
180 } while (0)
181
Steve Capperdde1b652013-05-17 12:32:55 +0100182/*
183 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
184 * that are written to a page table but not for ptes created with mk_pte.
185 *
186 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
187 * hugetlb_cow, where it is compared with an entry in a page table.
188 * This comparison test fails erroneously leading ultimately to a memory leak.
189 *
190 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
191 * present before running the comparison.
192 */
193#define __HAVE_ARCH_PTE_SAME
194#define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
195 : pte_val(pte_a)) \
196 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
197 : pte_val(pte_b)))
198
Catalin Marinasda028772011-11-22 17:30:29 +0000199#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
200
Catalin Marinas1355e2a2012-07-25 14:32:38 +0100201#define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
202#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
203
Catalin Marinas8d962502012-07-25 14:39:26 +0100204#define pmd_young(pmd) (pmd_val(pmd) & PMD_SECT_AF)
205
206#define __HAVE_ARCH_PMD_WRITE
207#define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY))
208
209#ifdef CONFIG_TRANSPARENT_HUGEPAGE
210#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
211#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
212#endif
213
214#define PMD_BIT_FUNC(fn,op) \
215static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
216
217PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
218PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
219PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
220PMD_BIT_FUNC(mkwrite, &= ~PMD_SECT_RDONLY);
221PMD_BIT_FUNC(mkdirty, |= PMD_SECT_DIRTY);
222PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
223
224#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
225
226#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
227#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
228#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
229
230/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
231#define pmd_mknotpresent(pmd) (__pmd(0))
232
233static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
234{
235 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
236 PMD_SECT_VALID | PMD_SECT_NONE;
237 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
238 return pmd;
239}
240
241static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
242 pmd_t *pmdp, pmd_t pmd)
243{
244 BUG_ON(addr >= TASK_SIZE);
245
246 /* create a faulting entry if PROT_NONE protected */
247 if (pmd_val(pmd) & PMD_SECT_NONE)
248 pmd_val(pmd) &= ~PMD_SECT_VALID;
249
250 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
251 flush_pmd_entry(pmdp);
252}
253
254static inline int has_transparent_hugepage(void)
255{
256 return 1;
257}
258
Catalin Marinasda028772011-11-22 17:30:29 +0000259#endif /* __ASSEMBLY__ */
260
Catalin Marinasdcfdae02011-11-22 17:30:29 +0000261#endif /* _ASM_PGTABLE_3LEVEL_H */