John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License version 2 as published |
| 4 | * by the Free Software Foundation. |
| 5 | * |
| 6 | * Parts of this file are based on Ralink's 2.6.21 BSP |
| 7 | * |
| 8 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 9 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 10 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | |
| 17 | #include <asm/mipsregs.h> |
| 18 | #include <asm/mach-ralink/ralink_regs.h> |
| 19 | #include <asm/mach-ralink/mt7620.h> |
John Crispin | f576fb6 | 2014-10-09 04:02:53 +0200 | [diff] [blame^] | 20 | #include <asm/mach-ralink/pinmux.h> |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 21 | |
| 22 | #include "common.h" |
| 23 | |
John Crispin | 2adf550 | 2014-07-27 09:16:50 +0100 | [diff] [blame] | 24 | /* analog */ |
| 25 | #define PMU0_CFG 0x88 |
| 26 | #define PMU_SW_SET BIT(28) |
| 27 | #define A_DCDC_EN BIT(24) |
| 28 | #define A_SSC_PERI BIT(19) |
| 29 | #define A_SSC_GEN BIT(18) |
| 30 | #define A_SSC_M 0x3 |
| 31 | #define A_SSC_S 16 |
| 32 | #define A_DLY_M 0x7 |
| 33 | #define A_DLY_S 8 |
| 34 | #define A_VTUNE_M 0xff |
| 35 | |
| 36 | /* digital */ |
| 37 | #define PMU1_CFG 0x8C |
| 38 | #define DIG_SW_SEL BIT(25) |
| 39 | |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 40 | /* does the board have sdram or ddram */ |
| 41 | static int dram_type; |
| 42 | |
John Crispin | f576fb6 | 2014-10-09 04:02:53 +0200 | [diff] [blame^] | 43 | static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; |
| 44 | static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; |
| 45 | static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; |
| 46 | static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; |
| 47 | static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; |
| 48 | static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; |
| 49 | static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; |
| 50 | static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; |
| 51 | static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; |
| 52 | static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; |
| 53 | static struct rt2880_pmx_func uartf_grp[] = { |
| 54 | FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), |
| 55 | FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), |
| 56 | FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), |
| 57 | FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), |
| 58 | FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), |
| 59 | FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), |
| 60 | FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), |
| 61 | }; |
| 62 | static struct rt2880_pmx_func wdt_grp[] = { |
| 63 | FUNC("wdt rst", 0, 17, 1), |
| 64 | FUNC("wdt refclk", 0, 17, 1), |
| 65 | }; |
| 66 | static struct rt2880_pmx_func pcie_rst_grp[] = { |
| 67 | FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), |
| 68 | FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) |
| 69 | }; |
| 70 | static struct rt2880_pmx_func nd_sd_grp[] = { |
| 71 | FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), |
| 72 | FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15) |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 73 | }; |
| 74 | |
John Crispin | f576fb6 | 2014-10-09 04:02:53 +0200 | [diff] [blame^] | 75 | static struct rt2880_pmx_group mt7620a_pinmux_data[] = { |
| 76 | GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), |
| 77 | GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, |
| 78 | MT7620_GPIO_MODE_UART0_SHIFT), |
| 79 | GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), |
| 80 | GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), |
| 81 | GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, |
| 82 | MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), |
| 83 | GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO), |
| 84 | GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), |
| 85 | GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), |
| 86 | GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, |
| 87 | MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), |
| 88 | GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, |
| 89 | MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), |
| 90 | GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), |
| 91 | GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), |
| 92 | GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), |
| 93 | GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), |
| 94 | { 0 } |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 95 | }; |
| 96 | |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 97 | static __init u32 |
| 98 | mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) |
| 99 | { |
| 100 | u64 t; |
| 101 | |
| 102 | t = ref_rate; |
| 103 | t *= mul; |
| 104 | do_div(t, div); |
| 105 | |
| 106 | return t; |
| 107 | } |
| 108 | |
| 109 | #define MHZ(x) ((x) * 1000 * 1000) |
| 110 | |
| 111 | static __init unsigned long |
| 112 | mt7620_get_xtal_rate(void) |
| 113 | { |
| 114 | u32 reg; |
| 115 | |
| 116 | reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); |
| 117 | if (reg & SYSCFG0_XTAL_FREQ_SEL) |
| 118 | return MHZ(40); |
| 119 | |
| 120 | return MHZ(20); |
| 121 | } |
| 122 | |
| 123 | static __init unsigned long |
| 124 | mt7620_get_periph_rate(unsigned long xtal_rate) |
| 125 | { |
| 126 | u32 reg; |
| 127 | |
| 128 | reg = rt_sysc_r32(SYSC_REG_CLKCFG0); |
| 129 | if (reg & CLKCFG0_PERI_CLK_SEL) |
| 130 | return xtal_rate; |
| 131 | |
| 132 | return MHZ(40); |
| 133 | } |
| 134 | |
| 135 | static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; |
| 136 | |
| 137 | static __init unsigned long |
| 138 | mt7620_get_cpu_pll_rate(unsigned long xtal_rate) |
| 139 | { |
| 140 | u32 reg; |
| 141 | u32 mul; |
| 142 | u32 div; |
| 143 | |
| 144 | reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); |
| 145 | if (reg & CPLL_CFG0_BYPASS_REF_CLK) |
| 146 | return xtal_rate; |
| 147 | |
| 148 | if ((reg & CPLL_CFG0_SW_CFG) == 0) |
| 149 | return MHZ(600); |
| 150 | |
| 151 | mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & |
| 152 | CPLL_CFG0_PLL_MULT_RATIO_MASK; |
| 153 | mul += 24; |
| 154 | if (reg & CPLL_CFG0_LC_CURFCK) |
| 155 | mul *= 2; |
| 156 | |
| 157 | div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & |
| 158 | CPLL_CFG0_PLL_DIV_RATIO_MASK; |
| 159 | |
| 160 | WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); |
| 161 | |
| 162 | return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); |
| 163 | } |
| 164 | |
| 165 | static __init unsigned long |
| 166 | mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) |
| 167 | { |
| 168 | u32 reg; |
| 169 | |
| 170 | reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); |
| 171 | if (reg & CPLL_CFG1_CPU_AUX1) |
| 172 | return xtal_rate; |
| 173 | |
| 174 | if (reg & CPLL_CFG1_CPU_AUX0) |
| 175 | return MHZ(480); |
| 176 | |
| 177 | return cpu_pll_rate; |
| 178 | } |
| 179 | |
| 180 | static __init unsigned long |
| 181 | mt7620_get_cpu_rate(unsigned long pll_rate) |
| 182 | { |
| 183 | u32 reg; |
| 184 | u32 mul; |
| 185 | u32 div; |
| 186 | |
| 187 | reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); |
| 188 | |
| 189 | mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; |
| 190 | div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & |
| 191 | CPU_SYS_CLKCFG_CPU_FDIV_MASK; |
| 192 | |
| 193 | return mt7620_calc_rate(pll_rate, mul, div); |
| 194 | } |
| 195 | |
| 196 | static const u32 mt7620_ocp_dividers[16] __initconst = { |
| 197 | [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, |
| 198 | [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, |
| 199 | [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, |
| 200 | [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, |
| 201 | [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, |
| 202 | }; |
| 203 | |
| 204 | static __init unsigned long |
| 205 | mt7620_get_dram_rate(unsigned long pll_rate) |
| 206 | { |
| 207 | if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) |
| 208 | return pll_rate / 4; |
| 209 | |
| 210 | return pll_rate / 3; |
| 211 | } |
| 212 | |
| 213 | static __init unsigned long |
| 214 | mt7620_get_sys_rate(unsigned long cpu_rate) |
| 215 | { |
| 216 | u32 reg; |
| 217 | u32 ocp_ratio; |
| 218 | u32 div; |
| 219 | |
| 220 | reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); |
| 221 | |
| 222 | ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & |
| 223 | CPU_SYS_CLKCFG_OCP_RATIO_MASK; |
| 224 | |
| 225 | if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) |
| 226 | return cpu_rate; |
| 227 | |
| 228 | div = mt7620_ocp_dividers[ocp_ratio]; |
| 229 | if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) |
| 230 | return cpu_rate; |
| 231 | |
| 232 | return cpu_rate / div; |
| 233 | } |
| 234 | |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 235 | void __init ralink_clk_init(void) |
| 236 | { |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 237 | unsigned long xtal_rate; |
| 238 | unsigned long cpu_pll_rate; |
| 239 | unsigned long pll_rate; |
| 240 | unsigned long cpu_rate; |
| 241 | unsigned long sys_rate; |
| 242 | unsigned long dram_rate; |
| 243 | unsigned long periph_rate; |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 244 | |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 245 | xtal_rate = mt7620_get_xtal_rate(); |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 246 | |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 247 | cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); |
| 248 | pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 249 | |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 250 | cpu_rate = mt7620_get_cpu_rate(pll_rate); |
| 251 | dram_rate = mt7620_get_dram_rate(pll_rate); |
| 252 | sys_rate = mt7620_get_sys_rate(cpu_rate); |
| 253 | periph_rate = mt7620_get_periph_rate(xtal_rate); |
| 254 | |
| 255 | #define RFMT(label) label ":%lu.%03luMHz " |
| 256 | #define RINT(x) ((x) / 1000000) |
| 257 | #define RFRAC(x) (((x) / 1000) % 1000) |
| 258 | |
| 259 | pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), |
| 260 | RINT(xtal_rate), RFRAC(xtal_rate), |
| 261 | RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), |
| 262 | RINT(pll_rate), RFRAC(pll_rate)); |
| 263 | |
| 264 | pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), |
| 265 | RINT(cpu_rate), RFRAC(cpu_rate), |
| 266 | RINT(dram_rate), RFRAC(dram_rate), |
| 267 | RINT(sys_rate), RFRAC(sys_rate), |
| 268 | RINT(periph_rate), RFRAC(periph_rate)); |
| 269 | |
| 270 | #undef RFRAC |
| 271 | #undef RINT |
| 272 | #undef RFMT |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 273 | |
| 274 | ralink_clk_add("cpu", cpu_rate); |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 275 | ralink_clk_add("10000100.timer", periph_rate); |
John Crispin | 68c9b7e | 2013-08-23 08:31:31 +0200 | [diff] [blame] | 276 | ralink_clk_add("10000120.watchdog", periph_rate); |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 277 | ralink_clk_add("10000500.uart", periph_rate); |
John Crispin | 0d46496 | 2013-08-23 08:31:32 +0200 | [diff] [blame] | 278 | ralink_clk_add("10000b00.spi", sys_rate); |
Gabor Juhos | ded1e9d | 2013-08-23 08:31:30 +0200 | [diff] [blame] | 279 | ralink_clk_add("10000c00.uartlite", periph_rate); |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | void __init ralink_of_remap(void) |
| 283 | { |
| 284 | rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); |
| 285 | rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); |
| 286 | |
| 287 | if (!rt_sysc_membase || !rt_memc_membase) |
| 288 | panic("Failed to remap core resources"); |
| 289 | } |
| 290 | |
| 291 | void prom_soc_init(struct ralink_soc_info *soc_info) |
| 292 | { |
| 293 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); |
| 294 | unsigned char *name = NULL; |
| 295 | u32 n0; |
| 296 | u32 n1; |
| 297 | u32 rev; |
| 298 | u32 cfg0; |
John Crispin | 2adf550 | 2014-07-27 09:16:50 +0100 | [diff] [blame] | 299 | u32 pmu0; |
| 300 | u32 pmu1; |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 301 | |
| 302 | n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); |
| 303 | n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); |
| 304 | |
| 305 | if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) { |
| 306 | name = "MT7620N"; |
| 307 | soc_info->compatible = "ralink,mt7620n-soc"; |
| 308 | } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) { |
| 309 | name = "MT7620A"; |
| 310 | soc_info->compatible = "ralink,mt7620a-soc"; |
| 311 | } else { |
Ralf Baechle | f7777dc | 2013-09-18 16:05:26 +0200 | [diff] [blame] | 312 | panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); |
| 316 | |
| 317 | snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, |
| 318 | "Ralink %s ver:%u eco:%u", |
| 319 | name, |
| 320 | (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, |
| 321 | (rev & CHIP_REV_ECO_MASK)); |
| 322 | |
| 323 | cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); |
| 324 | dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; |
John Crispin | 51e3960 | 2013-04-14 09:55:29 +0200 | [diff] [blame] | 325 | |
| 326 | switch (dram_type) { |
| 327 | case SYSCFG0_DRAM_TYPE_SDRAM: |
John Crispin | 538e0da | 2013-08-08 13:17:48 +0200 | [diff] [blame] | 328 | pr_info("Board has SDRAM\n"); |
John Crispin | 51e3960 | 2013-04-14 09:55:29 +0200 | [diff] [blame] | 329 | soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; |
| 330 | soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; |
| 331 | break; |
| 332 | |
| 333 | case SYSCFG0_DRAM_TYPE_DDR1: |
John Crispin | 538e0da | 2013-08-08 13:17:48 +0200 | [diff] [blame] | 334 | pr_info("Board has DDR1\n"); |
John Crispin | 51e3960 | 2013-04-14 09:55:29 +0200 | [diff] [blame] | 335 | soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; |
| 336 | soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; |
| 337 | break; |
| 338 | |
| 339 | case SYSCFG0_DRAM_TYPE_DDR2: |
John Crispin | 538e0da | 2013-08-08 13:17:48 +0200 | [diff] [blame] | 340 | pr_info("Board has DDR2\n"); |
John Crispin | 51e3960 | 2013-04-14 09:55:29 +0200 | [diff] [blame] | 341 | soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; |
| 342 | soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; |
| 343 | break; |
| 344 | default: |
| 345 | BUG(); |
| 346 | } |
| 347 | soc_info->mem_base = MT7620_DRAM_BASE; |
John Crispin | 2adf550 | 2014-07-27 09:16:50 +0100 | [diff] [blame] | 348 | |
| 349 | pmu0 = __raw_readl(sysc + PMU0_CFG); |
| 350 | pmu1 = __raw_readl(sysc + PMU1_CFG); |
| 351 | |
| 352 | pr_info("Analog PMU set to %s control\n", |
| 353 | (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); |
| 354 | pr_info("Digital PMU set to %s control\n", |
| 355 | (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); |
John Crispin | 594bde6 | 2013-03-21 17:49:02 +0100 | [diff] [blame] | 356 | } |