Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / f5c7726ffc994f1826415852e7196bcb6c664d44 / . / arch / m68knommu / platform / 68360 / head-rom.S
blob: 2d28c3e19a881894d2f2389f0691db2364b06f29 [file] [log] [blame]
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]1/* arch/m68knommu/platform/68360/head-rom.S
2 *
3 * Startup code for Motorola 68360
4 *
5 * Copyright (C) SED Systems, a Division of Calian Ltd.
6 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
7 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
8 * uClinux Kernel
9 * Copyright (C) Michael Leslie <mleslie@lineo.com>
10 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
11 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
12 *
13 */
14#include <linux/config.h>
15
16.global _stext
17.global _sbss
18.global _start
19
20.global _rambase
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]21.global _ramvec
22.global _ramstart
23.global _ramend
24
25.global _quicc_base
26.global _periph_base
27
Greg Ungererf5c77262006-06-27 13:27:13 +1000[diff] [blame^]28#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
29
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]30#define REGB 0x1000
31#define PEPAR (_dprbase + REGB + 0x0016)
32#define GMR (_dprbase + REGB + 0x0040)
33#define OR0 (_dprbase + REGB + 0x0054)
34#define BR0 (_dprbase + REGB + 0x0050)
35
36#define OR1 (_dprbase + REGB + 0x0064)
37#define BR1 (_dprbase + REGB + 0x0060)
38
39#define OR2 (_dprbase + REGB + 0x0074)
40#define BR2 (_dprbase + REGB + 0x0070)
41
42#define OR3 (_dprbase + REGB + 0x0084)
43#define BR3 (_dprbase + REGB + 0x0080)
44
45#define OR4 (_dprbase + REGB + 0x0094)
46#define BR4 (_dprbase + REGB + 0x0090)
47
48#define OR5 (_dprbase + REGB + 0x00A4)
49#define BR5 (_dprbase + REGB + 0x00A0)
50
51#define OR6 (_dprbase + REGB + 0x00b4)
52#define BR6 (_dprbase + REGB + 0x00b0)
53
54#define OR7 (_dprbase + REGB + 0x00c4)
55#define BR7 (_dprbase + REGB + 0x00c0)
56
57#define MCR (_dprbase + REGB + 0x0000)
58#define AVR (_dprbase + REGB + 0x0008)
59
60#define SYPCR (_dprbase + REGB + 0x0022)
61
62#define PLLCR (_dprbase + REGB + 0x0010)
63#define CLKOCR (_dprbase + REGB + 0x000C)
64#define CDVCR (_dprbase + REGB + 0x0014)
65
66#define BKAR (_dprbase + REGB + 0x0030)
67#define BKCR (_dprbase + REGB + 0x0034)
68#define SWIV (_dprbase + REGB + 0x0023)
69#define PICR (_dprbase + REGB + 0x0026)
70#define PITR (_dprbase + REGB + 0x002A)
71
72/* Define for all memory configuration */
73#define MCU_SIM_GMR 0x00000000
74#define SIM_OR_MASK 0x0fffffff
75
76/* Defines for chip select zero - the flash */
77#define SIM_OR0_MASK 0x20000000
78#define SIM_BR0_MASK 0x00000001
79
80/* Defines for chip select one - the RAM */
81#define SIM_OR1_MASK 0x10000000
82#define SIM_BR1_MASK 0x00000001
83
84#define MCU_SIM_MBAR_ADRS 0x0003ff00
85#define MCU_SIM_MBAR_BA_MASK 0xfffff000
86#define MCU_SIM_MBAR_AS_MASK 0x00000001
87
88#define MCU_SIM_PEPAR 0x00B4
89
90#define MCU_DISABLE_INTRPTS 0x2700
91#define MCU_SIM_AVR 0x00
92
93#define MCU_SIM_MCR 0x00005cff
94
95#define MCU_SIM_CLKOCR 0x00
96#define MCU_SIM_PLLCR 0x8000
97#define MCU_SIM_CDVCR 0x0000
98
99#define MCU_SIM_SYPCR 0x0000
100#define MCU_SIM_SWIV 0x00
101#define MCU_SIM_PICR 0x0000
102#define MCU_SIM_PITR 0x0000
103
104
105#include <asm/m68360_regs.h>
106
107
108/*
109 * By the time this RAM specific code begins to execute, DPRAM
110 * and DRAM should already be mapped and accessible.
111 */
112
113 .text
114_start:
115_stext:
116 nop
117 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
118 /* We should not need to setup the boot stack the reset should do it. */
Greg Ungererf5c77262006-06-27 13:27:13 +1000[diff] [blame^]119 movea.l #RAMEND, %sp /* set up stack at the end of DRAM:*/
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]120
121
122set_mbar_register:
123 moveq.l #0x07, %d1 /* Setup MBAR */
124 movec %d1, %dfc
125
126 lea.l MCU_SIM_MBAR_ADRS, %a0
127 move.l #_dprbase, %d0
128 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
129 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
130 moves.l %d0, %a0@
131
132 moveq.l #0x05, %d1
133 movec.l %d1, %dfc
134
135 /* Now we can begin to access registers in DPRAM */
136
137set_sim_mcr:
138 /* Set Module Configuration Register */
139 move.l #MCU_SIM_MCR, MCR
140
141 /* to do: Determine cause of reset */
142
143 /*
144 * configure system clock MC68360 p. 6-40
145 * (value +1)*osc/128 = system clock
146 * or
147 * (value + 1)*osc = system clock
148 * You do not need to divide the oscillator by 128 unless you want to.
149 */
150set_sim_clock:
151 move.w #MCU_SIM_PLLCR, PLLCR
152 move.b #MCU_SIM_CLKOCR, CLKOCR
153 move.w #MCU_SIM_CDVCR, CDVCR
154
155 /* Wait for the PLL to settle */
156 move.w #16384, %d0
157pll_settle_wait:
158 subi.w #1, %d0
159 bne pll_settle_wait
160
161 /* Setup the system protection register, and watchdog timer register */
162 move.b #MCU_SIM_SWIV, SWIV
163 move.w #MCU_SIM_PICR, PICR
164 move.w #MCU_SIM_PITR, PITR
165 move.w #MCU_SIM_SYPCR, SYPCR
166
167 /* Clear DPRAM - system + parameter */
168 movea.l #_dprbase, %a0
169 movea.l #_dprbase+0x2000, %a1
170
171 /* Copy 0 to %a0 until %a0 == %a1 */
172clear_dpram:
173 movel #0, %a0@+
174 cmpal %a0, %a1
175 bhi clear_dpram
176
177configure_memory_controller:
178 /* Set up Global Memory Register (GMR) */
179 move.l #MCU_SIM_GMR, %d0
180 move.l %d0, GMR
181
182configure_chip_select_0:
183 move.l #0x00400000, %d0
184 subq.l #0x01, %d0
185 eori.l #SIM_OR_MASK, %d0
186 ori.l #SIM_OR0_MASK, %d0
187 move.l %d0, OR0
188
189 move.l #__rom_start, %d0
190 ori.l #SIM_BR0_MASK, %d0
191 move.l %d0, BR0
192
193 move.l #0x0, BR1
194 move.l #0x0, BR2
195 move.l #0x0, BR3
196 move.l #0x0, BR4
197 move.l #0x0, BR5
198 move.l #0x0, BR6
199 move.l #0x0, BR7
200
201 move.w #MCU_SIM_PEPAR, PEPAR
202
203 /* point to vector table: */
204 move.l #_romvec, %a0
205 move.l #_ramvec, %a1
206copy_vectors:
207 move.l %a0@, %d0
208 move.l %d0, %a1@
209 move.l %a0@, %a1@
210 addq.l #0x04, %a0
211 addq.l #0x04, %a1
212 cmp.l #_start, %a0
213 blt copy_vectors
214
215 move.l #_ramvec, %a1
216 movec %a1, %vbr
217
218
219 /* Copy data segment from ROM to RAM */
220 moveal #_etext, %a0
221 moveal #_sdata, %a1
222 moveal #_edata, %a2
223
224 /* Copy %a0 to %a1 until %a1 == %a2 */
225LD1:
226 move.l %a0@, %d0
227 addq.l #0x04, %a0
228 move.l %d0, %a1@
229 addq.l #0x04, %a1
230 cmp.l #_edata, %a1
231 blt LD1
232
233 moveal #_sbss, %a0
234 moveal #_ebss, %a1
235
236 /* Copy 0 to %a0 until %a0 == %a1 */
237L1:
238 movel #0, %a0@+
239 cmpal %a0, %a1
240 bhi L1
241
242load_quicc:
243 move.l #_dprbase, _quicc_base
244
245store_ram_size:
246 /* Set ram size information */
247 move.l #_sdata, _rambase
248 move.l #_ebss, _ramstart
Greg Ungererf5c77262006-06-27 13:27:13 +1000[diff] [blame^]249 move.l #RAMEND, %d0
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]250 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
Greg Ungererf5c77262006-06-27 13:27:13 +1000[diff] [blame^]251 move.l %d0, _ramend /* Different from RAMEND.*/
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]252
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]253 pea 0
254 pea env
255 pea %sp@(4)
256 pea 0
257
258 lea init_thread_union, %a2
259 lea 0x2000(%a2), %sp
260
261lp:
262 jsr start_kernel
263
264_exit:
265 jmp _exit
266
267
268 .data
269 .align 4
270env:
271 .long 0
272_quicc_base:
273 .long 0
274_periph_base:
275 .long 0
276_ramvec:
277 .long 0
278_rambase:
279 .long 0
280_ramstart:
281 .long 0
282_ramend:
283 .long 0
284_dprbase:
285 .long 0xffffe000
286
287
288 .text
289
290 /*
291 * These are the exception vectors at boot up, they are copied into RAM
292 * and then overwritten as needed.
293 */
294
295.section ".data.initvect","awx"
Greg Ungererf5c77262006-06-27 13:27:13 +1000[diff] [blame^]296 .long RAMEND /* Reset: Initial Stack Pointer - 0. */
Greg Ungerer42ae7662005-09-12 11:18:10 +1000[diff] [blame]297 .long _start /* Reset: Initial Program Counter - 1. */
298 .long buserr /* Bus Error - 2. */
299 .long trap /* Address Error - 3. */
300 .long trap /* Illegal Instruction - 4. */
301 .long trap /* Divide by zero - 5. */
302 .long trap /* CHK, CHK2 Instructions - 6. */
303 .long trap /* TRAPcc, TRAPV Instructions - 7. */
304 .long trap /* Privilege Violation - 8. */
305 .long trap /* Trace - 9. */
306 .long trap /* Line 1010 Emulator - 10. */
307 .long trap /* Line 1111 Emualtor - 11. */
308 .long trap /* Harware Breakpoint - 12. */
309 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
310 .long trap /* Format Error - 14. */
311 .long trap /* Uninitialized Interrupt - 15. */
312 .long trap /* (Unassigned, Reserver) - 16. */
313 .long trap /* (Unassigned, Reserver) - 17. */
314 .long trap /* (Unassigned, Reserver) - 18. */
315 .long trap /* (Unassigned, Reserver) - 19. */
316 .long trap /* (Unassigned, Reserver) - 20. */
317 .long trap /* (Unassigned, Reserver) - 21. */
318 .long trap /* (Unassigned, Reserver) - 22. */
319 .long trap /* (Unassigned, Reserver) - 23. */
320 .long trap /* Spurious Interrupt - 24. */
321 .long trap /* Level 1 Interrupt Autovector - 25. */
322 .long trap /* Level 2 Interrupt Autovector - 26. */
323 .long trap /* Level 3 Interrupt Autovector - 27. */
324 .long trap /* Level 4 Interrupt Autovector - 28. */
325 .long trap /* Level 5 Interrupt Autovector - 29. */
326 .long trap /* Level 6 Interrupt Autovector - 30. */
327 .long trap /* Level 7 Interrupt Autovector - 31. */
328 .long system_call /* Trap Instruction Vectors 0 - 32. */
329 .long trap /* Trap Instruction Vectors 1 - 33. */
330 .long trap /* Trap Instruction Vectors 2 - 34. */
331 .long trap /* Trap Instruction Vectors 3 - 35. */
332 .long trap /* Trap Instruction Vectors 4 - 36. */
333 .long trap /* Trap Instruction Vectors 5 - 37. */
334 .long trap /* Trap Instruction Vectors 6 - 38. */
335 .long trap /* Trap Instruction Vectors 7 - 39. */
336 .long trap /* Trap Instruction Vectors 8 - 40. */
337 .long trap /* Trap Instruction Vectors 9 - 41. */
338 .long trap /* Trap Instruction Vectors 10 - 42. */
339 .long trap /* Trap Instruction Vectors 11 - 43. */
340 .long trap /* Trap Instruction Vectors 12 - 44. */
341 .long trap /* Trap Instruction Vectors 13 - 45. */
342 .long trap /* Trap Instruction Vectors 14 - 46. */
343 .long trap /* Trap Instruction Vectors 15 - 47. */
344 .long 0 /* (Reserved for Coprocessor) - 48. */
345 .long 0 /* (Reserved for Coprocessor) - 49. */
346 .long 0 /* (Reserved for Coprocessor) - 50. */
347 .long 0 /* (Reserved for Coprocessor) - 51. */
348 .long 0 /* (Reserved for Coprocessor) - 52. */
349 .long 0 /* (Reserved for Coprocessor) - 53. */
350 .long 0 /* (Reserved for Coprocessor) - 54. */
351 .long 0 /* (Reserved for Coprocessor) - 55. */
352 .long 0 /* (Reserved for Coprocessor) - 56. */
353 .long 0 /* (Reserved for Coprocessor) - 57. */
354 .long 0 /* (Reserved for Coprocessor) - 58. */
355 .long 0 /* (Unassigned, Reserved) - 59. */
356 .long 0 /* (Unassigned, Reserved) - 60. */
357 .long 0 /* (Unassigned, Reserved) - 61. */
358 .long 0 /* (Unassigned, Reserved) - 62. */
359 .long 0 /* (Unassigned, Reserved) - 63. */
360 /* The assignment of these vectors to the CPM is */
361 /* dependent on the configuration of the CPM vba */
362 /* fields. */
363 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
364 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
365 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
366 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
367 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
368 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
369 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
370 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
371 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
372 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
373 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
374 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
375 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
376 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
377 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
378 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
379 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
380 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
381 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
382 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
383 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
384 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
385 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
386 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
387 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
388 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
389 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
390 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
391 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
392 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
393 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
394 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
395 /* I don't think anything uses the vectors after here. */
396 .long 0 /* (User-Defined Vectors 34) - 96. */
397 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
401 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
402 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
403 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
404 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
405 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
406 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
407 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
408 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
409 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
410 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
411 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
412 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
413 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
414.text
415ignore: rte