Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. |
| 4 | * |
| 5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. |
| 6 | * |
| 7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> |
| 8 | * PeiSen Hou <pshou@realtek.com.tw> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the Free |
| 12 | * Software Foundation; either version 2 of the License, or (at your option) |
| 13 | * any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 18 | * more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along with |
| 21 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 23 | * |
| 24 | * CONTACTS: |
| 25 | * |
| 26 | * Matt Jared matt.jared@intel.com |
| 27 | * Andy Kopp andy.kopp@intel.com |
| 28 | * Dan Kogan dan.d.kogan@intel.com |
| 29 | * |
| 30 | * CHANGES: |
| 31 | * |
| 32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou |
| 33 | * |
| 34 | */ |
| 35 | |
| 36 | #include <sound/driver.h> |
| 37 | #include <asm/io.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/interrupt.h> |
| 40 | #include <linux/module.h> |
| 41 | #include <linux/moduleparam.h> |
| 42 | #include <linux/init.h> |
| 43 | #include <linux/slab.h> |
| 44 | #include <linux/pci.h> |
| 45 | #include <sound/core.h> |
| 46 | #include <sound/initval.h> |
| 47 | #include "hda_codec.h" |
| 48 | |
| 49 | |
| 50 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
| 51 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
| 52 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; |
| 53 | static char *model[SNDRV_CARDS]; |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 54 | static int position_fix[SNDRV_CARDS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
| 56 | module_param_array(index, int, NULL, 0444); |
| 57 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
| 58 | module_param_array(id, charp, NULL, 0444); |
| 59 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
| 60 | module_param_array(enable, bool, NULL, 0444); |
| 61 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); |
| 62 | module_param_array(model, charp, NULL, 0444); |
| 63 | MODULE_PARM_DESC(model, "Use the given board model."); |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 64 | module_param_array(position_fix, bool, NULL, 0444); |
| 65 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF)."); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | |
| 67 | MODULE_LICENSE("GPL"); |
| 68 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," |
| 69 | "{Intel, ICH6M}," |
Jason Gaston | 2f1b381 | 2005-05-01 08:58:50 -0700 | [diff] [blame] | 70 | "{Intel, ICH7}," |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 71 | "{Intel, ESB2}," |
| 72 | "{ATI, SB450}}"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | MODULE_DESCRIPTION("Intel HDA driver"); |
| 74 | |
| 75 | #define SFX "hda-intel: " |
| 76 | |
| 77 | /* |
| 78 | * registers |
| 79 | */ |
| 80 | #define ICH6_REG_GCAP 0x00 |
| 81 | #define ICH6_REG_VMIN 0x02 |
| 82 | #define ICH6_REG_VMAJ 0x03 |
| 83 | #define ICH6_REG_OUTPAY 0x04 |
| 84 | #define ICH6_REG_INPAY 0x06 |
| 85 | #define ICH6_REG_GCTL 0x08 |
| 86 | #define ICH6_REG_WAKEEN 0x0c |
| 87 | #define ICH6_REG_STATESTS 0x0e |
| 88 | #define ICH6_REG_GSTS 0x10 |
| 89 | #define ICH6_REG_INTCTL 0x20 |
| 90 | #define ICH6_REG_INTSTS 0x24 |
| 91 | #define ICH6_REG_WALCLK 0x30 |
| 92 | #define ICH6_REG_SYNC 0x34 |
| 93 | #define ICH6_REG_CORBLBASE 0x40 |
| 94 | #define ICH6_REG_CORBUBASE 0x44 |
| 95 | #define ICH6_REG_CORBWP 0x48 |
| 96 | #define ICH6_REG_CORBRP 0x4A |
| 97 | #define ICH6_REG_CORBCTL 0x4c |
| 98 | #define ICH6_REG_CORBSTS 0x4d |
| 99 | #define ICH6_REG_CORBSIZE 0x4e |
| 100 | |
| 101 | #define ICH6_REG_RIRBLBASE 0x50 |
| 102 | #define ICH6_REG_RIRBUBASE 0x54 |
| 103 | #define ICH6_REG_RIRBWP 0x58 |
| 104 | #define ICH6_REG_RINTCNT 0x5a |
| 105 | #define ICH6_REG_RIRBCTL 0x5c |
| 106 | #define ICH6_REG_RIRBSTS 0x5d |
| 107 | #define ICH6_REG_RIRBSIZE 0x5e |
| 108 | |
| 109 | #define ICH6_REG_IC 0x60 |
| 110 | #define ICH6_REG_IR 0x64 |
| 111 | #define ICH6_REG_IRS 0x68 |
| 112 | #define ICH6_IRS_VALID (1<<1) |
| 113 | #define ICH6_IRS_BUSY (1<<0) |
| 114 | |
| 115 | #define ICH6_REG_DPLBASE 0x70 |
| 116 | #define ICH6_REG_DPUBASE 0x74 |
| 117 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ |
| 118 | |
| 119 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
| 120 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; |
| 121 | |
| 122 | /* stream register offsets from stream base */ |
| 123 | #define ICH6_REG_SD_CTL 0x00 |
| 124 | #define ICH6_REG_SD_STS 0x03 |
| 125 | #define ICH6_REG_SD_LPIB 0x04 |
| 126 | #define ICH6_REG_SD_CBL 0x08 |
| 127 | #define ICH6_REG_SD_LVI 0x0c |
| 128 | #define ICH6_REG_SD_FIFOW 0x0e |
| 129 | #define ICH6_REG_SD_FIFOSIZE 0x10 |
| 130 | #define ICH6_REG_SD_FORMAT 0x12 |
| 131 | #define ICH6_REG_SD_BDLPL 0x18 |
| 132 | #define ICH6_REG_SD_BDLPU 0x1c |
| 133 | |
| 134 | /* PCI space */ |
| 135 | #define ICH6_PCIREG_TCSEL 0x44 |
| 136 | |
| 137 | /* |
| 138 | * other constants |
| 139 | */ |
| 140 | |
| 141 | /* max number of SDs */ |
| 142 | #define MAX_ICH6_DEV 8 |
| 143 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
| 144 | #define AZX_MAX_FRAG (PAGE_SIZE / (MAX_ICH6_DEV * 16)) |
| 145 | /* max buffer size - no h/w limit, you can increase as you like */ |
| 146 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) |
| 147 | /* max number of PCM devics per card */ |
| 148 | #define AZX_MAX_PCMS 8 |
| 149 | |
| 150 | /* RIRB int mask: overrun[2], response[0] */ |
| 151 | #define RIRB_INT_RESPONSE 0x01 |
| 152 | #define RIRB_INT_OVERRUN 0x04 |
| 153 | #define RIRB_INT_MASK 0x05 |
| 154 | |
| 155 | /* STATESTS int mask: SD2,SD1,SD0 */ |
| 156 | #define STATESTS_INT_MASK 0x07 |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 157 | #define AZX_MAX_CODECS 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | |
| 159 | /* SD_CTL bits */ |
| 160 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ |
| 161 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ |
| 162 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
| 163 | #define SD_CTL_STREAM_TAG_SHIFT 20 |
| 164 | |
| 165 | /* SD_CTL and SD_STS */ |
| 166 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ |
| 167 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ |
| 168 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ |
| 169 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) |
| 170 | |
| 171 | /* SD_STS */ |
| 172 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ |
| 173 | |
| 174 | /* INTCTL and INTSTS */ |
| 175 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
| 176 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ |
| 177 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ |
| 178 | |
| 179 | /* GCTL reset bit */ |
| 180 | #define ICH6_GCTL_RESET (1<<0) |
| 181 | |
| 182 | /* CORB/RIRB control, read/write pointer */ |
| 183 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ |
| 184 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ |
| 185 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ |
| 186 | /* below are so far hardcoded - should read registers in future */ |
| 187 | #define ICH6_MAX_CORB_ENTRIES 256 |
| 188 | #define ICH6_MAX_RIRB_ENTRIES 256 |
| 189 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 190 | /* position fix mode */ |
| 191 | enum { |
| 192 | POS_FIX_FIFO, |
| 193 | POS_FIX_NONE, |
| 194 | POS_FIX_POSBUF |
| 195 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 197 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
| 198 | #define ATI_SB450_HDAUDIO_PCI_DEVICE_ID 0x437b |
| 199 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
| 200 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 |
| 201 | |
| 202 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | /* |
| 204 | * Use CORB/RIRB for communication from/to codecs. |
| 205 | * This is the way recommended by Intel (see below). |
| 206 | */ |
| 207 | #define USE_CORB_RIRB |
| 208 | |
| 209 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | */ |
| 211 | |
| 212 | typedef struct snd_azx azx_t; |
| 213 | typedef struct snd_azx_rb azx_rb_t; |
| 214 | typedef struct snd_azx_dev azx_dev_t; |
| 215 | |
| 216 | struct snd_azx_dev { |
| 217 | u32 *bdl; /* virtual address of the BDL */ |
| 218 | dma_addr_t bdl_addr; /* physical address of the BDL */ |
| 219 | volatile u32 *posbuf; /* position buffer pointer */ |
| 220 | |
| 221 | unsigned int bufsize; /* size of the play buffer in bytes */ |
| 222 | unsigned int fragsize; /* size of each period in bytes */ |
| 223 | unsigned int frags; /* number for period in the play buffer */ |
| 224 | unsigned int fifo_size; /* FIFO size */ |
| 225 | |
| 226 | void __iomem *sd_addr; /* stream descriptor pointer */ |
| 227 | |
| 228 | u32 sd_int_sta_mask; /* stream int status mask */ |
| 229 | |
| 230 | /* pcm support */ |
| 231 | snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */ |
| 232 | unsigned int format_val; /* format value to be set in the controller and the codec */ |
| 233 | unsigned char stream_tag; /* assigned stream */ |
| 234 | unsigned char index; /* stream index */ |
| 235 | |
| 236 | unsigned int opened: 1; |
| 237 | unsigned int running: 1; |
| 238 | }; |
| 239 | |
| 240 | /* CORB/RIRB */ |
| 241 | struct snd_azx_rb { |
| 242 | u32 *buf; /* CORB/RIRB buffer |
| 243 | * Each CORB entry is 4byte, RIRB is 8byte |
| 244 | */ |
| 245 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ |
| 246 | /* for RIRB */ |
| 247 | unsigned short rp, wp; /* read/write pointers */ |
| 248 | int cmds; /* number of pending requests */ |
| 249 | u32 res; /* last read value */ |
| 250 | }; |
| 251 | |
| 252 | struct snd_azx { |
| 253 | snd_card_t *card; |
| 254 | struct pci_dev *pci; |
| 255 | |
| 256 | /* pci resources */ |
| 257 | unsigned long addr; |
| 258 | void __iomem *remap_addr; |
| 259 | int irq; |
| 260 | |
| 261 | /* locks */ |
| 262 | spinlock_t reg_lock; |
| 263 | struct semaphore open_mutex; |
| 264 | |
| 265 | /* streams */ |
| 266 | azx_dev_t azx_dev[MAX_ICH6_DEV]; |
| 267 | |
| 268 | /* PCM */ |
| 269 | unsigned int pcm_devs; |
| 270 | snd_pcm_t *pcm[AZX_MAX_PCMS]; |
| 271 | |
| 272 | /* HD codec */ |
| 273 | unsigned short codec_mask; |
| 274 | struct hda_bus *bus; |
| 275 | |
| 276 | /* CORB/RIRB */ |
| 277 | azx_rb_t corb; |
| 278 | azx_rb_t rirb; |
| 279 | |
| 280 | /* BDL, CORB/RIRB and position buffers */ |
| 281 | struct snd_dma_buffer bdl; |
| 282 | struct snd_dma_buffer rb; |
| 283 | struct snd_dma_buffer posbuf; |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 284 | |
| 285 | /* flags */ |
| 286 | int position_fix; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | /* |
| 290 | * macros for easy use |
| 291 | */ |
| 292 | #define azx_writel(chip,reg,value) \ |
| 293 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) |
| 294 | #define azx_readl(chip,reg) \ |
| 295 | readl((chip)->remap_addr + ICH6_REG_##reg) |
| 296 | #define azx_writew(chip,reg,value) \ |
| 297 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) |
| 298 | #define azx_readw(chip,reg) \ |
| 299 | readw((chip)->remap_addr + ICH6_REG_##reg) |
| 300 | #define azx_writeb(chip,reg,value) \ |
| 301 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) |
| 302 | #define azx_readb(chip,reg) \ |
| 303 | readb((chip)->remap_addr + ICH6_REG_##reg) |
| 304 | |
| 305 | #define azx_sd_writel(dev,reg,value) \ |
| 306 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) |
| 307 | #define azx_sd_readl(dev,reg) \ |
| 308 | readl((dev)->sd_addr + ICH6_REG_##reg) |
| 309 | #define azx_sd_writew(dev,reg,value) \ |
| 310 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) |
| 311 | #define azx_sd_readw(dev,reg) \ |
| 312 | readw((dev)->sd_addr + ICH6_REG_##reg) |
| 313 | #define azx_sd_writeb(dev,reg,value) \ |
| 314 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) |
| 315 | #define azx_sd_readb(dev,reg) \ |
| 316 | readb((dev)->sd_addr + ICH6_REG_##reg) |
| 317 | |
| 318 | /* for pcm support */ |
| 319 | #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data) |
| 320 | |
| 321 | /* Get the upper 32bit of the given dma_addr_t |
| 322 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit |
| 323 | */ |
| 324 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) |
| 325 | |
| 326 | |
| 327 | /* |
| 328 | * Interface for HD codec |
| 329 | */ |
| 330 | |
| 331 | #ifdef USE_CORB_RIRB |
| 332 | /* |
| 333 | * CORB / RIRB interface |
| 334 | */ |
| 335 | static int azx_alloc_cmd_io(azx_t *chip) |
| 336 | { |
| 337 | int err; |
| 338 | |
| 339 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ |
| 340 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), |
| 341 | PAGE_SIZE, &chip->rb); |
| 342 | if (err < 0) { |
| 343 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); |
| 344 | return err; |
| 345 | } |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | static void azx_init_cmd_io(azx_t *chip) |
| 350 | { |
| 351 | /* CORB set up */ |
| 352 | chip->corb.addr = chip->rb.addr; |
| 353 | chip->corb.buf = (u32 *)chip->rb.area; |
| 354 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); |
| 355 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); |
| 356 | |
| 357 | /* set the corb write pointer to 0 */ |
| 358 | azx_writew(chip, CORBWP, 0); |
| 359 | /* reset the corb hw read pointer */ |
| 360 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); |
| 361 | /* enable corb dma */ |
| 362 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); |
| 363 | |
| 364 | /* RIRB set up */ |
| 365 | chip->rirb.addr = chip->rb.addr + 2048; |
| 366 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); |
| 367 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
| 368 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); |
| 369 | |
| 370 | /* reset the rirb hw write pointer */ |
| 371 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); |
| 372 | /* set N=1, get RIRB response interrupt for new entry */ |
| 373 | azx_writew(chip, RINTCNT, 1); |
| 374 | /* enable rirb dma and response irq */ |
| 375 | #ifdef USE_CORB_RIRB |
| 376 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
| 377 | #else |
| 378 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN); |
| 379 | #endif |
| 380 | chip->rirb.rp = chip->rirb.cmds = 0; |
| 381 | } |
| 382 | |
| 383 | static void azx_free_cmd_io(azx_t *chip) |
| 384 | { |
| 385 | /* disable ringbuffer DMAs */ |
| 386 | azx_writeb(chip, RIRBCTL, 0); |
| 387 | azx_writeb(chip, CORBCTL, 0); |
| 388 | } |
| 389 | |
| 390 | /* send a command */ |
| 391 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, |
| 392 | unsigned int verb, unsigned int para) |
| 393 | { |
| 394 | azx_t *chip = codec->bus->private_data; |
| 395 | unsigned int wp; |
| 396 | u32 val; |
| 397 | |
| 398 | val = (u32)(codec->addr & 0x0f) << 28; |
| 399 | val |= (u32)direct << 27; |
| 400 | val |= (u32)nid << 20; |
| 401 | val |= verb << 8; |
| 402 | val |= para; |
| 403 | |
| 404 | /* add command to corb */ |
| 405 | wp = azx_readb(chip, CORBWP); |
| 406 | wp++; |
| 407 | wp %= ICH6_MAX_CORB_ENTRIES; |
| 408 | |
| 409 | spin_lock_irq(&chip->reg_lock); |
| 410 | chip->rirb.cmds++; |
| 411 | chip->corb.buf[wp] = cpu_to_le32(val); |
| 412 | azx_writel(chip, CORBWP, wp); |
| 413 | spin_unlock_irq(&chip->reg_lock); |
| 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) |
| 419 | |
| 420 | /* retrieve RIRB entry - called from interrupt handler */ |
| 421 | static void azx_update_rirb(azx_t *chip) |
| 422 | { |
| 423 | unsigned int rp, wp; |
| 424 | u32 res, res_ex; |
| 425 | |
| 426 | wp = azx_readb(chip, RIRBWP); |
| 427 | if (wp == chip->rirb.wp) |
| 428 | return; |
| 429 | chip->rirb.wp = wp; |
| 430 | |
| 431 | while (chip->rirb.rp != wp) { |
| 432 | chip->rirb.rp++; |
| 433 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; |
| 434 | |
| 435 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ |
| 436 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); |
| 437 | res = le32_to_cpu(chip->rirb.buf[rp]); |
| 438 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
| 439 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); |
| 440 | else if (chip->rirb.cmds) { |
| 441 | chip->rirb.cmds--; |
| 442 | chip->rirb.res = res; |
| 443 | } |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | /* receive a response */ |
| 448 | static unsigned int azx_get_response(struct hda_codec *codec) |
| 449 | { |
| 450 | azx_t *chip = codec->bus->private_data; |
| 451 | int timeout = 50; |
| 452 | |
| 453 | while (chip->rirb.cmds) { |
| 454 | if (! --timeout) { |
| 455 | snd_printk(KERN_ERR "azx_get_response timeout\n"); |
| 456 | chip->rirb.rp = azx_readb(chip, RIRBWP); |
| 457 | chip->rirb.cmds = 0; |
| 458 | return -1; |
| 459 | } |
| 460 | msleep(1); |
| 461 | } |
| 462 | return chip->rirb.res; /* the last value */ |
| 463 | } |
| 464 | |
| 465 | #else |
| 466 | /* |
| 467 | * Use the single immediate command instead of CORB/RIRB for simplicity |
| 468 | * |
| 469 | * Note: according to Intel, this is not preferred use. The command was |
| 470 | * intended for the BIOS only, and may get confused with unsolicited |
| 471 | * responses. So, we shouldn't use it for normal operation from the |
| 472 | * driver. |
| 473 | * I left the codes, however, for debugging/testing purposes. |
| 474 | */ |
| 475 | |
| 476 | #define azx_alloc_cmd_io(chip) 0 |
| 477 | #define azx_init_cmd_io(chip) |
| 478 | #define azx_free_cmd_io(chip) |
| 479 | |
| 480 | /* send a command */ |
| 481 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, |
| 482 | unsigned int verb, unsigned int para) |
| 483 | { |
| 484 | azx_t *chip = codec->bus->private_data; |
| 485 | u32 val; |
| 486 | int timeout = 50; |
| 487 | |
| 488 | val = (u32)(codec->addr & 0x0f) << 28; |
| 489 | val |= (u32)direct << 27; |
| 490 | val |= (u32)nid << 20; |
| 491 | val |= verb << 8; |
| 492 | val |= para; |
| 493 | |
| 494 | while (timeout--) { |
| 495 | /* check ICB busy bit */ |
| 496 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { |
| 497 | /* Clear IRV valid bit */ |
| 498 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); |
| 499 | azx_writel(chip, IC, val); |
| 500 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); |
| 501 | return 0; |
| 502 | } |
| 503 | udelay(1); |
| 504 | } |
| 505 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); |
| 506 | return -EIO; |
| 507 | } |
| 508 | |
| 509 | /* receive a response */ |
| 510 | static unsigned int azx_get_response(struct hda_codec *codec) |
| 511 | { |
| 512 | azx_t *chip = codec->bus->private_data; |
| 513 | int timeout = 50; |
| 514 | |
| 515 | while (timeout--) { |
| 516 | /* check IRV busy bit */ |
| 517 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) |
| 518 | return azx_readl(chip, IR); |
| 519 | udelay(1); |
| 520 | } |
| 521 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); |
| 522 | return (unsigned int)-1; |
| 523 | } |
| 524 | |
| 525 | #define azx_update_rirb(chip) |
| 526 | |
| 527 | #endif /* USE_CORB_RIRB */ |
| 528 | |
| 529 | /* reset codec link */ |
| 530 | static int azx_reset(azx_t *chip) |
| 531 | { |
| 532 | int count; |
| 533 | |
| 534 | /* reset controller */ |
| 535 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); |
| 536 | |
| 537 | count = 50; |
| 538 | while (azx_readb(chip, GCTL) && --count) |
| 539 | msleep(1); |
| 540 | |
| 541 | /* delay for >= 100us for codec PLL to settle per spec |
| 542 | * Rev 0.9 section 5.5.1 |
| 543 | */ |
| 544 | msleep(1); |
| 545 | |
| 546 | /* Bring controller out of reset */ |
| 547 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); |
| 548 | |
| 549 | count = 50; |
| 550 | while (! azx_readb(chip, GCTL) && --count) |
| 551 | msleep(1); |
| 552 | |
| 553 | /* Brent Chartrand said to wait >= 540us for codecs to intialize */ |
| 554 | msleep(1); |
| 555 | |
| 556 | /* check to see if controller is ready */ |
| 557 | if (! azx_readb(chip, GCTL)) { |
| 558 | snd_printd("azx_reset: controller not ready!\n"); |
| 559 | return -EBUSY; |
| 560 | } |
| 561 | |
| 562 | /* detect codecs */ |
| 563 | if (! chip->codec_mask) { |
| 564 | chip->codec_mask = azx_readw(chip, STATESTS); |
| 565 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); |
| 566 | } |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | |
| 572 | /* |
| 573 | * Lowlevel interface |
| 574 | */ |
| 575 | |
| 576 | /* enable interrupts */ |
| 577 | static void azx_int_enable(azx_t *chip) |
| 578 | { |
| 579 | /* enable controller CIE and GIE */ |
| 580 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | |
| 581 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); |
| 582 | } |
| 583 | |
| 584 | /* disable interrupts */ |
| 585 | static void azx_int_disable(azx_t *chip) |
| 586 | { |
| 587 | int i; |
| 588 | |
| 589 | /* disable interrupts in stream descriptor */ |
| 590 | for (i = 0; i < MAX_ICH6_DEV; i++) { |
| 591 | azx_dev_t *azx_dev = &chip->azx_dev[i]; |
| 592 | azx_sd_writeb(azx_dev, SD_CTL, |
| 593 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); |
| 594 | } |
| 595 | |
| 596 | /* disable SIE for all streams */ |
| 597 | azx_writeb(chip, INTCTL, 0); |
| 598 | |
| 599 | /* disable controller CIE and GIE */ |
| 600 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & |
| 601 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); |
| 602 | } |
| 603 | |
| 604 | /* clear interrupts */ |
| 605 | static void azx_int_clear(azx_t *chip) |
| 606 | { |
| 607 | int i; |
| 608 | |
| 609 | /* clear stream status */ |
| 610 | for (i = 0; i < MAX_ICH6_DEV; i++) { |
| 611 | azx_dev_t *azx_dev = &chip->azx_dev[i]; |
| 612 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
| 613 | } |
| 614 | |
| 615 | /* clear STATESTS */ |
| 616 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); |
| 617 | |
| 618 | /* clear rirb status */ |
| 619 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
| 620 | |
| 621 | /* clear int status */ |
| 622 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); |
| 623 | } |
| 624 | |
| 625 | /* start a stream */ |
| 626 | static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev) |
| 627 | { |
| 628 | /* enable SIE */ |
| 629 | azx_writeb(chip, INTCTL, |
| 630 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); |
| 631 | /* set DMA start and interrupt mask */ |
| 632 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | |
| 633 | SD_CTL_DMA_START | SD_INT_MASK); |
| 634 | } |
| 635 | |
| 636 | /* stop a stream */ |
| 637 | static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev) |
| 638 | { |
| 639 | /* stop DMA */ |
| 640 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & |
| 641 | ~(SD_CTL_DMA_START | SD_INT_MASK)); |
| 642 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ |
| 643 | /* disable SIE */ |
| 644 | azx_writeb(chip, INTCTL, |
| 645 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); |
| 646 | } |
| 647 | |
| 648 | |
| 649 | /* |
| 650 | * initialize the chip |
| 651 | */ |
| 652 | static void azx_init_chip(azx_t *chip) |
| 653 | { |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 654 | unsigned char tcsel_reg, ati_misc_cntl2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 655 | |
| 656 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
| 657 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS |
| 658 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs |
| 659 | */ |
| 660 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg); |
| 661 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8); |
| 662 | |
| 663 | /* reset controller */ |
| 664 | azx_reset(chip); |
| 665 | |
| 666 | /* initialize interrupts */ |
| 667 | azx_int_clear(chip); |
| 668 | azx_int_enable(chip); |
| 669 | |
| 670 | /* initialize the codec command I/O */ |
| 671 | azx_init_cmd_io(chip); |
| 672 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 673 | if (chip->position_fix == POS_FIX_POSBUF) { |
| 674 | /* program the position buffer */ |
| 675 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); |
| 676 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); |
| 677 | } |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 678 | |
| 679 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ |
| 680 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI && |
| 681 | chip->pci->device == ATI_SB450_HDAUDIO_PCI_DEVICE_ID) { |
| 682 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
| 683 | &ati_misc_cntl2); |
| 684 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
| 685 | (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); |
| 686 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | |
| 690 | /* |
| 691 | * interrupt handler |
| 692 | */ |
| 693 | static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs) |
| 694 | { |
| 695 | azx_t *chip = dev_id; |
| 696 | azx_dev_t *azx_dev; |
| 697 | u32 status; |
| 698 | int i; |
| 699 | |
| 700 | spin_lock(&chip->reg_lock); |
| 701 | |
| 702 | status = azx_readl(chip, INTSTS); |
| 703 | if (status == 0) { |
| 704 | spin_unlock(&chip->reg_lock); |
| 705 | return IRQ_NONE; |
| 706 | } |
| 707 | |
| 708 | for (i = 0; i < MAX_ICH6_DEV; i++) { |
| 709 | azx_dev = &chip->azx_dev[i]; |
| 710 | if (status & azx_dev->sd_int_sta_mask) { |
| 711 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
| 712 | if (azx_dev->substream && azx_dev->running) { |
| 713 | spin_unlock(&chip->reg_lock); |
| 714 | snd_pcm_period_elapsed(azx_dev->substream); |
| 715 | spin_lock(&chip->reg_lock); |
| 716 | } |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | /* clear rirb int */ |
| 721 | status = azx_readb(chip, RIRBSTS); |
| 722 | if (status & RIRB_INT_MASK) { |
| 723 | if (status & RIRB_INT_RESPONSE) |
| 724 | azx_update_rirb(chip); |
| 725 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
| 726 | } |
| 727 | |
| 728 | #if 0 |
| 729 | /* clear state status int */ |
| 730 | if (azx_readb(chip, STATESTS) & 0x04) |
| 731 | azx_writeb(chip, STATESTS, 0x04); |
| 732 | #endif |
| 733 | spin_unlock(&chip->reg_lock); |
| 734 | |
| 735 | return IRQ_HANDLED; |
| 736 | } |
| 737 | |
| 738 | |
| 739 | /* |
| 740 | * set up BDL entries |
| 741 | */ |
| 742 | static void azx_setup_periods(azx_dev_t *azx_dev) |
| 743 | { |
| 744 | u32 *bdl = azx_dev->bdl; |
| 745 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; |
| 746 | int idx; |
| 747 | |
| 748 | /* reset BDL address */ |
| 749 | azx_sd_writel(azx_dev, SD_BDLPL, 0); |
| 750 | azx_sd_writel(azx_dev, SD_BDLPU, 0); |
| 751 | |
| 752 | /* program the initial BDL entries */ |
| 753 | for (idx = 0; idx < azx_dev->frags; idx++) { |
| 754 | unsigned int off = idx << 2; /* 4 dword step */ |
| 755 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; |
| 756 | /* program the address field of the BDL entry */ |
| 757 | bdl[off] = cpu_to_le32((u32)addr); |
| 758 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); |
| 759 | |
| 760 | /* program the size field of the BDL entry */ |
| 761 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); |
| 762 | |
| 763 | /* program the IOC to enable interrupt when buffer completes */ |
| 764 | bdl[off+3] = cpu_to_le32(0x01); |
| 765 | } |
| 766 | } |
| 767 | |
| 768 | /* |
| 769 | * set up the SD for streaming |
| 770 | */ |
| 771 | static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev) |
| 772 | { |
| 773 | unsigned char val; |
| 774 | int timeout; |
| 775 | |
| 776 | /* make sure the run bit is zero for SD */ |
| 777 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); |
| 778 | /* reset stream */ |
| 779 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); |
| 780 | udelay(3); |
| 781 | timeout = 300; |
| 782 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && |
| 783 | --timeout) |
| 784 | ; |
| 785 | val &= ~SD_CTL_STREAM_RESET; |
| 786 | azx_sd_writeb(azx_dev, SD_CTL, val); |
| 787 | udelay(3); |
| 788 | |
| 789 | timeout = 300; |
| 790 | /* waiting for hardware to report that the stream is out of reset */ |
| 791 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && |
| 792 | --timeout) |
| 793 | ; |
| 794 | |
| 795 | /* program the stream_tag */ |
| 796 | azx_sd_writel(azx_dev, SD_CTL, |
| 797 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | |
| 798 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); |
| 799 | |
| 800 | /* program the length of samples in cyclic buffer */ |
| 801 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); |
| 802 | |
| 803 | /* program the stream format */ |
| 804 | /* this value needs to be the same as the one programmed */ |
| 805 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); |
| 806 | |
| 807 | /* program the stream LVI (last valid index) of the BDL */ |
| 808 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); |
| 809 | |
| 810 | /* program the BDL address */ |
| 811 | /* lower BDL address */ |
| 812 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); |
| 813 | /* upper BDL address */ |
| 814 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); |
| 815 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 816 | if (chip->position_fix == POS_FIX_POSBUF) { |
| 817 | /* enable the position buffer */ |
| 818 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
| 819 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); |
| 820 | } |
| 821 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | /* set the interrupt enable bits in the descriptor control register */ |
| 823 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); |
| 824 | |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | |
| 829 | /* |
| 830 | * Codec initialization |
| 831 | */ |
| 832 | |
| 833 | static int __devinit azx_codec_create(azx_t *chip, const char *model) |
| 834 | { |
| 835 | struct hda_bus_template bus_temp; |
| 836 | int c, codecs, err; |
| 837 | |
| 838 | memset(&bus_temp, 0, sizeof(bus_temp)); |
| 839 | bus_temp.private_data = chip; |
| 840 | bus_temp.modelname = model; |
| 841 | bus_temp.pci = chip->pci; |
| 842 | bus_temp.ops.command = azx_send_cmd; |
| 843 | bus_temp.ops.get_response = azx_get_response; |
| 844 | |
| 845 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) |
| 846 | return err; |
| 847 | |
| 848 | codecs = 0; |
| 849 | for (c = 0; c < AZX_MAX_CODECS; c++) { |
| 850 | if (chip->codec_mask & (1 << c)) { |
| 851 | err = snd_hda_codec_new(chip->bus, c, NULL); |
| 852 | if (err < 0) |
| 853 | continue; |
| 854 | codecs++; |
| 855 | } |
| 856 | } |
| 857 | if (! codecs) { |
| 858 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); |
| 859 | return -ENXIO; |
| 860 | } |
| 861 | |
| 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | |
| 866 | /* |
| 867 | * PCM support |
| 868 | */ |
| 869 | |
| 870 | /* assign a stream for the PCM */ |
| 871 | static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream) |
| 872 | { |
| 873 | int dev, i; |
| 874 | dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0; |
| 875 | for (i = 0; i < 4; i++, dev++) |
| 876 | if (! chip->azx_dev[dev].opened) { |
| 877 | chip->azx_dev[dev].opened = 1; |
| 878 | return &chip->azx_dev[dev]; |
| 879 | } |
| 880 | return NULL; |
| 881 | } |
| 882 | |
| 883 | /* release the assigned stream */ |
| 884 | static inline void azx_release_device(azx_dev_t *azx_dev) |
| 885 | { |
| 886 | azx_dev->opened = 0; |
| 887 | } |
| 888 | |
| 889 | static snd_pcm_hardware_t azx_pcm_hw = { |
| 890 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | |
| 891 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
| 892 | SNDRV_PCM_INFO_MMAP_VALID | |
| 893 | SNDRV_PCM_INFO_PAUSE | |
| 894 | SNDRV_PCM_INFO_RESUME), |
| 895 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
| 896 | .rates = SNDRV_PCM_RATE_48000, |
| 897 | .rate_min = 48000, |
| 898 | .rate_max = 48000, |
| 899 | .channels_min = 2, |
| 900 | .channels_max = 2, |
| 901 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, |
| 902 | .period_bytes_min = 128, |
| 903 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, |
| 904 | .periods_min = 2, |
| 905 | .periods_max = AZX_MAX_FRAG, |
| 906 | .fifo_size = 0, |
| 907 | }; |
| 908 | |
| 909 | struct azx_pcm { |
| 910 | azx_t *chip; |
| 911 | struct hda_codec *codec; |
| 912 | struct hda_pcm_stream *hinfo[2]; |
| 913 | }; |
| 914 | |
| 915 | static int azx_pcm_open(snd_pcm_substream_t *substream) |
| 916 | { |
| 917 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 918 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
| 919 | azx_t *chip = apcm->chip; |
| 920 | azx_dev_t *azx_dev; |
| 921 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 922 | unsigned long flags; |
| 923 | int err; |
| 924 | |
| 925 | down(&chip->open_mutex); |
| 926 | azx_dev = azx_assign_device(chip, substream->stream); |
| 927 | if (azx_dev == NULL) { |
| 928 | up(&chip->open_mutex); |
| 929 | return -EBUSY; |
| 930 | } |
| 931 | runtime->hw = azx_pcm_hw; |
| 932 | runtime->hw.channels_min = hinfo->channels_min; |
| 933 | runtime->hw.channels_max = hinfo->channels_max; |
| 934 | runtime->hw.formats = hinfo->formats; |
| 935 | runtime->hw.rates = hinfo->rates; |
| 936 | snd_pcm_limit_hw_rates(runtime); |
| 937 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); |
| 938 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { |
| 939 | azx_release_device(azx_dev); |
| 940 | up(&chip->open_mutex); |
| 941 | return err; |
| 942 | } |
| 943 | spin_lock_irqsave(&chip->reg_lock, flags); |
| 944 | azx_dev->substream = substream; |
| 945 | azx_dev->running = 0; |
| 946 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
| 947 | |
| 948 | runtime->private_data = azx_dev; |
| 949 | up(&chip->open_mutex); |
| 950 | return 0; |
| 951 | } |
| 952 | |
| 953 | static int azx_pcm_close(snd_pcm_substream_t *substream) |
| 954 | { |
| 955 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 956 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
| 957 | azx_t *chip = apcm->chip; |
| 958 | azx_dev_t *azx_dev = get_azx_dev(substream); |
| 959 | unsigned long flags; |
| 960 | |
| 961 | down(&chip->open_mutex); |
| 962 | spin_lock_irqsave(&chip->reg_lock, flags); |
| 963 | azx_dev->substream = NULL; |
| 964 | azx_dev->running = 0; |
| 965 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
| 966 | azx_release_device(azx_dev); |
| 967 | hinfo->ops.close(hinfo, apcm->codec, substream); |
| 968 | up(&chip->open_mutex); |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params) |
| 973 | { |
| 974 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); |
| 975 | } |
| 976 | |
| 977 | static int azx_pcm_hw_free(snd_pcm_substream_t *substream) |
| 978 | { |
| 979 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 980 | azx_dev_t *azx_dev = get_azx_dev(substream); |
| 981 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
| 982 | |
| 983 | /* reset BDL address */ |
| 984 | azx_sd_writel(azx_dev, SD_BDLPL, 0); |
| 985 | azx_sd_writel(azx_dev, SD_BDLPU, 0); |
| 986 | azx_sd_writel(azx_dev, SD_CTL, 0); |
| 987 | |
| 988 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); |
| 989 | |
| 990 | return snd_pcm_lib_free_pages(substream); |
| 991 | } |
| 992 | |
| 993 | static int azx_pcm_prepare(snd_pcm_substream_t *substream) |
| 994 | { |
| 995 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 996 | azx_t *chip = apcm->chip; |
| 997 | azx_dev_t *azx_dev = get_azx_dev(substream); |
| 998 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
| 999 | snd_pcm_runtime_t *runtime = substream->runtime; |
| 1000 | |
| 1001 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); |
| 1002 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); |
| 1003 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; |
| 1004 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, |
| 1005 | runtime->channels, |
| 1006 | runtime->format, |
| 1007 | hinfo->maxbps); |
| 1008 | if (! azx_dev->format_val) { |
| 1009 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", |
| 1010 | runtime->rate, runtime->channels, runtime->format); |
| 1011 | return -EINVAL; |
| 1012 | } |
| 1013 | |
| 1014 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", |
| 1015 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); |
| 1016 | azx_setup_periods(azx_dev); |
| 1017 | azx_setup_controller(chip, azx_dev); |
| 1018 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 1019 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; |
| 1020 | else |
| 1021 | azx_dev->fifo_size = 0; |
| 1022 | |
| 1023 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, |
| 1024 | azx_dev->format_val, substream); |
| 1025 | } |
| 1026 | |
| 1027 | static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd) |
| 1028 | { |
| 1029 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 1030 | azx_dev_t *azx_dev = get_azx_dev(substream); |
| 1031 | azx_t *chip = apcm->chip; |
| 1032 | int err = 0; |
| 1033 | |
| 1034 | spin_lock(&chip->reg_lock); |
| 1035 | switch (cmd) { |
| 1036 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 1037 | case SNDRV_PCM_TRIGGER_RESUME: |
| 1038 | case SNDRV_PCM_TRIGGER_START: |
| 1039 | azx_stream_start(chip, azx_dev); |
| 1040 | azx_dev->running = 1; |
| 1041 | break; |
| 1042 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 1043 | case SNDRV_PCM_TRIGGER_STOP: |
| 1044 | azx_stream_stop(chip, azx_dev); |
| 1045 | azx_dev->running = 0; |
| 1046 | break; |
| 1047 | default: |
| 1048 | err = -EINVAL; |
| 1049 | } |
| 1050 | spin_unlock(&chip->reg_lock); |
| 1051 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || |
| 1052 | cmd == SNDRV_PCM_TRIGGER_STOP) { |
| 1053 | int timeout = 5000; |
| 1054 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) |
| 1055 | ; |
| 1056 | } |
| 1057 | return err; |
| 1058 | } |
| 1059 | |
| 1060 | static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream) |
| 1061 | { |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1062 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
| 1063 | azx_t *chip = apcm->chip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | azx_dev_t *azx_dev = get_azx_dev(substream); |
| 1065 | unsigned int pos; |
| 1066 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1067 | if (chip->position_fix == POS_FIX_POSBUF) { |
| 1068 | /* use the position buffer */ |
| 1069 | pos = *azx_dev->posbuf; |
| 1070 | } else { |
| 1071 | /* read LPIB */ |
| 1072 | pos = azx_sd_readl(azx_dev, SD_LPIB); |
| 1073 | if (chip->position_fix == POS_FIX_FIFO) |
| 1074 | pos += azx_dev->fifo_size; |
| 1075 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | if (pos >= azx_dev->bufsize) |
| 1077 | pos = 0; |
| 1078 | return bytes_to_frames(substream->runtime, pos); |
| 1079 | } |
| 1080 | |
| 1081 | static snd_pcm_ops_t azx_pcm_ops = { |
| 1082 | .open = azx_pcm_open, |
| 1083 | .close = azx_pcm_close, |
| 1084 | .ioctl = snd_pcm_lib_ioctl, |
| 1085 | .hw_params = azx_pcm_hw_params, |
| 1086 | .hw_free = azx_pcm_hw_free, |
| 1087 | .prepare = azx_pcm_prepare, |
| 1088 | .trigger = azx_pcm_trigger, |
| 1089 | .pointer = azx_pcm_pointer, |
| 1090 | }; |
| 1091 | |
| 1092 | static void azx_pcm_free(snd_pcm_t *pcm) |
| 1093 | { |
| 1094 | kfree(pcm->private_data); |
| 1095 | } |
| 1096 | |
| 1097 | static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec, |
| 1098 | struct hda_pcm *cpcm, int pcm_dev) |
| 1099 | { |
| 1100 | int err; |
| 1101 | snd_pcm_t *pcm; |
| 1102 | struct azx_pcm *apcm; |
| 1103 | |
| 1104 | snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL); |
| 1105 | snd_assert(cpcm->name, return -EINVAL); |
| 1106 | |
| 1107 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, |
| 1108 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, |
| 1109 | &pcm); |
| 1110 | if (err < 0) |
| 1111 | return err; |
| 1112 | strcpy(pcm->name, cpcm->name); |
| 1113 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); |
| 1114 | if (apcm == NULL) |
| 1115 | return -ENOMEM; |
| 1116 | apcm->chip = chip; |
| 1117 | apcm->codec = codec; |
| 1118 | apcm->hinfo[0] = &cpcm->stream[0]; |
| 1119 | apcm->hinfo[1] = &cpcm->stream[1]; |
| 1120 | pcm->private_data = apcm; |
| 1121 | pcm->private_free = azx_pcm_free; |
| 1122 | if (cpcm->stream[0].substreams) |
| 1123 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); |
| 1124 | if (cpcm->stream[1].substreams) |
| 1125 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); |
| 1126 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
| 1127 | snd_dma_pci_data(chip->pci), |
| 1128 | 1024 * 64, 1024 * 128); |
| 1129 | chip->pcm[pcm_dev] = pcm; |
| 1130 | |
| 1131 | return 0; |
| 1132 | } |
| 1133 | |
| 1134 | static int __devinit azx_pcm_create(azx_t *chip) |
| 1135 | { |
| 1136 | struct list_head *p; |
| 1137 | struct hda_codec *codec; |
| 1138 | int c, err; |
| 1139 | int pcm_dev; |
| 1140 | |
| 1141 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) |
| 1142 | return err; |
| 1143 | |
| 1144 | pcm_dev = 0; |
| 1145 | list_for_each(p, &chip->bus->codec_list) { |
| 1146 | codec = list_entry(p, struct hda_codec, list); |
| 1147 | for (c = 0; c < codec->num_pcms; c++) { |
| 1148 | if (pcm_dev >= AZX_MAX_PCMS) { |
| 1149 | snd_printk(KERN_ERR SFX "Too many PCMs\n"); |
| 1150 | return -EINVAL; |
| 1151 | } |
| 1152 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); |
| 1153 | if (err < 0) |
| 1154 | return err; |
| 1155 | pcm_dev++; |
| 1156 | } |
| 1157 | } |
| 1158 | return 0; |
| 1159 | } |
| 1160 | |
| 1161 | /* |
| 1162 | * mixer creation - all stuff is implemented in hda module |
| 1163 | */ |
| 1164 | static int __devinit azx_mixer_create(azx_t *chip) |
| 1165 | { |
| 1166 | return snd_hda_build_controls(chip->bus); |
| 1167 | } |
| 1168 | |
| 1169 | |
| 1170 | /* |
| 1171 | * initialize SD streams |
| 1172 | */ |
| 1173 | static int __devinit azx_init_stream(azx_t *chip) |
| 1174 | { |
| 1175 | int i; |
| 1176 | |
| 1177 | /* initialize each stream (aka device) |
| 1178 | * assign the starting bdl address to each stream (device) and initialize |
| 1179 | */ |
| 1180 | for (i = 0; i < MAX_ICH6_DEV; i++) { |
| 1181 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); |
| 1182 | azx_dev_t *azx_dev = &chip->azx_dev[i]; |
| 1183 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); |
| 1184 | azx_dev->bdl_addr = chip->bdl.addr + off; |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1185 | if (chip->position_fix == POS_FIX_POSBUF) |
| 1186 | azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1187 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
| 1188 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); |
| 1189 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ |
| 1190 | azx_dev->sd_int_sta_mask = 1 << i; |
| 1191 | /* stream tag: must be non-zero and unique */ |
| 1192 | azx_dev->index = i; |
| 1193 | azx_dev->stream_tag = i + 1; |
| 1194 | } |
| 1195 | |
| 1196 | return 0; |
| 1197 | } |
| 1198 | |
| 1199 | |
| 1200 | #ifdef CONFIG_PM |
| 1201 | /* |
| 1202 | * power management |
| 1203 | */ |
| 1204 | static int azx_suspend(snd_card_t *card, pm_message_t state) |
| 1205 | { |
| 1206 | azx_t *chip = card->pm_private_data; |
| 1207 | int i; |
| 1208 | |
| 1209 | for (i = 0; i < chip->pcm_devs; i++) |
| 1210 | if (chip->pcm[i]) |
| 1211 | snd_pcm_suspend_all(chip->pcm[i]); |
| 1212 | snd_hda_suspend(chip->bus, state); |
| 1213 | azx_free_cmd_io(chip); |
| 1214 | pci_disable_device(chip->pci); |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | static int azx_resume(snd_card_t *card) |
| 1219 | { |
| 1220 | azx_t *chip = card->pm_private_data; |
| 1221 | |
| 1222 | pci_enable_device(chip->pci); |
| 1223 | pci_set_master(chip->pci); |
| 1224 | azx_init_chip(chip); |
| 1225 | snd_hda_resume(chip->bus); |
| 1226 | return 0; |
| 1227 | } |
| 1228 | #endif /* CONFIG_PM */ |
| 1229 | |
| 1230 | |
| 1231 | /* |
| 1232 | * destructor |
| 1233 | */ |
| 1234 | static int azx_free(azx_t *chip) |
| 1235 | { |
| 1236 | if (chip->remap_addr) { |
| 1237 | int i; |
| 1238 | |
| 1239 | for (i = 0; i < MAX_ICH6_DEV; i++) |
| 1240 | azx_stream_stop(chip, &chip->azx_dev[i]); |
| 1241 | |
| 1242 | /* disable interrupts */ |
| 1243 | azx_int_disable(chip); |
| 1244 | azx_int_clear(chip); |
| 1245 | |
| 1246 | /* disable CORB/RIRB */ |
| 1247 | azx_free_cmd_io(chip); |
| 1248 | |
| 1249 | /* disable position buffer */ |
| 1250 | azx_writel(chip, DPLBASE, 0); |
| 1251 | azx_writel(chip, DPUBASE, 0); |
| 1252 | |
| 1253 | /* wait a little for interrupts to finish */ |
| 1254 | msleep(1); |
| 1255 | |
| 1256 | iounmap(chip->remap_addr); |
| 1257 | } |
| 1258 | |
| 1259 | if (chip->irq >= 0) |
| 1260 | free_irq(chip->irq, (void*)chip); |
| 1261 | |
| 1262 | if (chip->bdl.area) |
| 1263 | snd_dma_free_pages(&chip->bdl); |
| 1264 | if (chip->rb.area) |
| 1265 | snd_dma_free_pages(&chip->rb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | if (chip->posbuf.area) |
| 1267 | snd_dma_free_pages(&chip->posbuf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | pci_release_regions(chip->pci); |
| 1269 | pci_disable_device(chip->pci); |
| 1270 | kfree(chip); |
| 1271 | |
| 1272 | return 0; |
| 1273 | } |
| 1274 | |
| 1275 | static int azx_dev_free(snd_device_t *device) |
| 1276 | { |
| 1277 | return azx_free(device->device_data); |
| 1278 | } |
| 1279 | |
| 1280 | /* |
| 1281 | * constructor |
| 1282 | */ |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1283 | static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci, |
| 1284 | int posfix, azx_t **rchip) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1285 | { |
| 1286 | azx_t *chip; |
| 1287 | int err = 0; |
| 1288 | static snd_device_ops_t ops = { |
| 1289 | .dev_free = azx_dev_free, |
| 1290 | }; |
| 1291 | |
| 1292 | *rchip = NULL; |
| 1293 | |
| 1294 | if ((err = pci_enable_device(pci)) < 0) |
| 1295 | return err; |
| 1296 | |
| 1297 | chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); |
| 1298 | |
| 1299 | if (NULL == chip) { |
| 1300 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); |
| 1301 | pci_disable_device(pci); |
| 1302 | return -ENOMEM; |
| 1303 | } |
| 1304 | |
| 1305 | spin_lock_init(&chip->reg_lock); |
| 1306 | init_MUTEX(&chip->open_mutex); |
| 1307 | chip->card = card; |
| 1308 | chip->pci = pci; |
| 1309 | chip->irq = -1; |
| 1310 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1311 | chip->position_fix = posfix; |
| 1312 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1313 | if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) { |
| 1314 | kfree(chip); |
| 1315 | pci_disable_device(pci); |
| 1316 | return err; |
| 1317 | } |
| 1318 | |
| 1319 | chip->addr = pci_resource_start(pci,0); |
| 1320 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); |
| 1321 | if (chip->remap_addr == NULL) { |
| 1322 | snd_printk(KERN_ERR SFX "ioremap error\n"); |
| 1323 | err = -ENXIO; |
| 1324 | goto errout; |
| 1325 | } |
| 1326 | |
| 1327 | if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ, |
| 1328 | "HDA Intel", (void*)chip)) { |
| 1329 | snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq); |
| 1330 | err = -EBUSY; |
| 1331 | goto errout; |
| 1332 | } |
| 1333 | chip->irq = pci->irq; |
| 1334 | |
| 1335 | pci_set_master(pci); |
| 1336 | synchronize_irq(chip->irq); |
| 1337 | |
| 1338 | /* allocate memory for the BDL for each stream */ |
| 1339 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), |
| 1340 | PAGE_SIZE, &chip->bdl)) < 0) { |
| 1341 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); |
| 1342 | goto errout; |
| 1343 | } |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1344 | if (chip->position_fix == POS_FIX_POSBUF) { |
| 1345 | /* allocate memory for the position buffer */ |
| 1346 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), |
| 1347 | MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) { |
| 1348 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); |
| 1349 | goto errout; |
| 1350 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1351 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | /* allocate CORB/RIRB */ |
| 1353 | if ((err = azx_alloc_cmd_io(chip)) < 0) |
| 1354 | goto errout; |
| 1355 | |
| 1356 | /* initialize streams */ |
| 1357 | azx_init_stream(chip); |
| 1358 | |
| 1359 | /* initialize chip */ |
| 1360 | azx_init_chip(chip); |
| 1361 | |
| 1362 | /* codec detection */ |
| 1363 | if (! chip->codec_mask) { |
| 1364 | snd_printk(KERN_ERR SFX "no codecs found!\n"); |
| 1365 | err = -ENODEV; |
| 1366 | goto errout; |
| 1367 | } |
| 1368 | |
| 1369 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { |
| 1370 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); |
| 1371 | goto errout; |
| 1372 | } |
| 1373 | |
| 1374 | *rchip = chip; |
| 1375 | return 0; |
| 1376 | |
| 1377 | errout: |
| 1378 | azx_free(chip); |
| 1379 | return err; |
| 1380 | } |
| 1381 | |
| 1382 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
| 1383 | { |
| 1384 | static int dev; |
| 1385 | snd_card_t *card; |
| 1386 | azx_t *chip; |
| 1387 | int err = 0; |
| 1388 | |
| 1389 | if (dev >= SNDRV_CARDS) |
| 1390 | return -ENODEV; |
| 1391 | if (! enable[dev]) { |
| 1392 | dev++; |
| 1393 | return -ENOENT; |
| 1394 | } |
| 1395 | |
| 1396 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); |
| 1397 | if (NULL == card) { |
| 1398 | snd_printk(KERN_ERR SFX "Error creating card!\n"); |
| 1399 | return -ENOMEM; |
| 1400 | } |
| 1401 | |
Takashi Iwai | c74db86 | 2005-05-12 14:26:27 +0200 | [diff] [blame] | 1402 | if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1403 | snd_card_free(card); |
| 1404 | return err; |
| 1405 | } |
| 1406 | |
| 1407 | strcpy(card->driver, "HDA-Intel"); |
| 1408 | strcpy(card->shortname, "HDA Intel"); |
| 1409 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); |
| 1410 | |
| 1411 | /* create codec instances */ |
| 1412 | if ((err = azx_codec_create(chip, model[dev])) < 0) { |
| 1413 | snd_card_free(card); |
| 1414 | return err; |
| 1415 | } |
| 1416 | |
| 1417 | /* create PCM streams */ |
| 1418 | if ((err = azx_pcm_create(chip)) < 0) { |
| 1419 | snd_card_free(card); |
| 1420 | return err; |
| 1421 | } |
| 1422 | |
| 1423 | /* create mixer controls */ |
| 1424 | if ((err = azx_mixer_create(chip)) < 0) { |
| 1425 | snd_card_free(card); |
| 1426 | return err; |
| 1427 | } |
| 1428 | |
| 1429 | snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip); |
| 1430 | snd_card_set_dev(card, &pci->dev); |
| 1431 | |
| 1432 | if ((err = snd_card_register(card)) < 0) { |
| 1433 | snd_card_free(card); |
| 1434 | return err; |
| 1435 | } |
| 1436 | |
| 1437 | pci_set_drvdata(pci, card); |
| 1438 | dev++; |
| 1439 | |
| 1440 | return err; |
| 1441 | } |
| 1442 | |
| 1443 | static void __devexit azx_remove(struct pci_dev *pci) |
| 1444 | { |
| 1445 | snd_card_free(pci_get_drvdata(pci)); |
| 1446 | pci_set_drvdata(pci, NULL); |
| 1447 | } |
| 1448 | |
| 1449 | /* PCI IDs */ |
| 1450 | static struct pci_device_id azx_ids[] = { |
| 1451 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */ |
| 1452 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */ |
Jason Gaston | 2f1b381 | 2005-05-01 08:58:50 -0700 | [diff] [blame] | 1453 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */ |
Frederick Li | f5d40b3 | 2005-05-12 14:55:20 +0200 | [diff] [blame^] | 1454 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1455 | { 0, } |
| 1456 | }; |
| 1457 | MODULE_DEVICE_TABLE(pci, azx_ids); |
| 1458 | |
| 1459 | /* pci_driver definition */ |
| 1460 | static struct pci_driver driver = { |
| 1461 | .name = "HDA Intel", |
| 1462 | .id_table = azx_ids, |
| 1463 | .probe = azx_probe, |
| 1464 | .remove = __devexit_p(azx_remove), |
| 1465 | SND_PCI_PM_CALLBACKS |
| 1466 | }; |
| 1467 | |
| 1468 | static int __init alsa_card_azx_init(void) |
| 1469 | { |
Takashi Iwai | 01d25d4 | 2005-04-11 16:58:24 +0200 | [diff] [blame] | 1470 | return pci_register_driver(&driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1471 | } |
| 1472 | |
| 1473 | static void __exit alsa_card_azx_exit(void) |
| 1474 | { |
| 1475 | pci_unregister_driver(&driver); |
| 1476 | } |
| 1477 | |
| 1478 | module_init(alsa_card_azx_init) |
| 1479 | module_exit(alsa_card_azx_exit) |