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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080018#include <linux/string.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090020#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -070022unsigned int pci_pm_d3_delay = 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Atsushi Nemoto4516a612007-02-05 16:36:06 -080024#define DEFAULT_CARDBUS_IO_SIZE (256)
25#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
26/* pci=cbmemsize=nnM,cbiosize=nn can override this */
27unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
28unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030/**
31 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
32 * @bus: pointer to PCI bus structure to search
33 *
34 * Given a PCI bus, returns the highest PCI bus number present in the set
35 * including the given PCI bus and its list of child PCI buses.
36 */
37unsigned char __devinit
38pci_bus_max_busnr(struct pci_bus* bus)
39{
40 struct list_head *tmp;
41 unsigned char max, n;
42
Kristen Accardib82db5c2006-01-17 16:56:56 -080043 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 list_for_each(tmp, &bus->children) {
45 n = pci_bus_max_busnr(pci_bus_b(tmp));
46 if(n > max)
47 max = n;
48 }
49 return max;
50}
Kristen Accardib82db5c2006-01-17 16:56:56 -080051EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Kristen Accardib82db5c2006-01-17 16:56:56 -080053#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070054/**
55 * pci_max_busnr - returns maximum PCI bus number
56 *
57 * Returns the highest PCI bus number present in the system global list of
58 * PCI buses.
59 */
60unsigned char __devinit
61pci_max_busnr(void)
62{
63 struct pci_bus *bus = NULL;
64 unsigned char max, n;
65
66 max = 0;
67 while ((bus = pci_find_next_bus(bus)) != NULL) {
68 n = pci_bus_max_busnr(bus);
69 if(n > max)
70 max = n;
71 }
72 return max;
73}
74
Adrian Bunk54c762f2005-12-22 01:08:52 +010075#endif /* 0 */
76
Michael Ellerman687d5fe2006-11-22 18:26:18 +110077#define PCI_FIND_CAP_TTL 48
78
79static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
80 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -070081{
82 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -070083
Michael Ellerman687d5fe2006-11-22 18:26:18 +110084 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -070085 pci_bus_read_config_byte(bus, devfn, pos, &pos);
86 if (pos < 0x40)
87 break;
88 pos &= ~3;
89 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
90 &id);
91 if (id == 0xff)
92 break;
93 if (id == cap)
94 return pos;
95 pos += PCI_CAP_LIST_NEXT;
96 }
97 return 0;
98}
99
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100100static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
101 u8 pos, int cap)
102{
103 int ttl = PCI_FIND_CAP_TTL;
104
105 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
106}
107
Roland Dreier24a4e372005-10-28 17:35:34 -0700108int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
109{
110 return __pci_find_next_cap(dev->bus, dev->devfn,
111 pos + PCI_CAP_LIST_NEXT, cap);
112}
113EXPORT_SYMBOL_GPL(pci_find_next_capability);
114
Michael Ellermand3bac112006-11-22 18:26:16 +1100115static int __pci_bus_find_cap_start(struct pci_bus *bus,
116 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117{
118 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
121 if (!(status & PCI_STATUS_CAP_LIST))
122 return 0;
123
124 switch (hdr_type) {
125 case PCI_HEADER_TYPE_NORMAL:
126 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100127 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100129 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 default:
131 return 0;
132 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100133
134 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135}
136
137/**
138 * pci_find_capability - query for devices' capabilities
139 * @dev: PCI device to query
140 * @cap: capability code
141 *
142 * Tell if a device supports a given PCI capability.
143 * Returns the address of the requested capability structure within the
144 * device's PCI configuration space or 0 in case the device does not
145 * support it. Possible values for @cap:
146 *
147 * %PCI_CAP_ID_PM Power Management
148 * %PCI_CAP_ID_AGP Accelerated Graphics Port
149 * %PCI_CAP_ID_VPD Vital Product Data
150 * %PCI_CAP_ID_SLOTID Slot Identification
151 * %PCI_CAP_ID_MSI Message Signalled Interrupts
152 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
153 * %PCI_CAP_ID_PCIX PCI-X
154 * %PCI_CAP_ID_EXP PCI Express
155 */
156int pci_find_capability(struct pci_dev *dev, int cap)
157{
Michael Ellermand3bac112006-11-22 18:26:16 +1100158 int pos;
159
160 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
161 if (pos)
162 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
163
164 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165}
166
167/**
168 * pci_bus_find_capability - query for devices' capabilities
169 * @bus: the PCI bus to query
170 * @devfn: PCI device to query
171 * @cap: capability code
172 *
173 * Like pci_find_capability() but works for pci devices that do not have a
174 * pci_dev structure set up yet.
175 *
176 * Returns the address of the requested capability structure within the
177 * device's PCI configuration space or 0 in case the device does not
178 * support it.
179 */
180int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
181{
Michael Ellermand3bac112006-11-22 18:26:16 +1100182 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 u8 hdr_type;
184
185 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
186
Michael Ellermand3bac112006-11-22 18:26:16 +1100187 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
188 if (pos)
189 pos = __pci_find_next_cap(bus, devfn, pos, cap);
190
191 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192}
193
194/**
195 * pci_find_ext_capability - Find an extended capability
196 * @dev: PCI device to query
197 * @cap: capability code
198 *
199 * Returns the address of the requested extended capability structure
200 * within the device's PCI configuration space or 0 if the device does
201 * not support it. Possible values for @cap:
202 *
203 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
204 * %PCI_EXT_CAP_ID_VC Virtual Channel
205 * %PCI_EXT_CAP_ID_DSN Device Serial Number
206 * %PCI_EXT_CAP_ID_PWR Power Budgeting
207 */
208int pci_find_ext_capability(struct pci_dev *dev, int cap)
209{
210 u32 header;
211 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
212 int pos = 0x100;
213
214 if (dev->cfg_size <= 256)
215 return 0;
216
217 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
218 return 0;
219
220 /*
221 * If we have no capabilities, this is indicated by cap ID,
222 * cap version and next pointer all being 0.
223 */
224 if (header == 0)
225 return 0;
226
227 while (ttl-- > 0) {
228 if (PCI_EXT_CAP_ID(header) == cap)
229 return pos;
230
231 pos = PCI_EXT_CAP_NEXT(header);
232 if (pos < 0x100)
233 break;
234
235 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
236 break;
237 }
238
239 return 0;
240}
Brice Goglin3a720d72006-05-23 06:10:01 -0400241EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100243static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
244{
245 int rc, ttl = PCI_FIND_CAP_TTL;
246 u8 cap, mask;
247
248 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
249 mask = HT_3BIT_CAP_MASK;
250 else
251 mask = HT_5BIT_CAP_MASK;
252
253 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
254 PCI_CAP_ID_HT, &ttl);
255 while (pos) {
256 rc = pci_read_config_byte(dev, pos + 3, &cap);
257 if (rc != PCIBIOS_SUCCESSFUL)
258 return 0;
259
260 if ((cap & mask) == ht_cap)
261 return pos;
262
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800263 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
264 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100265 PCI_CAP_ID_HT, &ttl);
266 }
267
268 return 0;
269}
270/**
271 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
272 * @dev: PCI device to query
273 * @pos: Position from which to continue searching
274 * @ht_cap: Hypertransport capability code
275 *
276 * To be used in conjunction with pci_find_ht_capability() to search for
277 * all capabilities matching @ht_cap. @pos should always be a value returned
278 * from pci_find_ht_capability().
279 *
280 * NB. To be 100% safe against broken PCI devices, the caller should take
281 * steps to avoid an infinite loop.
282 */
283int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
284{
285 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
286}
287EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
288
289/**
290 * pci_find_ht_capability - query a device's Hypertransport capabilities
291 * @dev: PCI device to query
292 * @ht_cap: Hypertransport capability code
293 *
294 * Tell if a device supports a given Hypertransport capability.
295 * Returns an address within the device's PCI configuration space
296 * or 0 in case the device does not support the request capability.
297 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
298 * which has a Hypertransport capability matching @ht_cap.
299 */
300int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
301{
302 int pos;
303
304 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
305 if (pos)
306 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
307
308 return pos;
309}
310EXPORT_SYMBOL_GPL(pci_find_ht_capability);
311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312/**
313 * pci_find_parent_resource - return resource region of parent bus of given region
314 * @dev: PCI device structure contains resources to be searched
315 * @res: child resource record for which parent is sought
316 *
317 * For given resource region of given device, return the resource
318 * region of parent bus the given region is contained in or where
319 * it should be allocated from.
320 */
321struct resource *
322pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
323{
324 const struct pci_bus *bus = dev->bus;
325 int i;
326 struct resource *best = NULL;
327
328 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
329 struct resource *r = bus->resource[i];
330 if (!r)
331 continue;
332 if (res->start && !(res->start >= r->start && res->end <= r->end))
333 continue; /* Not contained */
334 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
335 continue; /* Wrong type */
336 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
337 return r; /* Exact match */
338 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
339 best = r; /* Approximating prefetchable by non-prefetchable */
340 }
341 return best;
342}
343
344/**
John W. Linville064b53db2005-07-27 10:19:44 -0400345 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
346 * @dev: PCI device to have its BARs restored
347 *
348 * Restore the BAR values for a given device, so as to make it
349 * accessible by its driver.
350 */
351void
352pci_restore_bars(struct pci_dev *dev)
353{
354 int i, numres;
355
356 switch (dev->hdr_type) {
357 case PCI_HEADER_TYPE_NORMAL:
358 numres = 6;
359 break;
360 case PCI_HEADER_TYPE_BRIDGE:
361 numres = 2;
362 break;
363 case PCI_HEADER_TYPE_CARDBUS:
364 numres = 1;
365 break;
366 default:
367 /* Should never get here, but just in case... */
368 return;
369 }
370
371 for (i = 0; i < numres; i ++)
372 pci_update_resource(dev, &dev->resource[i], i);
373}
374
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700375int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
376
John W. Linville064b53db2005-07-27 10:19:44 -0400377/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 * pci_set_power_state - Set the power state of a PCI device
379 * @dev: PCI device to be suspended
380 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
381 *
382 * Transition a device to a new power state, using the Power Management
383 * Capabilities in the device's config space.
384 *
385 * RETURN VALUE:
386 * -EINVAL if trying to enter a lower state than we're already in.
387 * 0 if we're already in the requested state.
388 * -EIO if device does not support PCI PM.
389 * 0 if we can successfully change the power state.
390 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391int
392pci_set_power_state(struct pci_dev *dev, pci_power_t state)
393{
John W. Linville064b53db2005-07-27 10:19:44 -0400394 int pm, need_restore = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 u16 pmcsr, pmc;
396
397 /* bound the state we're entering */
398 if (state > PCI_D3hot)
399 state = PCI_D3hot;
400
Pavel Macheke36c4552007-01-16 12:17:13 +0100401 /*
402 * If the device or the parent bridge can't support PCI PM, ignore
403 * the request if we're doing anything besides putting it into D0
404 * (which would only happen on boot).
405 */
406 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
407 return 0;
408
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 /* Validate current state:
410 * Can enter D0 from any state, but if we can only go deeper
411 * to sleep if we're already in a low power state
412 */
Andrew Morton02669492006-03-23 01:38:34 -0800413 if (state != PCI_D0 && dev->current_state > state) {
414 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
415 __FUNCTION__, pci_name(dev), state, dev->current_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 return -EINVAL;
Andrew Morton02669492006-03-23 01:38:34 -0800417 } else if (dev->current_state == state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 return 0; /* we're already there */
419
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700420
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 /* find PCI PM capability in list */
422 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
423
424 /* abort if the device doesn't support PM capabilities */
425 if (!pm)
426 return -EIO;
427
428 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700429 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 printk(KERN_DEBUG
431 "PCI: %s has unsupported PM cap regs version (%u)\n",
432 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
433 return -EIO;
434 }
435
436 /* check if this device supports the desired state */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700437 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
438 return -EIO;
439 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
440 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441
John W. Linville064b53db2005-07-27 10:19:44 -0400442 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
443
John W. Linville32a36582005-09-14 09:52:42 -0400444 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 * This doesn't affect PME_Status, disables PME_En, and
446 * sets PowerState to 0.
447 */
John W. Linville32a36582005-09-14 09:52:42 -0400448 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400449 case PCI_D0:
450 case PCI_D1:
451 case PCI_D2:
452 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
453 pmcsr |= state;
454 break;
John W. Linville32a36582005-09-14 09:52:42 -0400455 case PCI_UNKNOWN: /* Boot-up */
456 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
457 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
John W. Linville064b53db2005-07-27 10:19:44 -0400458 need_restore = 1;
John W. Linville32a36582005-09-14 09:52:42 -0400459 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400460 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400461 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400462 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 }
464
465 /* enter specified state */
466 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
467
468 /* Mandatory power management transition delays */
469 /* see PCI PM 1.1 5.6.1 table 18 */
470 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700471 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 else if (state == PCI_D2 || dev->current_state == PCI_D2)
473 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
David Shaohua Lib9131002005-03-19 00:16:18 -0500475 /*
476 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
Andreas Mohrd6e05ed2006-06-26 18:35:02 +0200477 * Firmware method after native method ?
David Shaohua Lib9131002005-03-19 00:16:18 -0500478 */
479 if (platform_pci_set_power_state)
480 platform_pci_set_power_state(dev, state);
481
482 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400483
484 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
485 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
486 * from D3hot to D0 _may_ perform an internal reset, thereby
487 * going to "D0 Uninitialized" rather than "D0 Initialized".
488 * For example, at least some versions of the 3c905B and the
489 * 3c556B exhibit this behaviour.
490 *
491 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
492 * devices in a D3hot state at boot. Consequently, we need to
493 * restore at least the BARs so that the device will be
494 * accessible to its driver.
495 */
496 if (need_restore)
497 pci_restore_bars(dev);
498
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 return 0;
500}
501
Greg Kroah-Hartmanf165b102005-03-30 21:23:19 -0500502int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
David Shaohua Li0f644742005-03-19 00:15:48 -0500503
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504/**
505 * pci_choose_state - Choose the power state of a PCI device
506 * @dev: PCI device to be suspended
507 * @state: target sleep state for the whole system. This is the value
508 * that is passed to suspend() function.
509 *
510 * Returns PCI power state suitable for given device and given system
511 * message.
512 */
513
514pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
515{
David Shaohua Li0f644742005-03-19 00:15:48 -0500516 int ret;
517
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
519 return PCI_D0;
520
David Shaohua Li0f644742005-03-19 00:15:48 -0500521 if (platform_pci_choose_state) {
522 ret = platform_pci_choose_state(dev, state);
523 if (ret >= 0)
Pavel Machekca078ba2005-09-03 15:56:57 -0700524 state.event = ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500525 }
Pavel Machekca078ba2005-09-03 15:56:57 -0700526
527 switch (state.event) {
528 case PM_EVENT_ON:
529 return PCI_D0;
530 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700531 case PM_EVENT_PRETHAW:
532 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700533 case PM_EVENT_SUSPEND:
534 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535 default:
David Brownellb887d2e2006-08-14 23:11:05 -0700536 printk("Unrecognized suspend event %d\n", state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 BUG();
538 }
539 return PCI_D0;
540}
541
542EXPORT_SYMBOL(pci_choose_state);
543
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300544static int pci_save_pcie_state(struct pci_dev *dev)
545{
546 int pos, i = 0;
547 struct pci_cap_saved_state *save_state;
548 u16 *cap;
549
550 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
551 if (pos <= 0)
552 return 0;
553
554 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
555 if (!save_state) {
556 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
557 return -ENOMEM;
558 }
559 cap = (u16 *)&save_state->data[0];
560
561 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
562 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
563 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
564 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
565 pci_add_saved_cap(dev, save_state);
566 return 0;
567}
568
569static void pci_restore_pcie_state(struct pci_dev *dev)
570{
571 int i = 0, pos;
572 struct pci_cap_saved_state *save_state;
573 u16 *cap;
574
575 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
576 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
577 if (!save_state || pos <= 0)
578 return;
579 cap = (u16 *)&save_state->data[0];
580
581 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
582 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
583 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
584 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
585 pci_remove_saved_cap(save_state);
586 kfree(save_state);
587}
588
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800589
590static int pci_save_pcix_state(struct pci_dev *dev)
591{
592 int pos, i = 0;
593 struct pci_cap_saved_state *save_state;
594 u16 *cap;
595
596 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
597 if (pos <= 0)
598 return 0;
599
600 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
601 if (!save_state) {
602 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
603 return -ENOMEM;
604 }
605 cap = (u16 *)&save_state->data[0];
606
607 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
608 pci_add_saved_cap(dev, save_state);
609 return 0;
610}
611
612static void pci_restore_pcix_state(struct pci_dev *dev)
613{
614 int i = 0, pos;
615 struct pci_cap_saved_state *save_state;
616 u16 *cap;
617
618 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
619 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
620 if (!save_state || pos <= 0)
621 return;
622 cap = (u16 *)&save_state->data[0];
623
624 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
625 pci_remove_saved_cap(save_state);
626 kfree(save_state);
627}
628
629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630/**
631 * pci_save_state - save the PCI configuration space of a device before suspending
632 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 */
634int
635pci_save_state(struct pci_dev *dev)
636{
637 int i;
638 /* XXX: 100% dword access ok here? */
639 for (i = 0; i < 16; i++)
640 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Shaohua Li41017f02006-02-08 17:11:38 +0800641 if ((i = pci_save_msi_state(dev)) != 0)
642 return i;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300643 if ((i = pci_save_pcie_state(dev)) != 0)
644 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800645 if ((i = pci_save_pcix_state(dev)) != 0)
646 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 return 0;
648}
649
650/**
651 * pci_restore_state - Restore the saved state of a PCI device
652 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 */
654int
655pci_restore_state(struct pci_dev *dev)
656{
657 int i;
Dave Jones04d9c1a2006-04-18 21:06:51 -0700658 int val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300660 /* PCI Express register must be restored first */
661 pci_restore_pcie_state(dev);
662
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700663 /*
664 * The Base Address register should be programmed before the command
665 * register(s)
666 */
667 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700668 pci_read_config_dword(dev, i * 4, &val);
669 if (val != dev->saved_config_space[i]) {
670 printk(KERN_DEBUG "PM: Writing back config space on "
671 "device %s at offset %x (was %x, writing %x)\n",
672 pci_name(dev), i,
673 val, (int)dev->saved_config_space[i]);
674 pci_write_config_dword(dev,i * 4,
675 dev->saved_config_space[i]);
676 }
677 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800678 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800679 pci_restore_msi_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100680
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 return 0;
682}
683
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900684static int do_pci_enable_device(struct pci_dev *dev, int bars)
685{
686 int err;
687
688 err = pci_set_power_state(dev, PCI_D0);
689 if (err < 0 && err != -EIO)
690 return err;
691 err = pcibios_enable_device(dev, bars);
692 if (err < 0)
693 return err;
694 pci_fixup_device(pci_fixup_enable, dev);
695
696 return 0;
697}
698
699/**
700 * __pci_reenable_device - Resume abandoned device
701 * @dev: PCI device to be resumed
702 *
703 * Note this function is a backend of pci_default_resume and is not supposed
704 * to be called by normal code, write proper resume handler and use it instead.
705 */
706int
707__pci_reenable_device(struct pci_dev *dev)
708{
709 if (atomic_read(&dev->enable_cnt))
710 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
711 return 0;
712}
713
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714/**
715 * pci_enable_device_bars - Initialize some of a device for use
716 * @dev: PCI device to be initialized
717 * @bars: bitmask of BAR's that must be configured
718 *
719 * Initialize device before it's used by a driver. Ask low-level code
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900720 * to enable selected I/O and memory resources. Wake up the device if it
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 * was suspended. Beware, this function can fail.
722 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723int
724pci_enable_device_bars(struct pci_dev *dev, int bars)
725{
726 int err;
727
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900728 if (atomic_add_return(1, &dev->enable_cnt) > 1)
729 return 0; /* already enabled */
730
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900731 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700732 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900733 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900734 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735}
736
737/**
738 * pci_enable_device - Initialize device before it's used by a driver.
739 * @dev: PCI device to be initialized
740 *
741 * Initialize device before it's used by a driver. Ask low-level code
742 * to enable I/O and memory. Wake up the device if it was suspended.
743 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800744 *
745 * Note we don't actually enable the device many times if we call
746 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800748int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749{
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900750 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751}
752
Tejun Heo9ac78492007-01-20 16:00:26 +0900753/*
754 * Managed PCI resources. This manages device on/off, intx/msi/msix
755 * on/off and BAR regions. pci_dev itself records msi/msix status, so
756 * there's no need to track it separately. pci_devres is initialized
757 * when a device is enabled using managed PCI device enable interface.
758 */
759struct pci_devres {
760 unsigned int disable:1;
761 unsigned int orig_intx:1;
762 unsigned int restore_intx:1;
763 u32 region_mask;
764};
765
766static void pcim_release(struct device *gendev, void *res)
767{
768 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
769 struct pci_devres *this = res;
770 int i;
771
772 if (dev->msi_enabled)
773 pci_disable_msi(dev);
774 if (dev->msix_enabled)
775 pci_disable_msix(dev);
776
777 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
778 if (this->region_mask & (1 << i))
779 pci_release_region(dev, i);
780
781 if (this->restore_intx)
782 pci_intx(dev, this->orig_intx);
783
784 if (this->disable)
785 pci_disable_device(dev);
786}
787
788static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
789{
790 struct pci_devres *dr, *new_dr;
791
792 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
793 if (dr)
794 return dr;
795
796 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
797 if (!new_dr)
798 return NULL;
799 return devres_get(&pdev->dev, new_dr, NULL, NULL);
800}
801
802static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
803{
804 if (pci_is_managed(pdev))
805 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
806 return NULL;
807}
808
809/**
810 * pcim_enable_device - Managed pci_enable_device()
811 * @pdev: PCI device to be initialized
812 *
813 * Managed pci_enable_device().
814 */
815int pcim_enable_device(struct pci_dev *pdev)
816{
817 struct pci_devres *dr;
818 int rc;
819
820 dr = get_pci_dr(pdev);
821 if (unlikely(!dr))
822 return -ENOMEM;
823 WARN_ON(!!dr->disable);
824
825 rc = pci_enable_device(pdev);
826 if (!rc) {
827 pdev->is_managed = 1;
828 dr->disable = 1;
829 }
830 return rc;
831}
832
833/**
834 * pcim_pin_device - Pin managed PCI device
835 * @pdev: PCI device to pin
836 *
837 * Pin managed PCI device @pdev. Pinned device won't be disabled on
838 * driver detach. @pdev must have been enabled with
839 * pcim_enable_device().
840 */
841void pcim_pin_device(struct pci_dev *pdev)
842{
843 struct pci_devres *dr;
844
845 dr = find_pci_dr(pdev);
846 WARN_ON(!dr || !dr->disable);
847 if (dr)
848 dr->disable = 0;
849}
850
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851/**
852 * pcibios_disable_device - disable arch specific PCI resources for device dev
853 * @dev: the PCI device to disable
854 *
855 * Disables architecture specific PCI resources for the device. This
856 * is the default implementation. Architecture implementations can
857 * override this.
858 */
859void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
860
861/**
862 * pci_disable_device - Disable PCI device after use
863 * @dev: PCI device to be disabled
864 *
865 * Signal to the system that the PCI device is not in use by the system
866 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800867 *
868 * Note we don't actually disable the device until all callers of
869 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 */
871void
872pci_disable_device(struct pci_dev *dev)
873{
Tejun Heo9ac78492007-01-20 16:00:26 +0900874 struct pci_devres *dr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 u16 pci_command;
Shaohua Li99dc8042006-05-26 10:58:27 +0800876
Tejun Heo9ac78492007-01-20 16:00:26 +0900877 dr = find_pci_dr(dev);
878 if (dr)
879 dr->disable = 0;
880
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800881 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
882 return;
883
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
885 if (pci_command & PCI_COMMAND_MASTER) {
886 pci_command &= ~PCI_COMMAND_MASTER;
887 pci_write_config_word(dev, PCI_COMMAND, pci_command);
888 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900889 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890
891 pcibios_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892}
893
894/**
895 * pci_enable_wake - enable device to generate PME# when suspended
896 * @dev: - PCI device to operate on
897 * @state: - Current state of device.
898 * @enable: - Flag to enable or disable generation
899 *
900 * Set the bits in the device's PM Capabilities to generate PME# when
901 * the system is suspended.
902 *
903 * -EIO is returned if device doesn't have PM Capabilities.
904 * -EINVAL is returned if device supports it, but can't generate wake events.
905 * 0 if operation is successful.
906 *
907 */
908int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
909{
910 int pm;
911 u16 value;
912
913 /* find PCI PM capability in list */
914 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
915
916 /* If device doesn't support PM Capabilities, but request is to disable
917 * wake events, it's a nop; otherwise fail */
918 if (!pm)
919 return enable ? -EIO : 0;
920
921 /* Check device's ability to generate PME# */
922 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
923
924 value &= PCI_PM_CAP_PME_MASK;
925 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
926
927 /* Check if it can generate PME# from requested state. */
928 if (!value || !(value & (1 << state)))
929 return enable ? -EINVAL : 0;
930
931 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
932
933 /* Clear PME_Status by writing 1 to it and enable PME# */
934 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
935
936 if (!enable)
937 value &= ~PCI_PM_CTRL_PME_ENABLE;
938
939 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
940
941 return 0;
942}
943
944int
945pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
946{
947 u8 pin;
948
Kristen Accardi514d2072005-11-02 16:24:39 -0800949 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950 if (!pin)
951 return -1;
952 pin--;
953 while (dev->bus->self) {
954 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
955 dev = dev->bus->self;
956 }
957 *bridge = dev;
958 return pin;
959}
960
961/**
962 * pci_release_region - Release a PCI bar
963 * @pdev: PCI device whose resources were previously reserved by pci_request_region
964 * @bar: BAR to release
965 *
966 * Releases the PCI I/O and memory resources previously reserved by a
967 * successful call to pci_request_region. Call this function only
968 * after all use of the PCI regions has ceased.
969 */
970void pci_release_region(struct pci_dev *pdev, int bar)
971{
Tejun Heo9ac78492007-01-20 16:00:26 +0900972 struct pci_devres *dr;
973
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 if (pci_resource_len(pdev, bar) == 0)
975 return;
976 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
977 release_region(pci_resource_start(pdev, bar),
978 pci_resource_len(pdev, bar));
979 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
980 release_mem_region(pci_resource_start(pdev, bar),
981 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +0900982
983 dr = find_pci_dr(pdev);
984 if (dr)
985 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986}
987
988/**
989 * pci_request_region - Reserved PCI I/O and memory resource
990 * @pdev: PCI device whose resources are to be reserved
991 * @bar: BAR to be reserved
992 * @res_name: Name to be associated with resource.
993 *
994 * Mark the PCI region associated with PCI device @pdev BR @bar as
995 * being reserved by owner @res_name. Do not access any
996 * address inside the PCI regions unless this call returns
997 * successfully.
998 *
999 * Returns 0 on success, or %EBUSY on error. A warning
1000 * message is also printed on failure.
1001 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001002int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003{
Tejun Heo9ac78492007-01-20 16:00:26 +09001004 struct pci_devres *dr;
1005
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 if (pci_resource_len(pdev, bar) == 0)
1007 return 0;
1008
1009 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1010 if (!request_region(pci_resource_start(pdev, bar),
1011 pci_resource_len(pdev, bar), res_name))
1012 goto err_out;
1013 }
1014 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1015 if (!request_mem_region(pci_resource_start(pdev, bar),
1016 pci_resource_len(pdev, bar), res_name))
1017 goto err_out;
1018 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001019
1020 dr = find_pci_dr(pdev);
1021 if (dr)
1022 dr->region_mask |= 1 << bar;
1023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 return 0;
1025
1026err_out:
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001027 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1028 "for device %s\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1030 bar + 1, /* PCI BAR # */
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -07001031 (unsigned long long)pci_resource_len(pdev, bar),
1032 (unsigned long long)pci_resource_start(pdev, bar),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033 pci_name(pdev));
1034 return -EBUSY;
1035}
1036
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001037/**
1038 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1039 * @pdev: PCI device whose resources were previously reserved
1040 * @bars: Bitmask of BARs to be released
1041 *
1042 * Release selected PCI I/O and memory resources previously reserved.
1043 * Call this function only after all use of the PCI regions has ceased.
1044 */
1045void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1046{
1047 int i;
1048
1049 for (i = 0; i < 6; i++)
1050 if (bars & (1 << i))
1051 pci_release_region(pdev, i);
1052}
1053
1054/**
1055 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1056 * @pdev: PCI device whose resources are to be reserved
1057 * @bars: Bitmask of BARs to be requested
1058 * @res_name: Name to be associated with resource
1059 */
1060int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1061 const char *res_name)
1062{
1063 int i;
1064
1065 for (i = 0; i < 6; i++)
1066 if (bars & (1 << i))
1067 if(pci_request_region(pdev, i, res_name))
1068 goto err_out;
1069 return 0;
1070
1071err_out:
1072 while(--i >= 0)
1073 if (bars & (1 << i))
1074 pci_release_region(pdev, i);
1075
1076 return -EBUSY;
1077}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078
1079/**
1080 * pci_release_regions - Release reserved PCI I/O and memory resources
1081 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1082 *
1083 * Releases all PCI I/O and memory resources previously reserved by a
1084 * successful call to pci_request_regions. Call this function only
1085 * after all use of the PCI regions has ceased.
1086 */
1087
1088void pci_release_regions(struct pci_dev *pdev)
1089{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001090 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091}
1092
1093/**
1094 * pci_request_regions - Reserved PCI I/O and memory resources
1095 * @pdev: PCI device whose resources are to be reserved
1096 * @res_name: Name to be associated with resource.
1097 *
1098 * Mark all PCI regions associated with PCI device @pdev as
1099 * being reserved by owner @res_name. Do not access any
1100 * address inside the PCI regions unless this call returns
1101 * successfully.
1102 *
1103 * Returns 0 on success, or %EBUSY on error. A warning
1104 * message is also printed on failure.
1105 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001106int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001108 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109}
1110
1111/**
1112 * pci_set_master - enables bus-mastering for device dev
1113 * @dev: the PCI device to enable
1114 *
1115 * Enables bus-mastering on the device and calls pcibios_set_master()
1116 * to do the needed arch specific settings.
1117 */
1118void
1119pci_set_master(struct pci_dev *dev)
1120{
1121 u16 cmd;
1122
1123 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1124 if (! (cmd & PCI_COMMAND_MASTER)) {
1125 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1126 cmd |= PCI_COMMAND_MASTER;
1127 pci_write_config_word(dev, PCI_COMMAND, cmd);
1128 }
1129 dev->is_busmaster = 1;
1130 pcibios_set_master(dev);
1131}
1132
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001133#ifdef PCI_DISABLE_MWI
1134int pci_set_mwi(struct pci_dev *dev)
1135{
1136 return 0;
1137}
1138
1139void pci_clear_mwi(struct pci_dev *dev)
1140{
1141}
1142
1143#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001144
1145#ifndef PCI_CACHE_LINE_BYTES
1146#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1147#endif
1148
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001150/* Don't forget this is measured in 32-bit words, not bytes */
1151u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152
1153/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001154 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1155 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001157 * Helper function for pci_set_mwi.
1158 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1160 *
1161 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1162 */
1163static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001164pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001165{
1166 u8 cacheline_size;
1167
1168 if (!pci_cache_line_size)
1169 return -EINVAL; /* The system doesn't support MWI. */
1170
1171 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1172 equal to or multiple of the right value. */
1173 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1174 if (cacheline_size >= pci_cache_line_size &&
1175 (cacheline_size % pci_cache_line_size) == 0)
1176 return 0;
1177
1178 /* Write the correct value. */
1179 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1180 /* Read it back. */
1181 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1182 if (cacheline_size == pci_cache_line_size)
1183 return 0;
1184
1185 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1186 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1187
1188 return -EINVAL;
1189}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190
1191/**
1192 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1193 * @dev: the PCI device for which MWI is enabled
1194 *
1195 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
1196 * and then calls @pcibios_set_mwi to do the needed arch specific
1197 * operations or a generic mwi-prep function.
1198 *
1199 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1200 */
1201int
1202pci_set_mwi(struct pci_dev *dev)
1203{
1204 int rc;
1205 u16 cmd;
1206
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001207 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 if (rc)
1209 return rc;
1210
1211 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1212 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1213 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
1214 cmd |= PCI_COMMAND_INVALIDATE;
1215 pci_write_config_word(dev, PCI_COMMAND, cmd);
1216 }
1217
1218 return 0;
1219}
1220
1221/**
1222 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1223 * @dev: the PCI device to disable
1224 *
1225 * Disables PCI Memory-Write-Invalidate transaction on the device
1226 */
1227void
1228pci_clear_mwi(struct pci_dev *dev)
1229{
1230 u16 cmd;
1231
1232 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1233 if (cmd & PCI_COMMAND_INVALIDATE) {
1234 cmd &= ~PCI_COMMAND_INVALIDATE;
1235 pci_write_config_word(dev, PCI_COMMAND, cmd);
1236 }
1237}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001238#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
Brett M Russa04ce0f2005-08-15 15:23:41 -04001240/**
1241 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001242 * @pdev: the PCI device to operate on
1243 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001244 *
1245 * Enables/disables PCI INTx for device dev
1246 */
1247void
1248pci_intx(struct pci_dev *pdev, int enable)
1249{
1250 u16 pci_command, new;
1251
1252 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1253
1254 if (enable) {
1255 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1256 } else {
1257 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1258 }
1259
1260 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001261 struct pci_devres *dr;
1262
Brett M Russ2fd9d742005-09-09 10:02:22 -07001263 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001264
1265 dr = find_pci_dr(pdev);
1266 if (dr && !dr->restore_intx) {
1267 dr->restore_intx = 1;
1268 dr->orig_intx = !enable;
1269 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001270 }
1271}
1272
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001273/**
1274 * pci_msi_off - disables any msi or msix capabilities
1275 * @pdev: the PCI device to operate on
1276 *
1277 * If you want to use msi see pci_enable_msi and friends.
1278 * This is a lower level primitive that allows us to disable
1279 * msi operation at the device level.
1280 */
1281void pci_msi_off(struct pci_dev *dev)
1282{
1283 int pos;
1284 u16 control;
1285
1286 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1287 if (pos) {
1288 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1289 control &= ~PCI_MSI_FLAGS_ENABLE;
1290 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1291 }
1292 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1293 if (pos) {
1294 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1295 control &= ~PCI_MSIX_FLAGS_ENABLE;
1296 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1297 }
1298}
1299
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1301/*
1302 * These can be overridden by arch-specific implementations
1303 */
1304int
1305pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1306{
1307 if (!pci_dma_supported(dev, mask))
1308 return -EIO;
1309
1310 dev->dma_mask = mask;
1311
1312 return 0;
1313}
1314
1315int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1317{
1318 if (!pci_dma_supported(dev, mask))
1319 return -EIO;
1320
1321 dev->dev.coherent_dma_mask = mask;
1322
1323 return 0;
1324}
1325#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001326
1327/**
1328 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08001329 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001330 * @flags: resource type mask to be selected
1331 *
1332 * This helper routine makes bar mask from the type of resource.
1333 */
1334int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1335{
1336 int i, bars = 0;
1337 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1338 if (pci_resource_flags(dev, i) & flags)
1339 bars |= (1 << i);
1340 return bars;
1341}
1342
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343static int __devinit pci_init(void)
1344{
1345 struct pci_dev *dev = NULL;
1346
1347 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1348 pci_fixup_device(pci_fixup_final, dev);
1349 }
1350 return 0;
1351}
1352
1353static int __devinit pci_setup(char *str)
1354{
1355 while (str) {
1356 char *k = strchr(str, ',');
1357 if (k)
1358 *k++ = 0;
1359 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001360 if (!strcmp(str, "nomsi")) {
1361 pci_no_msi();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08001362 } else if (!strncmp(str, "cbiosize=", 9)) {
1363 pci_cardbus_io_size = memparse(str + 9, &str);
1364 } else if (!strncmp(str, "cbmemsize=", 10)) {
1365 pci_cardbus_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001366 } else {
1367 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1368 str);
1369 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 }
1371 str = k;
1372 }
Andi Kleen0637a702006-09-26 10:52:41 +02001373 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374}
Andi Kleen0637a702006-09-26 10:52:41 +02001375early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376
1377device_initcall(pci_init);
1378
John W. Linville064b53db2005-07-27 10:19:44 -04001379EXPORT_SYMBOL_GPL(pci_restore_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380EXPORT_SYMBOL(pci_enable_device_bars);
1381EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001382EXPORT_SYMBOL(pcim_enable_device);
1383EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385EXPORT_SYMBOL(pci_find_capability);
1386EXPORT_SYMBOL(pci_bus_find_capability);
1387EXPORT_SYMBOL(pci_release_regions);
1388EXPORT_SYMBOL(pci_request_regions);
1389EXPORT_SYMBOL(pci_release_region);
1390EXPORT_SYMBOL(pci_request_region);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001391EXPORT_SYMBOL(pci_release_selected_regions);
1392EXPORT_SYMBOL(pci_request_selected_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393EXPORT_SYMBOL(pci_set_master);
1394EXPORT_SYMBOL(pci_set_mwi);
1395EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04001396EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1399EXPORT_SYMBOL(pci_assign_resource);
1400EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001401EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402
1403EXPORT_SYMBOL(pci_set_power_state);
1404EXPORT_SYMBOL(pci_save_state);
1405EXPORT_SYMBOL(pci_restore_state);
1406EXPORT_SYMBOL(pci_enable_wake);
1407