Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
| 7 | * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/module.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 14 | #include <linux/irq.h> |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 15 | #include <asm/irq_cpu.h> |
| 16 | #include <asm/mipsregs.h> |
| 17 | #include <bcm63xx_cpu.h> |
| 18 | #include <bcm63xx_regs.h> |
| 19 | #include <bcm63xx_io.h> |
| 20 | #include <bcm63xx_irq.h> |
| 21 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 22 | static void __dispatch_internal(void) __maybe_unused; |
| 23 | |
| 24 | #ifndef BCMCPU_RUNTIME_DETECT |
| 25 | #ifdef CONFIG_BCM63XX_CPU_6338 |
| 26 | #define irq_stat_reg PERF_IRQSTAT_6338_REG |
| 27 | #define irq_mask_reg PERF_IRQMASK_6338_REG |
| 28 | #endif |
| 29 | #ifdef CONFIG_BCM63XX_CPU_6345 |
| 30 | #define irq_stat_reg PERF_IRQSTAT_6345_REG |
| 31 | #define irq_mask_reg PERF_IRQMASK_6345_REG |
| 32 | #endif |
| 33 | #ifdef CONFIG_BCM63XX_CPU_6348 |
| 34 | #define irq_stat_reg PERF_IRQSTAT_6348_REG |
| 35 | #define irq_mask_reg PERF_IRQMASK_6348_REG |
| 36 | #endif |
| 37 | #ifdef CONFIG_BCM63XX_CPU_6358 |
| 38 | #define irq_stat_reg PERF_IRQSTAT_6358_REG |
| 39 | #define irq_mask_reg PERF_IRQMASK_6358_REG |
| 40 | #endif |
| 41 | |
| 42 | #define dispatch_internal __dispatch_internal |
| 43 | |
| 44 | #define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg) |
| 45 | #define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg) |
| 46 | |
| 47 | static inline void bcm63xx_init_irq(void) |
| 48 | { |
| 49 | } |
| 50 | #else /* ! BCMCPU_RUNTIME_DETECT */ |
| 51 | |
| 52 | static u32 irq_stat_addr, irq_mask_addr; |
| 53 | static void (*dispatch_internal)(void); |
| 54 | |
| 55 | static void bcm63xx_init_irq(void) |
| 56 | { |
| 57 | irq_stat_addr = bcm63xx_regset_address(RSET_PERF); |
| 58 | irq_mask_addr = bcm63xx_regset_address(RSET_PERF); |
| 59 | |
| 60 | switch (bcm63xx_get_cpu_id()) { |
| 61 | case BCM6338_CPU_ID: |
| 62 | irq_stat_addr += PERF_IRQSTAT_6338_REG; |
| 63 | irq_mask_addr += PERF_IRQMASK_6338_REG; |
| 64 | break; |
| 65 | case BCM6345_CPU_ID: |
| 66 | irq_stat_addr += PERF_IRQSTAT_6345_REG; |
| 67 | irq_mask_addr += PERF_IRQMASK_6345_REG; |
| 68 | break; |
| 69 | case BCM6348_CPU_ID: |
| 70 | irq_stat_addr += PERF_IRQSTAT_6348_REG; |
| 71 | irq_mask_addr += PERF_IRQMASK_6348_REG; |
| 72 | break; |
| 73 | case BCM6358_CPU_ID: |
| 74 | irq_stat_addr += PERF_IRQSTAT_6358_REG; |
| 75 | irq_mask_addr += PERF_IRQMASK_6358_REG; |
| 76 | break; |
| 77 | default: |
| 78 | BUG(); |
| 79 | } |
| 80 | |
| 81 | dispatch_internal = __dispatch_internal; |
| 82 | } |
| 83 | #endif /* ! BCMCPU_RUNTIME_DETECT */ |
| 84 | |
| 85 | static inline void handle_internal(int intbit) |
| 86 | { |
| 87 | do_IRQ(intbit + IRQ_INTERNAL_BASE); |
| 88 | } |
| 89 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 90 | /* |
| 91 | * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not |
| 92 | * prioritize any interrupt relatively to another. the static counter |
| 93 | * will resume the loop where it ended the last time we left this |
| 94 | * function. |
| 95 | */ |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 96 | static void __dispatch_internal(void) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 97 | { |
| 98 | u32 pending; |
| 99 | static int i; |
| 100 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 101 | pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 102 | |
| 103 | if (!pending) |
| 104 | return ; |
| 105 | |
| 106 | while (1) { |
| 107 | int to_call = i; |
| 108 | |
| 109 | i = (i + 1) & 0x1f; |
| 110 | if (pending & (1 << to_call)) { |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 111 | handle_internal(to_call); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 112 | break; |
| 113 | } |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | asmlinkage void plat_irq_dispatch(void) |
| 118 | { |
| 119 | u32 cause; |
| 120 | |
| 121 | do { |
| 122 | cause = read_c0_cause() & read_c0_status() & ST0_IM; |
| 123 | |
| 124 | if (!cause) |
| 125 | break; |
| 126 | |
| 127 | if (cause & CAUSEF_IP7) |
| 128 | do_IRQ(7); |
| 129 | if (cause & CAUSEF_IP2) |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 130 | dispatch_internal(); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 131 | if (cause & CAUSEF_IP3) |
| 132 | do_IRQ(IRQ_EXT_0); |
| 133 | if (cause & CAUSEF_IP4) |
| 134 | do_IRQ(IRQ_EXT_1); |
| 135 | if (cause & CAUSEF_IP5) |
| 136 | do_IRQ(IRQ_EXT_2); |
| 137 | if (cause & CAUSEF_IP6) |
| 138 | do_IRQ(IRQ_EXT_3); |
| 139 | } while (1); |
| 140 | } |
| 141 | |
| 142 | /* |
| 143 | * internal IRQs operations: only mask/unmask on PERF irq mask |
| 144 | * register. |
| 145 | */ |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 146 | static inline void bcm63xx_internal_irq_mask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 147 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 148 | unsigned int irq = d->irq - IRQ_INTERNAL_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 149 | u32 mask; |
| 150 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 151 | mask = bcm_readl(irq_mask_addr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 152 | mask &= ~(1 << irq); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 153 | bcm_writel(mask, irq_mask_addr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 154 | } |
| 155 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 156 | static void bcm63xx_internal_irq_unmask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 157 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 158 | unsigned int irq = d->irq - IRQ_INTERNAL_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 159 | u32 mask; |
| 160 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 161 | mask = bcm_readl(irq_mask_addr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 162 | mask |= (1 << irq); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 163 | bcm_writel(mask, irq_mask_addr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 166 | /* |
| 167 | * external IRQs operations: mask/unmask and clear on PERF external |
| 168 | * irq control register. |
| 169 | */ |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 170 | static void bcm63xx_external_irq_mask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 171 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 172 | unsigned int irq = d->irq - IRQ_EXT_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 173 | u32 reg; |
| 174 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 175 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
| 176 | reg &= ~EXTIRQ_CFG_MASK(irq); |
| 177 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
| 178 | } |
| 179 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 180 | static void bcm63xx_external_irq_unmask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 181 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 182 | unsigned int irq = d->irq - IRQ_EXT_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 183 | u32 reg; |
| 184 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 185 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
| 186 | reg |= EXTIRQ_CFG_MASK(irq); |
| 187 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
| 188 | } |
| 189 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 190 | static void bcm63xx_external_irq_clear(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 191 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 192 | unsigned int irq = d->irq - IRQ_EXT_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 193 | u32 reg; |
| 194 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 195 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
| 196 | reg |= EXTIRQ_CFG_CLEAR(irq); |
| 197 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
| 198 | } |
| 199 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 200 | static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 201 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 202 | set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 203 | irq_enable_hazard(); |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 204 | bcm63xx_external_irq_unmask(d); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 205 | return 0; |
| 206 | } |
| 207 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 208 | static void bcm63xx_external_irq_shutdown(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 209 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 210 | bcm63xx_external_irq_mask(d); |
| 211 | clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 212 | irq_disable_hazard(); |
| 213 | } |
| 214 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 215 | static int bcm63xx_external_irq_set_type(struct irq_data *d, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 216 | unsigned int flow_type) |
| 217 | { |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 218 | unsigned int irq = d->irq - IRQ_EXT_BASE; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 219 | u32 reg; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 220 | |
| 221 | flow_type &= IRQ_TYPE_SENSE_MASK; |
| 222 | |
| 223 | if (flow_type == IRQ_TYPE_NONE) |
| 224 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 225 | |
| 226 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
| 227 | switch (flow_type) { |
| 228 | case IRQ_TYPE_EDGE_BOTH: |
| 229 | reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
| 230 | reg |= EXTIRQ_CFG_BOTHEDGE(irq); |
| 231 | break; |
| 232 | |
| 233 | case IRQ_TYPE_EDGE_RISING: |
| 234 | reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
| 235 | reg |= EXTIRQ_CFG_SENSE(irq); |
| 236 | reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
| 237 | break; |
| 238 | |
| 239 | case IRQ_TYPE_EDGE_FALLING: |
| 240 | reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
| 241 | reg &= ~EXTIRQ_CFG_SENSE(irq); |
| 242 | reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
| 243 | break; |
| 244 | |
| 245 | case IRQ_TYPE_LEVEL_HIGH: |
| 246 | reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
| 247 | reg |= EXTIRQ_CFG_SENSE(irq); |
| 248 | break; |
| 249 | |
| 250 | case IRQ_TYPE_LEVEL_LOW: |
| 251 | reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
| 252 | reg &= ~EXTIRQ_CFG_SENSE(irq); |
| 253 | break; |
| 254 | |
| 255 | default: |
| 256 | printk(KERN_ERR "bogus flow type combination given !\n"); |
| 257 | return -EINVAL; |
| 258 | } |
| 259 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
| 260 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 261 | irqd_set_trigger_type(d, flow_type); |
| 262 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
| 263 | __irq_set_handler_locked(d->irq, handle_level_irq); |
| 264 | else |
| 265 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 266 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 267 | return IRQ_SET_MASK_OK_NOCOPY; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | static struct irq_chip bcm63xx_internal_irq_chip = { |
| 271 | .name = "bcm63xx_ipic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 272 | .irq_mask = bcm63xx_internal_irq_mask, |
| 273 | .irq_unmask = bcm63xx_internal_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | static struct irq_chip bcm63xx_external_irq_chip = { |
| 277 | .name = "bcm63xx_epic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 278 | .irq_startup = bcm63xx_external_irq_startup, |
| 279 | .irq_shutdown = bcm63xx_external_irq_shutdown, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 280 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 281 | .irq_ack = bcm63xx_external_irq_clear, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 282 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 283 | .irq_mask = bcm63xx_external_irq_mask, |
| 284 | .irq_unmask = bcm63xx_external_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 285 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 286 | .irq_set_type = bcm63xx_external_irq_set_type, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | static struct irqaction cpu_ip2_cascade_action = { |
| 290 | .handler = no_action, |
| 291 | .name = "cascade_ip2", |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 292 | .flags = IRQF_NO_THREAD, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 293 | }; |
| 294 | |
| 295 | void __init arch_init_irq(void) |
| 296 | { |
| 297 | int i; |
| 298 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame^] | 299 | bcm63xx_init_irq(); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 300 | mips_cpu_irq_init(); |
| 301 | for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 302 | irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 303 | handle_level_irq); |
| 304 | |
| 305 | for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 306 | irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 307 | handle_edge_irq); |
| 308 | |
| 309 | setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); |
| 310 | } |