blob: 32a1b5cfeba1f426547127233c84732363fc4e30 [file] [log] [blame]
Daniel Ribeiro13a09f92009-05-28 15:43:37 -03001/*
2 * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
3 *
4 * For further information, please see http://wiki.openezx.org/PCAP2
5 */
6
7#ifndef EZX_PCAP_H
8#define EZX_PCAP_H
9
10struct pcap_subdev {
11 int id;
12 const char *name;
13 void *platform_data;
14};
15
16struct pcap_platform_data {
17 unsigned int irq_base;
18 unsigned int config;
Arnd Bergmann59ee93a2012-08-05 14:58:37 +000019 int gpio;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030020 void (*init) (void *); /* board specific init */
21 int num_subdevs;
22 struct pcap_subdev *subdevs;
23};
24
25struct pcap_chip;
26
27int ezx_pcap_write(struct pcap_chip *, u8, u32);
28int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
Daniel Ribeiroe9a22632009-06-27 00:17:20 -030029int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030030int pcap_to_irq(struct pcap_chip *, int);
Daniel Ribeiro9f7b07d2009-06-23 12:32:11 -030031int irq_to_pcap(struct pcap_chip *, int);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030032int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
33int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -030034void pcap_set_ts_bits(struct pcap_chip *, u32);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030035
36#define PCAP_SECOND_PORT 1
37#define PCAP_CS_AH 2
38
39#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
40#define PCAP_REGISTER_READ_OP_BIT 0x00000000
41
42#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
43#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
44#define PCAP_REGISTER_ADDRESS_SHIFT 26
45#define PCAP_REGISTER_NUMBER 32
46#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
47#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
48
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020049/* registers accessible by both pcap ports */
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030050#define PCAP_REG_ISR 0x0 /* Interrupt Status */
51#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
52#define PCAP_REG_PSTAT 0x2 /* Processor Status */
53#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
54#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
55#define PCAP_REG_BATT 0x8 /* Battery Control */
56#define PCAP_REG_ADC 0x9 /* AD Control */
57#define PCAP_REG_ADR 0xa /* AD Result */
58#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
59#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
60#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
61#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
62#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
63#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
64#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
65#define PCAP_REG_GP 0x1b /* General Purpose */
66#define PCAP_REG_TEST1 0x1c
67#define PCAP_REG_TEST2 0x1d
68#define PCAP_REG_VENDOR_TEST1 0x1e
69#define PCAP_REG_VENDOR_TEST2 0x1f
70
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020071/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030072#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
73#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
74#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
75#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
76#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
77#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
78#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
79#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
80#define PCAP_REG_PWR 0x13 /* Power Control */
81#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
82#define PCAP_REG_VENDOR_REV 0x17
83#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
84
85/* PCAP2 Interrupts */
86#define PCAP_NIRQS 23
87#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
88#define PCAP_IRQ_TS 1 /* Touch Screen */
89#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
90#define PCAP_IRQ_WH 3 /* ADC above high limit */
91#define PCAP_IRQ_WL 4 /* ADC below low limit */
92#define PCAP_IRQ_TODA 5 /* Time of day alarm */
93#define PCAP_IRQ_USB4V 6 /* USB above 4V */
94#define PCAP_IRQ_ONOFF 7 /* On/Off button */
95#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
96#define PCAP_IRQ_USB1V 9 /* USB above 1V */
97#define PCAP_IRQ_MOBPORT 10
98#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
99#define PCAP_IRQ_HS 12 /* Headset attach */
100#define PCAP_IRQ_ST 13
101#define PCAP_IRQ_PC 14 /* Power Cut */
102#define PCAP_IRQ_WARM 15
103#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
104#define PCAP_IRQ_CLK 17
105#define PCAP_IRQ_SYSRST 18 /* System Reset */
106#define PCAP_IRQ_DUMMY 19
107#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
108#define PCAP_IRQ_SOFTRESET 21
109#define PCAP_IRQ_MNEXB 22
110
111/* voltage regulators */
112#define V1 0
113#define V2 1
114#define V3 2
115#define V4 3
116#define V5 4
117#define V6 5
118#define V7 6
119#define V8 7
120#define V9 8
121#define V10 9
122#define VAUX1 10
123#define VAUX2 11
124#define VAUX3 12
125#define VAUX4 13
126#define VSIM 14
127#define VSIM2 15
128#define VVIB 16
129#define SW1 17
130#define SW2 18
131#define SW3 19
132#define SW1S 20
133#define SW2S 21
134
135#define PCAP_BATT_DAC_MASK 0x000000ff
136#define PCAP_BATT_DAC_SHIFT 0
137#define PCAP_BATT_B_FDBK (1 << 8)
138#define PCAP_BATT_EXT_ISENSE (1 << 9)
139#define PCAP_BATT_V_COIN_MASK 0x00003c00
140#define PCAP_BATT_V_COIN_SHIFT 10
141#define PCAP_BATT_I_COIN (1 << 14)
142#define PCAP_BATT_COIN_CH_EN (1 << 15)
143#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
144#define PCAP_BATT_EOL_SEL_SHIFT 17
145#define PCAP_BATT_EOL_CMP_EN (1 << 20)
146#define PCAP_BATT_BATT_DET_EN (1 << 21)
147#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
148
149#define PCAP_ADC_ADEN (1 << 0)
150#define PCAP_ADC_RAND (1 << 1)
151#define PCAP_ADC_AD_SEL1 (1 << 2)
152#define PCAP_ADC_AD_SEL2 (1 << 3)
153#define PCAP_ADC_ADA1_MASK 0x00000070
154#define PCAP_ADC_ADA1_SHIFT 4
155#define PCAP_ADC_ADA2_MASK 0x00000380
156#define PCAP_ADC_ADA2_SHIFT 7
157#define PCAP_ADC_ATO_MASK 0x00003c00
158#define PCAP_ADC_ATO_SHIFT 10
159#define PCAP_ADC_ATOX (1 << 14)
160#define PCAP_ADC_MTR1 (1 << 15)
161#define PCAP_ADC_MTR2 (1 << 16)
162#define PCAP_ADC_TS_M_MASK 0x000e0000
163#define PCAP_ADC_TS_M_SHIFT 17
164#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
165#define PCAP_ADC_TS_REFENB (1 << 21)
166#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
167#define PCAP_ADC_BATT_I_ADC (1 << 23)
168
169#define PCAP_ADC_BANK_0 0
170#define PCAP_ADC_BANK_1 1
171/* ADC bank 0 */
172#define PCAP_ADC_CH_COIN 0
173#define PCAP_ADC_CH_BATT 1
174#define PCAP_ADC_CH_BPLUS 2
175#define PCAP_ADC_CH_MOBPORTB 3
176#define PCAP_ADC_CH_TEMPERATURE 4
177#define PCAP_ADC_CH_CHARGER_ID 5
178#define PCAP_ADC_CH_AD6 6
179/* ADC bank 1 */
180#define PCAP_ADC_CH_AD7 0
181#define PCAP_ADC_CH_AD8 1
182#define PCAP_ADC_CH_AD9 2
183#define PCAP_ADC_CH_TS_X1 3
184#define PCAP_ADC_CH_TS_X2 4
185#define PCAP_ADC_CH_TS_Y1 5
186#define PCAP_ADC_CH_TS_Y2 6
187
188#define PCAP_ADC_T_NOW 0
189#define PCAP_ADC_T_IN_BURST 1
190#define PCAP_ADC_T_OUT_BURST 2
191
192#define PCAP_ADC_ATO_IN_BURST 6
193#define PCAP_ADC_ATO_OUT_BURST 0
194
195#define PCAP_ADC_TS_M_XY 1
196#define PCAP_ADC_TS_M_PRESSURE 2
197#define PCAP_ADC_TS_M_PLATE_X 3
198#define PCAP_ADC_TS_M_PLATE_Y 4
199#define PCAP_ADC_TS_M_STANDBY 5
200#define PCAP_ADC_TS_M_NONTS 6
201
202#define PCAP_ADR_ADD1_MASK 0x000003ff
203#define PCAP_ADR_ADD1_SHIFT 0
204#define PCAP_ADR_ADD2_MASK 0x000ffc00
205#define PCAP_ADR_ADD2_SHIFT 10
206#define PCAP_ADR_ADINC1 (1 << 20)
207#define PCAP_ADR_ADINC2 (1 << 21)
208#define PCAP_ADR_ASC (1 << 22)
209#define PCAP_ADR_ONESHOT (1 << 23)
210
211#define PCAP_BUSCTRL_FSENB (1 << 0)
212#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
213#define PCAP_BUSCTRL_USB_PU (1 << 2)
214#define PCAP_BUSCTRL_USB_PD (1 << 3)
215#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
216#define PCAP_BUSCTRL_USB_PS (1 << 5)
217#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
218#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
219#define PCAP_BUSCTRL_CURRLIM (1 << 8)
220#define PCAP_BUSCTRL_RS232ENB (1 << 9)
221#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
222#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
223#define PCAP_BUSCTRL_USB_PDM (1 << 12)
224#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
225
226/* leds */
227#define PCAP_LED0 0
228#define PCAP_LED1 1
229#define PCAP_BL0 2
230#define PCAP_BL1 3
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300231#define PCAP_LED_3MA 0
232#define PCAP_LED_4MA 1
233#define PCAP_LED_5MA 2
234#define PCAP_LED_9MA 3
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300235#define PCAP_LED_T_MASK 0xf
236#define PCAP_LED_C_MASK 0x3
237#define PCAP_BL_MASK 0x1f
238#define PCAP_BL0_SHIFT 0
239#define PCAP_LED0_EN (1 << 5)
240#define PCAP_LED1_EN (1 << 6)
241#define PCAP_LED0_T_SHIFT 7
242#define PCAP_LED1_T_SHIFT 11
243#define PCAP_LED0_C_SHIFT 15
244#define PCAP_LED1_C_SHIFT 17
245#define PCAP_BL1_SHIFT 20
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300246
247/* RTC */
248#define PCAP_RTC_DAY_MASK 0x3fff
249#define PCAP_RTC_TOD_MASK 0xffff
250#define PCAP_RTC_PC_MASK 0x7
251#define SEC_PER_DAY 86400
252
253#endif