Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | Driver for Philips tda1004xh OFDM Demodulator |
| 3 | |
| 4 | (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20 | |
| 21 | */ |
| 22 | /* |
| 23 | * This driver needs external firmware. Please use the commands |
| 24 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045", |
| 25 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to |
Ville Skytt\รค | 12e66f6 | 2006-01-09 15:25:38 -0200 | [diff] [blame] | 26 | * download/extract them, and then copy them to /usr/lib/hotplug/firmware |
| 27 | * or /lib/firmware (depending on configuration of firmware hotplug). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | */ |
| 29 | #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw" |
| 30 | #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw" |
| 31 | |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <linux/device.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 35 | #include <linux/jiffies.h> |
| 36 | #include <linux/string.h> |
| 37 | #include <linux/slab.h> |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #include "dvb_frontend.h" |
| 40 | #include "tda1004x.h" |
| 41 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | static int debug; |
| 43 | #define dprintk(args...) \ |
| 44 | do { \ |
| 45 | if (debug) printk(KERN_DEBUG "tda1004x: " args); \ |
| 46 | } while (0) |
| 47 | |
| 48 | #define TDA1004X_CHIPID 0x00 |
| 49 | #define TDA1004X_AUTO 0x01 |
| 50 | #define TDA1004X_IN_CONF1 0x02 |
| 51 | #define TDA1004X_IN_CONF2 0x03 |
| 52 | #define TDA1004X_OUT_CONF1 0x04 |
| 53 | #define TDA1004X_OUT_CONF2 0x05 |
| 54 | #define TDA1004X_STATUS_CD 0x06 |
| 55 | #define TDA1004X_CONFC4 0x07 |
| 56 | #define TDA1004X_DSSPARE2 0x0C |
| 57 | #define TDA10045H_CODE_IN 0x0D |
| 58 | #define TDA10045H_FWPAGE 0x0E |
| 59 | #define TDA1004X_SCAN_CPT 0x10 |
| 60 | #define TDA1004X_DSP_CMD 0x11 |
| 61 | #define TDA1004X_DSP_ARG 0x12 |
| 62 | #define TDA1004X_DSP_DATA1 0x13 |
| 63 | #define TDA1004X_DSP_DATA2 0x14 |
| 64 | #define TDA1004X_CONFADC1 0x15 |
| 65 | #define TDA1004X_CONFC1 0x16 |
| 66 | #define TDA10045H_S_AGC 0x1a |
| 67 | #define TDA10046H_AGC_TUN_LEVEL 0x1a |
| 68 | #define TDA1004X_SNR 0x1c |
| 69 | #define TDA1004X_CONF_TS1 0x1e |
| 70 | #define TDA1004X_CONF_TS2 0x1f |
| 71 | #define TDA1004X_CBER_RESET 0x20 |
| 72 | #define TDA1004X_CBER_MSB 0x21 |
| 73 | #define TDA1004X_CBER_LSB 0x22 |
| 74 | #define TDA1004X_CVBER_LUT 0x23 |
| 75 | #define TDA1004X_VBER_MSB 0x24 |
| 76 | #define TDA1004X_VBER_MID 0x25 |
| 77 | #define TDA1004X_VBER_LSB 0x26 |
| 78 | #define TDA1004X_UNCOR 0x27 |
| 79 | |
| 80 | #define TDA10045H_CONFPLL_P 0x2D |
| 81 | #define TDA10045H_CONFPLL_M_MSB 0x2E |
| 82 | #define TDA10045H_CONFPLL_M_LSB 0x2F |
| 83 | #define TDA10045H_CONFPLL_N 0x30 |
| 84 | |
| 85 | #define TDA10046H_CONFPLL1 0x2D |
| 86 | #define TDA10046H_CONFPLL2 0x2F |
| 87 | #define TDA10046H_CONFPLL3 0x30 |
| 88 | #define TDA10046H_TIME_WREF1 0x31 |
| 89 | #define TDA10046H_TIME_WREF2 0x32 |
| 90 | #define TDA10046H_TIME_WREF3 0x33 |
| 91 | #define TDA10046H_TIME_WREF4 0x34 |
| 92 | #define TDA10046H_TIME_WREF5 0x35 |
| 93 | |
| 94 | #define TDA10045H_UNSURW_MSB 0x31 |
| 95 | #define TDA10045H_UNSURW_LSB 0x32 |
| 96 | #define TDA10045H_WREF_MSB 0x33 |
| 97 | #define TDA10045H_WREF_MID 0x34 |
| 98 | #define TDA10045H_WREF_LSB 0x35 |
| 99 | #define TDA10045H_MUXOUT 0x36 |
| 100 | #define TDA1004X_CONFADC2 0x37 |
| 101 | |
| 102 | #define TDA10045H_IOFFSET 0x38 |
| 103 | |
| 104 | #define TDA10046H_CONF_TRISTATE1 0x3B |
| 105 | #define TDA10046H_CONF_TRISTATE2 0x3C |
| 106 | #define TDA10046H_CONF_POLARITY 0x3D |
| 107 | #define TDA10046H_FREQ_OFFSET 0x3E |
| 108 | #define TDA10046H_GPIO_OUT_SEL 0x41 |
| 109 | #define TDA10046H_GPIO_SELECT 0x42 |
| 110 | #define TDA10046H_AGC_CONF 0x43 |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 111 | #define TDA10046H_AGC_THR 0x44 |
| 112 | #define TDA10046H_AGC_RENORM 0x45 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | #define TDA10046H_AGC_GAINS 0x46 |
| 114 | #define TDA10046H_AGC_TUN_MIN 0x47 |
| 115 | #define TDA10046H_AGC_TUN_MAX 0x48 |
| 116 | #define TDA10046H_AGC_IF_MIN 0x49 |
| 117 | #define TDA10046H_AGC_IF_MAX 0x4A |
| 118 | |
| 119 | #define TDA10046H_FREQ_PHY2_MSB 0x4D |
| 120 | #define TDA10046H_FREQ_PHY2_LSB 0x4E |
| 121 | |
| 122 | #define TDA10046H_CVBER_CTRL 0x4F |
| 123 | #define TDA10046H_AGC_IF_LEVEL 0x52 |
| 124 | #define TDA10046H_CODE_CPT 0x57 |
| 125 | #define TDA10046H_CODE_IN 0x58 |
| 126 | |
| 127 | |
| 128 | static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) |
| 129 | { |
| 130 | int ret; |
| 131 | u8 buf[] = { reg, data }; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 132 | struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 134 | dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | |
| 136 | msg.addr = state->config->demod_address; |
| 137 | ret = i2c_transfer(state->i2c, &msg, 1); |
| 138 | |
| 139 | if (ret != 1) |
| 140 | dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n", |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 141 | __func__, reg, data, ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 143 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | reg, data, ret); |
| 145 | return (ret != 1) ? -1 : 0; |
| 146 | } |
| 147 | |
| 148 | static int tda1004x_read_byte(struct tda1004x_state *state, int reg) |
| 149 | { |
| 150 | int ret; |
| 151 | u8 b0[] = { reg }; |
| 152 | u8 b1[] = { 0 }; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 153 | struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 }, |
| 154 | { .flags = I2C_M_RD, .buf = b1, .len = 1 }}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 156 | dprintk("%s: reg=0x%x\n", __func__, reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | |
| 158 | msg[0].addr = state->config->demod_address; |
| 159 | msg[1].addr = state->config->demod_address; |
| 160 | ret = i2c_transfer(state->i2c, msg, 2); |
| 161 | |
| 162 | if (ret != 2) { |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 163 | dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | ret); |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 165 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | } |
| 167 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 168 | dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | reg, b1[0], ret); |
| 170 | return b1[0]; |
| 171 | } |
| 172 | |
| 173 | static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) |
| 174 | { |
| 175 | int val; |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 176 | dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | mask, data); |
| 178 | |
| 179 | // read a byte and check |
| 180 | val = tda1004x_read_byte(state, reg); |
| 181 | if (val < 0) |
| 182 | return val; |
| 183 | |
| 184 | // mask if off |
| 185 | val = val & ~mask; |
| 186 | val |= data & 0xff; |
| 187 | |
| 188 | // write it out again |
| 189 | return tda1004x_write_byteI(state, reg, val); |
| 190 | } |
| 191 | |
| 192 | static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) |
| 193 | { |
| 194 | int i; |
| 195 | int result; |
| 196 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 197 | dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | |
| 199 | result = 0; |
| 200 | for (i = 0; i < len; i++) { |
| 201 | result = tda1004x_write_byteI(state, reg + i, buf[i]); |
| 202 | if (result != 0) |
| 203 | break; |
| 204 | } |
| 205 | |
| 206 | return result; |
| 207 | } |
| 208 | |
| 209 | static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) |
| 210 | { |
| 211 | int result; |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 212 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | |
| 214 | result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 215 | msleep(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | return result; |
| 217 | } |
| 218 | |
| 219 | static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) |
| 220 | { |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 221 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | |
| 223 | return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); |
| 224 | } |
| 225 | |
| 226 | static int tda10045h_set_bandwidth(struct tda1004x_state *state, |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 227 | u32 bandwidth) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | { |
| 229 | static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; |
| 230 | static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; |
| 231 | static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; |
| 232 | |
| 233 | switch (bandwidth) { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 234 | case 6000000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); |
| 236 | break; |
| 237 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 238 | case 7000000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 239 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); |
| 240 | break; |
| 241 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 242 | case 8000000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); |
| 244 | break; |
| 245 | |
| 246 | default: |
| 247 | return -EINVAL; |
| 248 | } |
| 249 | |
| 250 | tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); |
| 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | static int tda10046h_set_bandwidth(struct tda1004x_state *state, |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 256 | u32 bandwidth) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | { |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 258 | static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; |
| 259 | static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; |
| 260 | static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 262 | static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 }; |
| 263 | static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab }; |
| 264 | static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 }; |
| 265 | int tda10046_clk53m; |
| 266 | |
| 267 | if ((state->config->if_freq == TDA10046_FREQ_045) || |
| 268 | (state->config->if_freq == TDA10046_FREQ_052)) |
| 269 | tda10046_clk53m = 0; |
| 270 | else |
| 271 | tda10046_clk53m = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | switch (bandwidth) { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 273 | case 6000000: |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 274 | if (tda10046_clk53m) |
| 275 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 276 | sizeof(bandwidth_6mhz_53M)); |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 277 | else |
| 278 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 279 | sizeof(bandwidth_6mhz_48M)); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 280 | if (state->config->if_freq == TDA10046_FREQ_045) { |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 281 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); |
| 282 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 283 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | break; |
| 285 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 286 | case 7000000: |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 287 | if (tda10046_clk53m) |
| 288 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 289 | sizeof(bandwidth_7mhz_53M)); |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 290 | else |
| 291 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 292 | sizeof(bandwidth_7mhz_48M)); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 293 | if (state->config->if_freq == TDA10046_FREQ_045) { |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 294 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); |
| 295 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 296 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | break; |
| 298 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 299 | case 8000000: |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 300 | if (tda10046_clk53m) |
| 301 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 302 | sizeof(bandwidth_8mhz_53M)); |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 303 | else |
| 304 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, |
Michael Krufky | 50c25ff | 2006-01-09 15:25:34 -0200 | [diff] [blame] | 305 | sizeof(bandwidth_8mhz_48M)); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 306 | if (state->config->if_freq == TDA10046_FREQ_045) { |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 307 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); |
| 308 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 309 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | break; |
| 311 | |
| 312 | default: |
| 313 | return -EINVAL; |
| 314 | } |
| 315 | |
| 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | static int tda1004x_do_upload(struct tda1004x_state *state, |
David Woodhouse | bc17915 | 2008-05-24 00:12:23 +0100 | [diff] [blame] | 320 | const unsigned char *mem, unsigned int len, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | u8 dspCodeCounterReg, u8 dspCodeInReg) |
| 322 | { |
| 323 | u8 buf[65]; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 324 | struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | int tx_size; |
| 326 | int pos = 0; |
| 327 | |
| 328 | /* clear code counter */ |
| 329 | tda1004x_write_byteI(state, dspCodeCounterReg, 0); |
| 330 | fw_msg.addr = state->config->demod_address; |
| 331 | |
Mauro Carvalho Chehab | 347c4e9 | 2012-09-28 16:28:51 -0300 | [diff] [blame] | 332 | i2c_lock_adapter(state->i2c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | buf[0] = dspCodeInReg; |
| 334 | while (pos != len) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | // work out how much to send this time |
| 336 | tx_size = len - pos; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 337 | if (tx_size > 0x10) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 338 | tx_size = 0x10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | |
| 340 | // send the chunk |
| 341 | memcpy(buf + 1, mem + pos, tx_size); |
| 342 | fw_msg.len = tx_size + 1; |
Mauro Carvalho Chehab | 347c4e9 | 2012-09-28 16:28:51 -0300 | [diff] [blame] | 343 | if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) { |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 344 | printk(KERN_ERR "tda1004x: Error during firmware upload\n"); |
Mauro Carvalho Chehab | 347c4e9 | 2012-09-28 16:28:51 -0300 | [diff] [blame] | 345 | i2c_unlock_adapter(state->i2c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | return -EIO; |
| 347 | } |
| 348 | pos += tx_size; |
| 349 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 350 | dprintk("%s: fw_pos=0x%x\n", __func__, pos); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | } |
Mauro Carvalho Chehab | 347c4e9 | 2012-09-28 16:28:51 -0300 | [diff] [blame] | 352 | i2c_unlock_adapter(state->i2c); |
| 353 | |
| 354 | /* give the DSP a chance to settle 03/10/05 Hac */ |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 355 | msleep(100); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 356 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | return 0; |
| 358 | } |
| 359 | |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 360 | static int tda1004x_check_upload_ok(struct tda1004x_state *state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | { |
| 362 | u8 data1, data2; |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 363 | unsigned long timeout; |
| 364 | |
| 365 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { |
| 366 | timeout = jiffies + 2 * HZ; |
| 367 | while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { |
| 368 | if (time_after(jiffies, timeout)) { |
| 369 | printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n"); |
| 370 | break; |
| 371 | } |
| 372 | msleep(1); |
| 373 | } |
| 374 | } else |
| 375 | msleep(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | |
| 377 | // check upload was OK |
| 378 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP |
| 379 | tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); |
| 380 | |
| 381 | data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); |
| 382 | data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); |
Hartmut Hackmann | 3faadbb | 2005-07-07 17:57:42 -0700 | [diff] [blame] | 383 | if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) { |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 384 | printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | return -EIO; |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 386 | } |
| 387 | printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | static int tda10045_fwupload(struct dvb_frontend* fe) |
| 392 | { |
| 393 | struct tda1004x_state* state = fe->demodulator_priv; |
| 394 | int ret; |
| 395 | const struct firmware *fw; |
| 396 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | /* don't re-upload unless necessary */ |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 398 | if (tda1004x_check_upload_ok(state) == 0) |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 399 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | |
| 401 | /* request the firmware, this will block until someone uploads it */ |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 402 | printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); |
| 404 | if (ret) { |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 405 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | return ret; |
| 407 | } |
| 408 | |
| 409 | /* reset chip */ |
| 410 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); |
| 411 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); |
| 412 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); |
| 413 | msleep(10); |
| 414 | |
| 415 | /* set parameters */ |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 416 | tda10045h_set_bandwidth(state, 8000000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | |
| 418 | ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); |
Anssi Hannula | 0c744b0 | 2005-07-07 17:57:42 -0700 | [diff] [blame] | 419 | release_firmware(fw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | if (ret) |
| 421 | return ret; |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 422 | printk(KERN_INFO "tda1004x: firmware upload complete\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | |
| 424 | /* wait for DSP to initialise */ |
| 425 | /* DSPREADY doesn't seem to work on the TDA10045H */ |
| 426 | msleep(100); |
| 427 | |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 428 | return tda1004x_check_upload_ok(state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | } |
| 430 | |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 431 | static void tda10046_init_plls(struct dvb_frontend* fe) |
Johannes Stezenbach | 71e3420 | 2005-05-16 21:54:36 -0700 | [diff] [blame] | 432 | { |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 433 | struct tda1004x_state* state = fe->demodulator_priv; |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 434 | int tda10046_clk53m; |
| 435 | |
| 436 | if ((state->config->if_freq == TDA10046_FREQ_045) || |
| 437 | (state->config->if_freq == TDA10046_FREQ_052)) |
| 438 | tda10046_clk53m = 0; |
| 439 | else |
| 440 | tda10046_clk53m = 1; |
Johannes Stezenbach | 71e3420 | 2005-05-16 21:54:36 -0700 | [diff] [blame] | 441 | |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 442 | tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 443 | if(tda10046_clk53m) { |
| 444 | printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n"); |
| 445 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 |
| 446 | } else { |
| 447 | printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n"); |
| 448 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 |
| 449 | } |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 450 | if (state->config->xtal_freq == TDA10046_XTAL_4M ) { |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 451 | dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__); |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 452 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 |
| 453 | } else { |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 454 | dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__); |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 455 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 |
Johannes Stezenbach | 71e3420 | 2005-05-16 21:54:36 -0700 | [diff] [blame] | 456 | } |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 457 | if(tda10046_clk53m) |
| 458 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); |
| 459 | else |
| 460 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); |
| 461 | /* Note clock frequency is handled implicitly */ |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 462 | switch (state->config->if_freq) { |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 463 | case TDA10046_FREQ_045: |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 464 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); |
| 465 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 466 | break; |
| 467 | case TDA10046_FREQ_052: |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 468 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); |
| 469 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); |
| 470 | break; |
| 471 | case TDA10046_FREQ_3617: |
| 472 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); |
| 473 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); |
| 474 | break; |
| 475 | case TDA10046_FREQ_3613: |
| 476 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); |
| 477 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 478 | break; |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 479 | } |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 480 | tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */ |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 481 | /* let the PLLs settle */ |
| 482 | msleep(120); |
Johannes Stezenbach | 71e3420 | 2005-05-16 21:54:36 -0700 | [diff] [blame] | 483 | } |
| 484 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | static int tda10046_fwupload(struct dvb_frontend* fe) |
| 486 | { |
| 487 | struct tda1004x_state* state = fe->demodulator_priv; |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 488 | int ret, confc4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | const struct firmware *fw; |
| 490 | |
| 491 | /* reset + wake up chip */ |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 492 | if (state->config->xtal_freq == TDA10046_XTAL_4M) { |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 493 | confc4 = 0; |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 494 | } else { |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 495 | dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__); |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 496 | confc4 = 0x80; |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 497 | } |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 498 | tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); |
| 499 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 501 | /* set GPIO 1 and 3 */ |
| 502 | if (state->config->gpio_config != TDA10046_GPTRI) { |
| 503 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); |
| 504 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); |
| 505 | } |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 506 | /* let the clocks recover from sleep */ |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 507 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 509 | /* The PLLs need to be reprogrammed after sleep */ |
| 510 | tda10046_init_plls(fe); |
Hartmut Hackmann | 6871758 | 2007-04-27 12:31:15 -0300 | [diff] [blame] | 511 | tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 512 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | /* don't re-upload unless necessary */ |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 514 | if (tda1004x_check_upload_ok(state) == 0) |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 515 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 517 | /* |
| 518 | For i2c normal work, we need to slow down the bus speed. |
| 519 | However, the slow down breaks the eeprom firmware load. |
| 520 | So, use normal speed for eeprom booting and then restore the |
| 521 | i2c speed after that. Tested with MSI TV @nyware A/D board, |
| 522 | that comes with firmware version 29 inside their eeprom. |
| 523 | |
| 524 | It should also be noticed that no other I2C transfer should |
| 525 | be in course while booting from eeprom, otherwise, tda10046 |
| 526 | goes into an instable state. So, proper locking are needed |
| 527 | at the i2c bus master. |
| 528 | */ |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 529 | printk(KERN_INFO "tda1004x: trying to boot from eeprom\n"); |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 530 | tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 531 | msleep(300); |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 532 | tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); |
| 533 | |
| 534 | /* Checks if eeprom firmware went without troubles */ |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 535 | if (tda1004x_check_upload_ok(state) == 0) |
| 536 | return 0; |
| 537 | |
Mauro Carvalho Chehab | 517efa8 | 2009-02-09 13:12:41 -0300 | [diff] [blame] | 538 | /* eeprom firmware didn't work. Load one manually. */ |
| 539 | |
Hartmut Hackmann | f4546e7 | 2007-04-27 12:31:13 -0300 | [diff] [blame] | 540 | if (state->config->request_firmware != NULL) { |
| 541 | /* request the firmware, this will block until someone uploads it */ |
| 542 | printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); |
| 543 | ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 544 | if (ret) { |
Hartmut Hackmann | f4546e7 | 2007-04-27 12:31:13 -0300 | [diff] [blame] | 545 | /* remain compatible to old bug: try to load with tda10045 image name */ |
| 546 | ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); |
| 547 | if (ret) { |
| 548 | printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); |
| 549 | return ret; |
| 550 | } else { |
| 551 | printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n", |
| 552 | TDA10046_DEFAULT_FIRMWARE); |
| 553 | } |
| 554 | } |
| 555 | } else { |
| 556 | printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n"); |
| 557 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | } |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 559 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST |
| 560 | ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); |
| 561 | release_firmware(fw); |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 562 | return tda1004x_check_upload_ok(state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | } |
| 564 | |
| 565 | static int tda1004x_encode_fec(int fec) |
| 566 | { |
| 567 | // convert known FEC values |
| 568 | switch (fec) { |
| 569 | case FEC_1_2: |
| 570 | return 0; |
| 571 | case FEC_2_3: |
| 572 | return 1; |
| 573 | case FEC_3_4: |
| 574 | return 2; |
| 575 | case FEC_5_6: |
| 576 | return 3; |
| 577 | case FEC_7_8: |
| 578 | return 4; |
| 579 | } |
| 580 | |
| 581 | // unsupported |
| 582 | return -EINVAL; |
| 583 | } |
| 584 | |
| 585 | static int tda1004x_decode_fec(int tdafec) |
| 586 | { |
| 587 | // convert known FEC values |
| 588 | switch (tdafec) { |
| 589 | case 0: |
| 590 | return FEC_1_2; |
| 591 | case 1: |
| 592 | return FEC_2_3; |
| 593 | case 2: |
| 594 | return FEC_3_4; |
| 595 | case 3: |
| 596 | return FEC_5_6; |
| 597 | case 4: |
| 598 | return FEC_7_8; |
| 599 | } |
| 600 | |
| 601 | // unsupported |
| 602 | return -1; |
| 603 | } |
| 604 | |
lawrence rust | 2e4e98e | 2010-08-25 09:50:20 -0300 | [diff] [blame] | 605 | static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | { |
| 607 | struct tda1004x_state* state = fe->demodulator_priv; |
| 608 | |
Andrew de Quincey | c10d14d | 2006-08-08 09:10:08 -0300 | [diff] [blame] | 609 | if (len != 2) |
| 610 | return -EINVAL; |
| 611 | |
| 612 | return tda1004x_write_byteI(state, buf[0], buf[1]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | static int tda10045_init(struct dvb_frontend* fe) |
| 616 | { |
| 617 | struct tda1004x_state* state = fe->demodulator_priv; |
| 618 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 619 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | if (tda10045_fwupload(fe)) { |
| 622 | printk("tda1004x: firmware upload failed\n"); |
| 623 | return -EIO; |
| 624 | } |
| 625 | |
| 626 | tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC |
| 627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | // tda setup |
| 629 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer |
| 630 | tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream |
| 631 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal |
| 632 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer |
| 633 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset |
| 634 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset |
| 635 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface |
| 636 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface |
| 637 | tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits |
| 638 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity |
| 639 | tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); |
| 640 | |
| 641 | tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); |
| 642 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | static int tda10046_init(struct dvb_frontend* fe) |
| 647 | { |
| 648 | struct tda1004x_state* state = fe->demodulator_priv; |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 649 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | if (tda10046_fwupload(fe)) { |
| 652 | printk("tda1004x: firmware upload failed\n"); |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 653 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | } |
| 655 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 656 | // tda setup |
| 657 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 658 | tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 659 | tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 660 | |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 661 | switch (state->config->agc_config) { |
| 662 | case TDA10046_AGC_DEFAULT: |
| 663 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 664 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 665 | break; |
| 666 | case TDA10046_AGC_IFO_AUTO_NEG: |
| 667 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 668 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 669 | break; |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 670 | case TDA10046_AGC_IFO_AUTO_POS: |
| 671 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 672 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 673 | break; |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 674 | case TDA10046_AGC_TDA827X: |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 675 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup |
| 676 | tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 677 | tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 678 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities |
Hartmut Hackmann | 550a9a5 | 2006-11-15 21:31:54 -0300 | [diff] [blame] | 679 | break; |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 680 | } |
Hartmut Hackmann | 08cdf94 | 2007-03-18 19:23:20 -0300 | [diff] [blame] | 681 | if (state->config->ts_mode == 0) { |
| 682 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); |
| 683 | tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); |
| 684 | } else { |
| 685 | tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); |
| 686 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, |
| 687 | state->config->invert_oclk << 4); |
| 688 | } |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 689 | tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); |
Hartmut Hackmann | 08cdf94 | 2007-03-18 19:23:20 -0300 | [diff] [blame] | 690 | tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } |
| 692 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values |
| 693 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } |
| 694 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 695 | tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 696 | tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 698 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 699 | // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes |
Hartmut Hackmann | ecb60de | 2005-07-07 17:57:40 -0700 | [diff] [blame] | 700 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 701 | return 0; |
| 702 | } |
| 703 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 704 | static int tda1004x_set_fe(struct dvb_frontend *fe) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 706 | struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 707 | struct tda1004x_state* state = fe->demodulator_priv; |
| 708 | int tmp; |
| 709 | int inversion; |
| 710 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 711 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 712 | |
| 713 | if (state->demod_type == TDA1004X_DEMOD_TDA10046) { |
| 714 | // setup auto offset |
| 715 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); |
| 716 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); |
| 717 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); |
| 718 | |
| 719 | // disable agc_conf[2] |
| 720 | tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); |
| 721 | } |
| 722 | |
| 723 | // set frequency |
Patrick Boettcher | dea7486 | 2006-05-14 05:01:31 -0300 | [diff] [blame] | 724 | if (fe->ops.tuner_ops.set_params) { |
Mauro Carvalho Chehab | 14d24d1 | 2011-12-24 12:24:33 -0300 | [diff] [blame] | 725 | fe->ops.tuner_ops.set_params(fe); |
Hartmut Hackmann | ede2200 | 2007-04-27 12:31:32 -0300 | [diff] [blame] | 726 | if (fe->ops.i2c_gate_ctrl) |
| 727 | fe->ops.i2c_gate_ctrl(fe, 0); |
Hartmut Hackmann | 634623d | 2005-11-08 21:35:13 -0800 | [diff] [blame] | 728 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | // Hardcoded to use auto as much as possible on the TDA10045 as it |
| 731 | // is very unreliable if AUTO mode is _not_ used. |
| 732 | if (state->demod_type == TDA1004X_DEMOD_TDA10045) { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 733 | fe_params->code_rate_HP = FEC_AUTO; |
| 734 | fe_params->guard_interval = GUARD_INTERVAL_AUTO; |
| 735 | fe_params->transmission_mode = TRANSMISSION_MODE_AUTO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | } |
| 737 | |
| 738 | // Set standard params.. or put them to auto |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 739 | if ((fe_params->code_rate_HP == FEC_AUTO) || |
| 740 | (fe_params->code_rate_LP == FEC_AUTO) || |
| 741 | (fe_params->modulation == QAM_AUTO) || |
| 742 | (fe_params->hierarchy == HIERARCHY_AUTO)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 743 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 744 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits |
| 746 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits |
| 747 | } else { |
| 748 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto |
| 749 | |
| 750 | // set HP FEC |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 751 | tmp = tda1004x_encode_fec(fe_params->code_rate_HP); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 752 | if (tmp < 0) |
| 753 | return tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); |
| 755 | |
| 756 | // set LP FEC |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 757 | tmp = tda1004x_encode_fec(fe_params->code_rate_LP); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 758 | if (tmp < 0) |
| 759 | return tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); |
| 761 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 762 | /* set modulation */ |
| 763 | switch (fe_params->modulation) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | case QPSK: |
| 765 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); |
| 766 | break; |
| 767 | |
| 768 | case QAM_16: |
| 769 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); |
| 770 | break; |
| 771 | |
| 772 | case QAM_64: |
| 773 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); |
| 774 | break; |
| 775 | |
| 776 | default: |
| 777 | return -EINVAL; |
| 778 | } |
| 779 | |
| 780 | // set hierarchy |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 781 | switch (fe_params->hierarchy) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | case HIERARCHY_NONE: |
| 783 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); |
| 784 | break; |
| 785 | |
| 786 | case HIERARCHY_1: |
| 787 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); |
| 788 | break; |
| 789 | |
| 790 | case HIERARCHY_2: |
| 791 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); |
| 792 | break; |
| 793 | |
| 794 | case HIERARCHY_4: |
| 795 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); |
| 796 | break; |
| 797 | |
| 798 | default: |
| 799 | return -EINVAL; |
| 800 | } |
| 801 | } |
| 802 | |
| 803 | // set bandwidth |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 804 | switch (state->demod_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | case TDA1004X_DEMOD_TDA10045: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 806 | tda10045h_set_bandwidth(state, fe_params->bandwidth_hz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | break; |
| 808 | |
| 809 | case TDA1004X_DEMOD_TDA10046: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 810 | tda10046h_set_bandwidth(state, fe_params->bandwidth_hz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | break; |
| 812 | } |
| 813 | |
| 814 | // set inversion |
| 815 | inversion = fe_params->inversion; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 816 | if (state->config->invert) |
| 817 | inversion = inversion ? INVERSION_OFF : INVERSION_ON; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 818 | switch (inversion) { |
| 819 | case INVERSION_OFF: |
| 820 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); |
| 821 | break; |
| 822 | |
| 823 | case INVERSION_ON: |
| 824 | tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); |
| 825 | break; |
| 826 | |
| 827 | default: |
| 828 | return -EINVAL; |
| 829 | } |
| 830 | |
| 831 | // set guard interval |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 832 | switch (fe_params->guard_interval) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | case GUARD_INTERVAL_1_32: |
| 834 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); |
| 835 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); |
| 836 | break; |
| 837 | |
| 838 | case GUARD_INTERVAL_1_16: |
| 839 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); |
| 840 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); |
| 841 | break; |
| 842 | |
| 843 | case GUARD_INTERVAL_1_8: |
| 844 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); |
| 845 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); |
| 846 | break; |
| 847 | |
| 848 | case GUARD_INTERVAL_1_4: |
| 849 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); |
| 850 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); |
| 851 | break; |
| 852 | |
| 853 | case GUARD_INTERVAL_AUTO: |
| 854 | tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); |
| 855 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); |
| 856 | break; |
| 857 | |
| 858 | default: |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | |
| 862 | // set transmission mode |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 863 | switch (fe_params->transmission_mode) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | case TRANSMISSION_MODE_2K: |
| 865 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); |
| 866 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); |
| 867 | break; |
| 868 | |
| 869 | case TRANSMISSION_MODE_8K: |
| 870 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); |
| 871 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); |
| 872 | break; |
| 873 | |
| 874 | case TRANSMISSION_MODE_AUTO: |
| 875 | tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); |
| 876 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); |
| 877 | break; |
| 878 | |
| 879 | default: |
| 880 | return -EINVAL; |
| 881 | } |
| 882 | |
| 883 | // start the lock |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 884 | switch (state->demod_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 885 | case TDA1004X_DEMOD_TDA10045: |
| 886 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); |
| 887 | tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | break; |
| 889 | |
| 890 | case TDA1004X_DEMOD_TDA10046: |
| 891 | tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); |
Hartmut Hackmann | 634623d | 2005-11-08 21:35:13 -0800 | [diff] [blame] | 892 | msleep(1); |
| 893 | tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | break; |
| 895 | } |
| 896 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 897 | msleep(10); |
| 898 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | return 0; |
| 900 | } |
| 901 | |
Mauro Carvalho Chehab | 7c61d80 | 2011-12-30 11:30:21 -0300 | [diff] [blame] | 902 | static int tda1004x_get_fe(struct dvb_frontend *fe) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | { |
Mauro Carvalho Chehab | 7c61d80 | 2011-12-30 11:30:21 -0300 | [diff] [blame] | 904 | struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | struct tda1004x_state* state = fe->demodulator_priv; |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 906 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 907 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 908 | |
| 909 | // inversion status |
| 910 | fe_params->inversion = INVERSION_OFF; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 911 | if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 912 | fe_params->inversion = INVERSION_ON; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 913 | if (state->config->invert) |
| 914 | fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | |
| 916 | // bandwidth |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 917 | switch (state->demod_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 918 | case TDA1004X_DEMOD_TDA10045: |
| 919 | switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { |
| 920 | case 0x14: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 921 | fe_params->bandwidth_hz = 8000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | break; |
| 923 | case 0xdb: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 924 | fe_params->bandwidth_hz = 7000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | break; |
| 926 | case 0x4f: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 927 | fe_params->bandwidth_hz = 6000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 928 | break; |
| 929 | } |
| 930 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | case TDA1004X_DEMOD_TDA10046: |
| 932 | switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 933 | case 0x5c: |
| 934 | case 0x54: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 935 | fe_params->bandwidth_hz = 8000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 936 | break; |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 937 | case 0x6a: |
| 938 | case 0x60: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 939 | fe_params->bandwidth_hz = 7000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 940 | break; |
Hartmut Hackmann | 8a8e9c2 | 2006-01-09 15:25:04 -0200 | [diff] [blame] | 941 | case 0x7b: |
| 942 | case 0x70: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 943 | fe_params->bandwidth_hz = 6000000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 944 | break; |
| 945 | } |
| 946 | break; |
| 947 | } |
| 948 | |
| 949 | // FEC |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 950 | fe_params->code_rate_HP = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 952 | fe_params->code_rate_LP = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); |
| 954 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 955 | /* modulation */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { |
| 957 | case 0: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 958 | fe_params->modulation = QPSK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 959 | break; |
| 960 | case 1: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 961 | fe_params->modulation = QAM_16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | break; |
| 963 | case 2: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 964 | fe_params->modulation = QAM_64; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | break; |
| 966 | } |
| 967 | |
| 968 | // transmission mode |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 969 | fe_params->transmission_mode = TRANSMISSION_MODE_2K; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 970 | if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 971 | fe_params->transmission_mode = TRANSMISSION_MODE_8K; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 972 | |
| 973 | // guard interval |
| 974 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { |
| 975 | case 0: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 976 | fe_params->guard_interval = GUARD_INTERVAL_1_32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | break; |
| 978 | case 1: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 979 | fe_params->guard_interval = GUARD_INTERVAL_1_16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | break; |
| 981 | case 2: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 982 | fe_params->guard_interval = GUARD_INTERVAL_1_8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | break; |
| 984 | case 3: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 985 | fe_params->guard_interval = GUARD_INTERVAL_1_4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | break; |
| 987 | } |
| 988 | |
| 989 | // hierarchy |
| 990 | switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { |
| 991 | case 0: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 992 | fe_params->hierarchy = HIERARCHY_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 993 | break; |
| 994 | case 1: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 995 | fe_params->hierarchy = HIERARCHY_1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | break; |
| 997 | case 2: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 998 | fe_params->hierarchy = HIERARCHY_2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 999 | break; |
| 1000 | case 3: |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 1001 | fe_params->hierarchy = HIERARCHY_4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | break; |
| 1003 | } |
| 1004 | |
| 1005 | return 0; |
| 1006 | } |
| 1007 | |
| 1008 | static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status) |
| 1009 | { |
| 1010 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1011 | int status; |
| 1012 | int cber; |
| 1013 | int vber; |
| 1014 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1015 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | |
| 1017 | // read status |
| 1018 | status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1019 | if (status == -1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1020 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1021 | |
| 1022 | // decode |
| 1023 | *fe_status = 0; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1024 | if (status & 4) |
| 1025 | *fe_status |= FE_HAS_SIGNAL; |
| 1026 | if (status & 2) |
| 1027 | *fe_status |= FE_HAS_CARRIER; |
| 1028 | if (status & 8) |
| 1029 | *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1030 | |
| 1031 | // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi |
| 1032 | // is getting anything valid |
| 1033 | if (!(*fe_status & FE_HAS_VITERBI)) { |
| 1034 | // read the CBER |
| 1035 | cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1036 | if (cber == -1) |
| 1037 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1038 | status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1039 | if (status == -1) |
| 1040 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1041 | cber |= (status << 8); |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 1042 | // The address 0x20 should be read to cope with a TDA10046 bug |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); |
| 1044 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1045 | if (cber != 65535) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1046 | *fe_status |= FE_HAS_VITERBI; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | // if we DO have some valid VITERBI output, but don't already have SYNC |
| 1050 | // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid. |
| 1051 | if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) { |
| 1052 | // read the VBER |
| 1053 | vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1054 | if (vber == -1) |
| 1055 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | status = tda1004x_read_byte(state, TDA1004X_VBER_MID); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1057 | if (status == -1) |
| 1058 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | vber |= (status << 8); |
| 1060 | status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1061 | if (status == -1) |
| 1062 | return -EIO; |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 1063 | vber |= (status & 0x0f) << 16; |
| 1064 | // The CVBER_LUT should be read to cope with TDA10046 hardware bug |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1065 | tda1004x_read_byte(state, TDA1004X_CVBER_LUT); |
| 1066 | |
| 1067 | // if RS has passed some valid TS packets, then we must be |
| 1068 | // getting some SYNC bytes |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1069 | if (vber < 16632) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | *fe_status |= FE_HAS_SYNC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | // success |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1074 | dprintk("%s: fe_status=0x%x\n", __func__, *fe_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal) |
| 1079 | { |
| 1080 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1081 | int tmp; |
| 1082 | int reg = 0; |
| 1083 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1084 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | |
| 1086 | // determine the register to use |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1087 | switch (state->demod_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | case TDA1004X_DEMOD_TDA10045: |
| 1089 | reg = TDA10045H_S_AGC; |
| 1090 | break; |
| 1091 | |
| 1092 | case TDA1004X_DEMOD_TDA10046: |
| 1093 | reg = TDA10046H_AGC_IF_LEVEL; |
| 1094 | break; |
| 1095 | } |
| 1096 | |
| 1097 | // read it |
| 1098 | tmp = tda1004x_read_byte(state, reg); |
| 1099 | if (tmp < 0) |
| 1100 | return -EIO; |
| 1101 | |
| 1102 | *signal = (tmp << 8) | tmp; |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1103 | dprintk("%s: signal=0x%x\n", __func__, *signal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1104 | return 0; |
| 1105 | } |
| 1106 | |
| 1107 | static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr) |
| 1108 | { |
| 1109 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1110 | int tmp; |
| 1111 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1112 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | |
| 1114 | // read it |
| 1115 | tmp = tda1004x_read_byte(state, TDA1004X_SNR); |
| 1116 | if (tmp < 0) |
| 1117 | return -EIO; |
Andrew de Quincey | c2026b3 | 2005-09-09 13:02:33 -0700 | [diff] [blame] | 1118 | tmp = 255 - tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | |
| 1120 | *snr = ((tmp << 8) | tmp); |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1121 | dprintk("%s: snr=0x%x\n", __func__, *snr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1122 | return 0; |
| 1123 | } |
| 1124 | |
| 1125 | static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
| 1126 | { |
| 1127 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1128 | int tmp; |
| 1129 | int tmp2; |
| 1130 | int counter; |
| 1131 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1132 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1133 | |
| 1134 | // read the UCBLOCKS and reset |
| 1135 | counter = 0; |
| 1136 | tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); |
| 1137 | if (tmp < 0) |
| 1138 | return -EIO; |
| 1139 | tmp &= 0x7f; |
| 1140 | while (counter++ < 5) { |
| 1141 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); |
| 1142 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); |
| 1143 | tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); |
| 1144 | |
| 1145 | tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); |
| 1146 | if (tmp2 < 0) |
| 1147 | return -EIO; |
| 1148 | tmp2 &= 0x7f; |
| 1149 | if ((tmp2 < tmp) || (tmp2 == 0)) |
| 1150 | break; |
| 1151 | } |
| 1152 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1153 | if (tmp != 0x7f) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1154 | *ucblocks = tmp; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1155 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | *ucblocks = 0xffffffff; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1157 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1158 | dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | return 0; |
| 1160 | } |
| 1161 | |
| 1162 | static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber) |
| 1163 | { |
| 1164 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1165 | int tmp; |
| 1166 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1167 | dprintk("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
| 1169 | // read it in |
| 1170 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1171 | if (tmp < 0) |
| 1172 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1173 | *ber = tmp << 1; |
| 1174 | tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1175 | if (tmp < 0) |
| 1176 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | *ber |= (tmp << 9); |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 1178 | // The address 0x20 should be read to cope with a TDA10046 bug |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | tda1004x_read_byte(state, TDA1004X_CBER_RESET); |
| 1180 | |
Harvey Harrison | 271ddbf | 2008-04-08 23:20:00 -0300 | [diff] [blame] | 1181 | dprintk("%s: ber=0x%x\n", __func__, *ber); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1182 | return 0; |
| 1183 | } |
| 1184 | |
| 1185 | static int tda1004x_sleep(struct dvb_frontend* fe) |
| 1186 | { |
| 1187 | struct tda1004x_state* state = fe->demodulator_priv; |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 1188 | int gpio_conf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1189 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1190 | switch (state->demod_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1191 | case TDA1004X_DEMOD_TDA10045: |
| 1192 | tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); |
| 1193 | break; |
| 1194 | |
| 1195 | case TDA1004X_DEMOD_TDA10046: |
Hartmut Hackmann | 0eb3de2 | 2006-02-07 06:49:10 -0200 | [diff] [blame] | 1196 | /* set outputs to tristate */ |
| 1197 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); |
Hartmut Hackmann | 1bb0e86 | 2007-04-27 12:31:10 -0300 | [diff] [blame] | 1198 | /* invert GPIO 1 and 3 if desired*/ |
| 1199 | gpio_conf = state->config->gpio_config; |
| 1200 | if (gpio_conf >= TDA10046_GP00_I) |
| 1201 | tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, |
| 1202 | (gpio_conf & 0x0f) ^ 0x0a); |
| 1203 | |
Hartmut Hackmann | 6871758 | 2007-04-27 12:31:15 -0300 | [diff] [blame] | 1204 | tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 1205 | tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | break; |
| 1207 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | |
| 1209 | return 0; |
| 1210 | } |
| 1211 | |
Andrew de Quincey | 74349bef | 2006-04-18 17:47:10 -0300 | [diff] [blame] | 1212 | static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
| 1213 | { |
| 1214 | struct tda1004x_state* state = fe->demodulator_priv; |
| 1215 | |
| 1216 | if (enable) { |
| 1217 | return tda1004x_enable_tuner_i2c(state); |
| 1218 | } else { |
| 1219 | return tda1004x_disable_tuner_i2c(state); |
| 1220 | } |
| 1221 | } |
| 1222 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1223 | static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) |
| 1224 | { |
| 1225 | fesettings->min_delay_ms = 800; |
Hartmut Hackmann | f03cbea | 2005-07-07 17:57:43 -0700 | [diff] [blame] | 1226 | /* Drift compensation makes no sense for DVB-T */ |
| 1227 | fesettings->step_size = 0; |
| 1228 | fesettings->max_drift = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | return 0; |
| 1230 | } |
| 1231 | |
Andrew de Quincey | 2a514de | 2006-08-08 09:10:09 -0300 | [diff] [blame] | 1232 | static void tda1004x_release(struct dvb_frontend* fe) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1233 | { |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1234 | struct tda1004x_state *state = fe->demodulator_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | kfree(state); |
| 1236 | } |
| 1237 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1238 | static struct dvb_frontend_ops tda10045_ops = { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 1239 | .delsys = { SYS_DVBT }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | .info = { |
| 1241 | .name = "Philips TDA10045H DVB-T", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1242 | .frequency_min = 51000000, |
| 1243 | .frequency_max = 858000000, |
| 1244 | .frequency_stepsize = 166667, |
| 1245 | .caps = |
| 1246 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 1247 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
| 1248 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
| 1249 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
| 1250 | }, |
| 1251 | |
Andrew de Quincey | 2a514de | 2006-08-08 09:10:09 -0300 | [diff] [blame] | 1252 | .release = tda1004x_release, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1253 | |
| 1254 | .init = tda10045_init, |
| 1255 | .sleep = tda1004x_sleep, |
Andrew de Quincey | c10d14d | 2006-08-08 09:10:08 -0300 | [diff] [blame] | 1256 | .write = tda1004x_write, |
Andrew de Quincey | 74349bef | 2006-04-18 17:47:10 -0300 | [diff] [blame] | 1257 | .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 1259 | .set_frontend = tda1004x_set_fe, |
| 1260 | .get_frontend = tda1004x_get_fe, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | .get_tune_settings = tda1004x_get_tune_settings, |
| 1262 | |
| 1263 | .read_status = tda1004x_read_status, |
| 1264 | .read_ber = tda1004x_read_ber, |
| 1265 | .read_signal_strength = tda1004x_read_signal_strength, |
| 1266 | .read_snr = tda1004x_read_snr, |
| 1267 | .read_ucblocks = tda1004x_read_ucblocks, |
| 1268 | }; |
| 1269 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1270 | struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, |
| 1271 | struct i2c_adapter* i2c) |
| 1272 | { |
| 1273 | struct tda1004x_state *state; |
Mauro Carvalho Chehab | 0e7830b | 2008-06-14 11:27:34 -0300 | [diff] [blame] | 1274 | int id; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1275 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1276 | /* allocate memory for the internal state */ |
Matthias Schwarzott | 084e24a | 2009-08-10 22:51:01 -0300 | [diff] [blame] | 1277 | state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1278 | if (!state) { |
Masanari Iida | 546c973 | 2012-02-03 09:56:59 -0300 | [diff] [blame] | 1279 | printk(KERN_ERR "Can't allocate memory for tda10045 state\n"); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1280 | return NULL; |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1281 | } |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1282 | |
| 1283 | /* setup the state */ |
| 1284 | state->config = config; |
| 1285 | state->i2c = i2c; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1286 | state->demod_type = TDA1004X_DEMOD_TDA10045; |
| 1287 | |
| 1288 | /* check if the demod is there */ |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1289 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
Mauro Carvalho Chehab | 0e7830b | 2008-06-14 11:27:34 -0300 | [diff] [blame] | 1290 | if (id < 0) { |
| 1291 | printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n"); |
| 1292 | kfree(state); |
| 1293 | return NULL; |
| 1294 | } |
| 1295 | |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1296 | if (id != 0x25) { |
| 1297 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1298 | kfree(state); |
| 1299 | return NULL; |
| 1300 | } |
| 1301 | |
| 1302 | /* create dvb_frontend */ |
Patrick Boettcher | dea7486 | 2006-05-14 05:01:31 -0300 | [diff] [blame] | 1303 | memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1304 | state->frontend.demodulator_priv = state; |
| 1305 | return &state->frontend; |
| 1306 | } |
| 1307 | |
| 1308 | static struct dvb_frontend_ops tda10046_ops = { |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 1309 | .delsys = { SYS_DVBT }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1310 | .info = { |
| 1311 | .name = "Philips TDA10046H DVB-T", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1312 | .frequency_min = 51000000, |
| 1313 | .frequency_max = 858000000, |
| 1314 | .frequency_stepsize = 166667, |
| 1315 | .caps = |
| 1316 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 1317 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
| 1318 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
| 1319 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
| 1320 | }, |
| 1321 | |
Andrew de Quincey | 2a514de | 2006-08-08 09:10:09 -0300 | [diff] [blame] | 1322 | .release = tda1004x_release, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1323 | |
| 1324 | .init = tda10046_init, |
| 1325 | .sleep = tda1004x_sleep, |
Andrew de Quincey | c10d14d | 2006-08-08 09:10:08 -0300 | [diff] [blame] | 1326 | .write = tda1004x_write, |
Andrew de Quincey | 159f8a6 | 2006-04-19 18:31:03 -0300 | [diff] [blame] | 1327 | .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1328 | |
Mauro Carvalho Chehab | 5f82e6b | 2011-12-26 13:19:48 -0300 | [diff] [blame] | 1329 | .set_frontend = tda1004x_set_fe, |
| 1330 | .get_frontend = tda1004x_get_fe, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1331 | .get_tune_settings = tda1004x_get_tune_settings, |
| 1332 | |
| 1333 | .read_status = tda1004x_read_status, |
| 1334 | .read_ber = tda1004x_read_ber, |
| 1335 | .read_signal_strength = tda1004x_read_signal_strength, |
| 1336 | .read_snr = tda1004x_read_snr, |
| 1337 | .read_ucblocks = tda1004x_read_ucblocks, |
| 1338 | }; |
| 1339 | |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1340 | struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, |
| 1341 | struct i2c_adapter* i2c) |
| 1342 | { |
| 1343 | struct tda1004x_state *state; |
Mauro Carvalho Chehab | 0e7830b | 2008-06-14 11:27:34 -0300 | [diff] [blame] | 1344 | int id; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1345 | |
| 1346 | /* allocate memory for the internal state */ |
Matthias Schwarzott | 084e24a | 2009-08-10 22:51:01 -0300 | [diff] [blame] | 1347 | state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1348 | if (!state) { |
Masanari Iida | 546c973 | 2012-02-03 09:56:59 -0300 | [diff] [blame] | 1349 | printk(KERN_ERR "Can't allocate memory for tda10046 state\n"); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1350 | return NULL; |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1351 | } |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1352 | |
| 1353 | /* setup the state */ |
| 1354 | state->config = config; |
| 1355 | state->i2c = i2c; |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1356 | state->demod_type = TDA1004X_DEMOD_TDA10046; |
| 1357 | |
| 1358 | /* check if the demod is there */ |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1359 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
Mauro Carvalho Chehab | 0e7830b | 2008-06-14 11:27:34 -0300 | [diff] [blame] | 1360 | if (id < 0) { |
| 1361 | printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n"); |
| 1362 | kfree(state); |
| 1363 | return NULL; |
| 1364 | } |
Mauro Carvalho Chehab | bc36ec7 | 2008-06-14 10:44:04 -0300 | [diff] [blame] | 1365 | if (id != 0x46) { |
| 1366 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1367 | kfree(state); |
| 1368 | return NULL; |
| 1369 | } |
| 1370 | |
| 1371 | /* create dvb_frontend */ |
Patrick Boettcher | dea7486 | 2006-05-14 05:01:31 -0300 | [diff] [blame] | 1372 | memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); |
Johannes Stezenbach | 7f5e02d | 2005-05-16 21:54:30 -0700 | [diff] [blame] | 1373 | state->frontend.demodulator_priv = state; |
| 1374 | return &state->frontend; |
| 1375 | } |
| 1376 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1377 | module_param(debug, int, 0644); |
| 1378 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); |
| 1379 | |
| 1380 | MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); |
| 1381 | MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); |
| 1382 | MODULE_LICENSE("GPL"); |
| 1383 | |
| 1384 | EXPORT_SYMBOL(tda10045_attach); |
| 1385 | EXPORT_SYMBOL(tda10046_attach); |