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Dmitry Baryshkovf024ff12008-06-27 10:37:57 +01001#ifndef MFD_TMIO_H
2#define MFD_TMIO_H
3
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +01004#include <linux/device.h>
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -07005#include <linux/fb.h>
Ian Molton64e88672010-01-06 13:51:48 +01006#include <linux/io.h>
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +01007#include <linux/jiffies.h>
Ian Molton64e88672010-01-06 13:51:48 +01008#include <linux/platform_device.h>
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +00009#include <linux/pm_runtime.h>
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -070010
Ian Moltond3a2f712008-07-31 20:44:28 +020011#define tmio_ioread8(addr) readb(addr)
12#define tmio_ioread16(addr) readw(addr)
13#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
14#define tmio_ioread32(addr) \
15 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
16
17#define tmio_iowrite8(val, addr) writeb((val), (addr))
18#define tmio_iowrite16(val, addr) writew((val), (addr))
19#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
20#define tmio_iowrite32(val, addr) \
21 do { \
22 writew((val), (addr)); \
23 writew((val) >> 16, (addr) + 2); \
24 } while (0)
25
Ian Molton64e88672010-01-06 13:51:48 +010026#define CNF_CMD 0x04
27#define CNF_CTL_BASE 0x10
28#define CNF_INT_PIN 0x3d
29#define CNF_STOP_CLK_CTL 0x40
30#define CNF_GCLK_CTL 0x41
31#define CNF_SD_CLK_MODE 0x42
32#define CNF_PIN_STATUS 0x44
33#define CNF_PWR_CTL_1 0x48
34#define CNF_PWR_CTL_2 0x49
35#define CNF_PWR_CTL_3 0x4a
36#define CNF_CARD_DETECT_MODE 0x4c
37#define CNF_SD_SLOT 0x50
38#define CNF_EXT_GCLK_CTL_1 0xf0
39#define CNF_EXT_GCLK_CTL_2 0xf1
40#define CNF_EXT_GCLK_CTL_3 0xf9
41#define CNF_SD_LED_EN_1 0xfa
42#define CNF_SD_LED_EN_2 0xfe
43
44#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
45
46#define sd_config_write8(base, shift, reg, val) \
47 tmio_iowrite8((val), (base) + ((reg) << (shift)))
48#define sd_config_write16(base, shift, reg, val) \
49 tmio_iowrite16((val), (base) + ((reg) << (shift)))
50#define sd_config_write32(base, shift, reg, val) \
51 do { \
52 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
53 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
54 } while (0)
55
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000056/* tmio MMC platform flags */
57#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
Yusuke Godaf1334fb2010-08-30 11:50:19 +010058/*
59 * Some controllers can support a 2-byte block size when the bus width
60 * is configured in 4-bit mode.
61 */
62#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
Arnd Hannemann845ecd22010-12-28 23:22:31 +010063/*
64 * Some controllers can support SDIO IRQ signalling.
65 */
66#define TMIO_MMC_SDIO_IRQ (1 << 2)
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +000067/*
Simon Horman973ed3a2011-06-21 08:00:10 +090068 * Some controllers require waiting for the SD bus to become
69 * idle before writing to some registers.
70 */
71#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +010072/*
73 * A GPIO is used for card hotplug detection. We need an extra flag for this,
74 * because 0 is a valid GPIO number too, and requiring users to specify
75 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
76 */
77#define TMIO_MMC_USE_GPIO_CD (1 << 5)
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000078
Kuninori Morimoto5d60e502013-11-20 00:31:06 -080079/*
80 * Some controllers doesn't have over 0x100 register.
81 * it is used to checking accessibility of
82 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
83 */
84#define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
85
Ian Molton64e88672010-01-06 13:51:48 +010086int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
87int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
88void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
89void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
90
Guennadi Liakhovetski03a06752013-04-26 17:47:17 +020091struct dma_chan;
92
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +000093struct tmio_mmc_dma {
94 void *chan_priv_tx;
95 void *chan_priv_rx;
Guennadi Liakhovetskieec95ee2013-04-26 17:47:18 +020096 int slave_id_tx;
97 int slave_id_rx;
Guennadi Liakhovetski93173052010-12-22 12:02:15 +010098 int alignment_shift;
Guennadi Liakhovetski03a06752013-04-26 17:47:17 +020099 bool (*filter)(struct dma_chan *chan, void *arg);
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +0000100};
101
Simon Horman973ed3a2011-06-21 08:00:10 +0900102struct tmio_mmc_host;
103
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100104/*
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200105 * data for the MMC controller
106 */
107struct tmio_mmc_data {
Magnus Damm707f0b22010-02-17 16:38:14 +0900108 unsigned int hclk;
Yusuke Godab741d442010-02-17 16:37:55 +0900109 unsigned long capabilities;
Guennadi Liakhovetski02cb3222012-05-23 10:44:37 +0200110 unsigned long capabilities2;
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +0000111 unsigned long flags;
Kuninori Morimoto3b159a62013-11-20 00:30:55 -0800112 unsigned long bus_shift;
Guennadi Liakhovetskia2b14dc2010-05-19 18:37:25 +0000113 u32 ocr_mask; /* available voltages */
Guennadi Liakhovetski42a45332010-05-19 18:34:11 +0000114 struct tmio_mmc_dma *dma;
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +0000115 struct device *dev;
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +0100116 unsigned int cd_gpio;
Chris Ball9d731e72013-09-06 07:29:05 -0400117 void (*set_pwr)(struct platform_device *host, int state);
Ian Molton64e88672010-01-06 13:51:48 +0100118 void (*set_clk_div)(struct platform_device *host, int state);
Simon Horman973ed3a2011-06-21 08:00:10 +0900119 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
Guennadi Liakhovetski8c102a92012-06-20 19:10:31 +0200120 /* clock management callbacks */
121 int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
122 void (*clk_disable)(struct platform_device *pdev);
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200123};
124
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +0100125/*
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100126 * data for the NAND controller
127 */
128struct tmio_nand_data {
129 struct nand_bbt_descr *badblock_pattern;
130 struct mtd_partition *partition;
131 unsigned int num_partitions;
132};
133
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -0700134#define FBIO_TMIO_ACC_WRITE 0x7C639300
135#define FBIO_TMIO_ACC_SYNC 0x7C639301
136
137struct tmio_fb_data {
138 int (*lcd_set_power)(struct platform_device *fb_dev,
139 bool on);
140 int (*lcd_mode)(struct platform_device *fb_dev,
141 const struct fb_videomode *mode);
142 int num_modes;
143 struct fb_videomode *modes;
144
145 /* in mm: size of screen */
146 int height;
147 int width;
148};
149
150
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100151#endif