| Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009-2010 Pengutronix |
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> |
| 4 | * Juergen Beisert <j.beisert@pengutronix.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it under |
| 7 | * the terms of the GNU General Public License version 2 as published by the |
| 8 | * Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/err.h> |
| 13 | #include <linux/kernel.h> |
| 14 | |
| 15 | #include <asm/hardware/cache-l2x0.h> |
| 16 | |
| 17 | #include <mach/hardware.h> |
| 18 | |
| 19 | static int mxc_init_l2x0(void) |
| 20 | { |
| 21 | void __iomem *l2x0_base; |
| 22 | void __iomem *clkctl_base; |
| 23 | |
| 24 | if (!cpu_is_mx31() && !cpu_is_mx35()) |
| 25 | return 0; |
| 26 | |
| 27 | /* |
| 28 | * First of all, we must repair broken chip settings. There are some |
| 29 | * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These |
| 30 | * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. |
| 31 | * Workaraound is to setup the correct register setting prior enabling the |
| 32 | * L2 cache. This should not hurt already working CPUs, as they are using the |
| 33 | * same value. |
| 34 | */ |
| 35 | #define L2_MEM_VAL 0x10 |
| 36 | |
| 37 | clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); |
| 38 | if (clkctl_base != NULL) { |
| 39 | writel(0x00000515, clkctl_base + L2_MEM_VAL); |
| 40 | iounmap(clkctl_base); |
| 41 | } else { |
| 42 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); |
| 43 | } |
| 44 | |
| 45 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); |
| 46 | if (IS_ERR(l2x0_base)) { |
| 47 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", |
| 48 | PTR_ERR(l2x0_base)); |
| 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); |
| 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | arch_initcall(mxc_init_l2x0); |