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Hanumath Prasad008f8a22010-08-19 12:06:32 +01001/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/gpio.h>
10#include <linux/amba/bus.h>
11#include <linux/amba/mmci.h>
12#include <linux/mmc/host.h>
13#include <linux/platform_device.h>
14
Linus Walleij4b4f7572011-02-15 15:01:35 +010015#include <asm/mach-types.h>
Linus Walleij5d7b8462010-10-14 13:57:59 +020016#include <plat/ste_dma40.h>
Hanumath Prasad008f8a22010-08-19 12:06:32 +010017#include <mach/devices.h>
18#include <mach/hardware.h>
19
Rabin Vincentfbf1eadf2010-09-29 19:46:32 +053020#include "devices-db8500.h"
Hanumath Prasad008f8a22010-08-19 12:06:32 +010021#include "board-mop500.h"
Linus Walleij5d7b8462010-10-14 13:57:59 +020022#include "ste-dma40-db8500.h"
Hanumath Prasad008f8a22010-08-19 12:06:32 +010023
Hanumath Prasad008f8a22010-08-19 12:06:32 +010024/*
Rabin Vincentb8410a12010-08-09 19:18:17 +053025 * SDI 0 (MicroSD slot)
26 */
27
28/* MMCIPOWER bits */
29#define MCI_DATA2DIREN (1 << 2)
30#define MCI_CMDDIREN (1 << 3)
31#define MCI_DATA0DIREN (1 << 4)
32#define MCI_DATA31DIREN (1 << 5)
33#define MCI_FBCLKEN (1 << 7)
34
35static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
36 unsigned char power_mode)
37{
38 if (power_mode == MMC_POWER_UP)
Linus Walleij1bde6682010-09-09 22:29:34 +020039 gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
Rabin Vincentb8410a12010-08-09 19:18:17 +053040 else if (power_mode == MMC_POWER_OFF)
Linus Walleij1bde6682010-09-09 22:29:34 +020041 gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
Rabin Vincentb8410a12010-08-09 19:18:17 +053042
43 return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
44 MCI_DATA2DIREN | MCI_DATA31DIREN;
45}
46
Linus Walleij5d7b8462010-10-14 13:57:59 +020047#ifdef CONFIG_STE_DMA40
48struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
49 .mode = STEDMA40_MODE_LOGICAL,
50 .dir = STEDMA40_PERIPH_TO_MEM,
51 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
52 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
53 .src_info.data_width = STEDMA40_WORD_WIDTH,
54 .dst_info.data_width = STEDMA40_WORD_WIDTH,
55};
56
57static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
58 .mode = STEDMA40_MODE_LOGICAL,
59 .dir = STEDMA40_MEM_TO_PERIPH,
60 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
61 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
62 .src_info.data_width = STEDMA40_WORD_WIDTH,
63 .dst_info.data_width = STEDMA40_WORD_WIDTH,
64};
65#endif
66
Rabin Vincentb8410a12010-08-09 19:18:17 +053067static struct mmci_platform_data mop500_sdi0_data = {
68 .vdd_handler = mop500_sdi0_vdd_handler,
69 .ocr_mask = MMC_VDD_29_30,
70 .f_max = 100000000,
71 .capabilities = MMC_CAP_4_BIT_DATA,
Rabin Vincentb8410a12010-08-09 19:18:17 +053072 .gpio_wp = -1,
Linus Walleij5d7b8462010-10-14 13:57:59 +020073#ifdef CONFIG_STE_DMA40
74 .dma_filter = stedma40_filter,
75 .dma_rx_param = &mop500_sdi0_dma_cfg_rx,
76 .dma_tx_param = &mop500_sdi0_dma_cfg_tx,
77#endif
Rabin Vincentb8410a12010-08-09 19:18:17 +053078};
79
Linus Walleij4b4f7572011-02-15 15:01:35 +010080/* GPIO pins used by the sdi0 level shifter */
81static int sdi0_en = -1;
82static int sdi0_vsel = -1;
83
84static void sdi0_configure(void)
Rabin Vincentb8410a12010-08-09 19:18:17 +053085{
86 int ret;
87
Linus Walleij4b4f7572011-02-15 15:01:35 +010088 ret = gpio_request(sdi0_en, "level shifter enable");
Rabin Vincentb8410a12010-08-09 19:18:17 +053089 if (!ret)
Linus Walleij4b4f7572011-02-15 15:01:35 +010090 ret = gpio_request(sdi0_vsel,
91 "level shifter 1v8-3v select");
92
93 if (ret) {
94 pr_warning("unable to config sdi0 gpios for level shifter.\n");
Rabin Vincentb8410a12010-08-09 19:18:17 +053095 return;
Linus Walleij4b4f7572011-02-15 15:01:35 +010096 }
Rabin Vincentb8410a12010-08-09 19:18:17 +053097
Linus Walleij4b4f7572011-02-15 15:01:35 +010098 /* Select the default 2.9V and enable level shifter */
99 gpio_direction_output(sdi0_vsel, 0);
100 gpio_direction_output(sdi0_en, 1);
Rabin Vincentb8410a12010-08-09 19:18:17 +0530101
Linus Walleij72930312011-03-24 16:13:13 +0100102 /* Add the device, force v2 to subrevision 1 */
103 if (cpu_is_u8500v2())
104 db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
105 else
106 db8500_add_sdi0(&mop500_sdi0_data, 0);
Rabin Vincentb8410a12010-08-09 19:18:17 +0530107}
108
Linus Walleij4b4f7572011-02-15 15:01:35 +0100109void mop500_sdi_tc35892_init(void)
110{
111 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
112 sdi0_en = GPIO_SDMMC_EN;
113 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
114 sdi0_configure();
115}
116
Rabin Vincentb8410a12010-08-09 19:18:17 +0530117/*
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100118 * SDI 2 (POP eMMC, not on DB8500ed)
119 */
120
Linus Walleij5d7b8462010-10-14 13:57:59 +0200121#ifdef CONFIG_STE_DMA40
122struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
123 .mode = STEDMA40_MODE_LOGICAL,
124 .dir = STEDMA40_PERIPH_TO_MEM,
125 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
126 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
127 .src_info.data_width = STEDMA40_WORD_WIDTH,
128 .dst_info.data_width = STEDMA40_WORD_WIDTH,
129};
130
131static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
132 .mode = STEDMA40_MODE_LOGICAL,
133 .dir = STEDMA40_MEM_TO_PERIPH,
134 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
135 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
136 .src_info.data_width = STEDMA40_WORD_WIDTH,
137 .dst_info.data_width = STEDMA40_WORD_WIDTH,
138};
139#endif
140
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100141static struct mmci_platform_data mop500_sdi2_data = {
142 .ocr_mask = MMC_VDD_165_195,
143 .f_max = 100000000,
144 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
145 .gpio_cd = -1,
146 .gpio_wp = -1,
Linus Walleij5d7b8462010-10-14 13:57:59 +0200147#ifdef CONFIG_STE_DMA40
148 .dma_filter = stedma40_filter,
149 .dma_rx_param = &mop500_sdi2_dma_cfg_rx,
150 .dma_tx_param = &mop500_sdi2_dma_cfg_tx,
151#endif
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100152};
153
154/*
155 * SDI 4 (on-board eMMC)
156 */
157
Linus Walleij5d7b8462010-10-14 13:57:59 +0200158#ifdef CONFIG_STE_DMA40
159struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
160 .mode = STEDMA40_MODE_LOGICAL,
161 .dir = STEDMA40_PERIPH_TO_MEM,
162 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
163 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
164 .src_info.data_width = STEDMA40_WORD_WIDTH,
165 .dst_info.data_width = STEDMA40_WORD_WIDTH,
166};
167
168static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
169 .mode = STEDMA40_MODE_LOGICAL,
170 .dir = STEDMA40_MEM_TO_PERIPH,
171 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
172 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
173 .src_info.data_width = STEDMA40_WORD_WIDTH,
174 .dst_info.data_width = STEDMA40_WORD_WIDTH,
175};
176#endif
177
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100178static struct mmci_platform_data mop500_sdi4_data = {
179 .ocr_mask = MMC_VDD_29_30,
180 .f_max = 100000000,
181 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
182 MMC_CAP_MMC_HIGHSPEED,
183 .gpio_cd = -1,
184 .gpio_wp = -1,
Linus Walleij5d7b8462010-10-14 13:57:59 +0200185#ifdef CONFIG_STE_DMA40
186 .dma_filter = stedma40_filter,
187 .dma_rx_param = &mop500_sdi4_dma_cfg_rx,
188 .dma_tx_param = &mop500_sdi4_dma_cfg_tx,
189#endif
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100190};
191
Linus Walleijedaa86a2010-12-02 12:05:18 +0100192void __init mop500_sdi_init(void)
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100193{
Linus Walleij72930312011-03-24 16:13:13 +0100194 u32 periphid = 0;
195
196 /* v2 has a new version of this block that need to be forced */
197 if (cpu_is_u8500v2())
198 periphid = 0x10480180;
Bibek Basu4bc3a692011-02-15 10:46:59 +0100199 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
200 if (!cpu_is_u8500v10())
201 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
Linus Walleij72930312011-03-24 16:13:13 +0100202 db8500_add_sdi2(&mop500_sdi2_data, periphid);
Bibek Basu4bc3a692011-02-15 10:46:59 +0100203
204 /* On-board eMMC */
Linus Walleij72930312011-03-24 16:13:13 +0100205 db8500_add_sdi4(&mop500_sdi4_data, periphid);
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100206
Linus Walleij4b4f7572011-02-15 15:01:35 +0100207 if (machine_is_hrefv60()) {
208 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
209 sdi0_en = HREFV60_SDMMC_EN_GPIO;
210 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
211 sdi0_configure();
212 }
Linus Walleijedaa86a2010-12-02 12:05:18 +0100213 /*
Linus Walleij4b4f7572011-02-15 15:01:35 +0100214 * On boards with the TC35892 GPIO expander, sdi0 will finally
215 * be added when the TC35892 initializes and calls
Linus Walleijedaa86a2010-12-02 12:05:18 +0100216 * mop500_sdi_tc35892_init() above.
217 */
Hanumath Prasad008f8a22010-08-19 12:06:32 +0100218}